1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Analog Devices AXI PWM generator 4 * 5 * Copyright 2024 Analog Devices Inc. 6 * Copyright 2024 Baylibre SAS 7 * 8 * Device docs: https://analogdevicesinc.github.io/hdl/library/axi_pwm_gen/index.html 9 * 10 * Limitations: 11 * - The writes to registers for period and duty are shadowed until 12 * LOAD_CONFIG is written to AXI_PWMGEN_REG_CONFIG, at which point 13 * they take effect. 14 * - Writing LOAD_CONFIG also has the effect of re-synchronizing all 15 * enabled channels, which could cause glitching on other channels. It 16 * is therefore expected that channels are assigned harmonic periods 17 * and all have a single user coordinating this. 18 * - Supports normal polarity. Does not support changing polarity. 19 * - On disable, the PWM output becomes low (inactive). 20 */ 21 #include <linux/bits.h> 22 #include <linux/clk.h> 23 #include <linux/err.h> 24 #include <linux/fpga/adi-axi-common.h> 25 #include <linux/io.h> 26 #include <linux/module.h> 27 #include <linux/platform_device.h> 28 #include <linux/pwm.h> 29 #include <linux/regmap.h> 30 #include <linux/slab.h> 31 32 #define AXI_PWMGEN_REG_CORE_VERSION 0x00 33 #define AXI_PWMGEN_REG_ID 0x04 34 #define AXI_PWMGEN_REG_SCRATCHPAD 0x08 35 #define AXI_PWMGEN_REG_CORE_MAGIC 0x0C 36 #define AXI_PWMGEN_REG_CONFIG 0x10 37 #define AXI_PWMGEN_REG_NPWM 0x14 38 #define AXI_PWMGEN_CHX_PERIOD(ch) (0x40 + (4 * (ch))) 39 #define AXI_PWMGEN_CHX_DUTY(ch) (0x80 + (4 * (ch))) 40 #define AXI_PWMGEN_CHX_OFFSET(ch) (0xC0 + (4 * (ch))) 41 #define AXI_PWMGEN_REG_CORE_MAGIC_VAL 0x601A3471 /* Identification number to test during setup */ 42 #define AXI_PWMGEN_LOAD_CONFIG BIT(1) 43 #define AXI_PWMGEN_REG_CONFIG_RESET BIT(0) 44 45 struct axi_pwmgen_ddata { 46 struct regmap *regmap; 47 unsigned long clk_rate_hz; 48 }; 49 50 static const struct regmap_config axi_pwmgen_regmap_config = { 51 .reg_bits = 32, 52 .reg_stride = 4, 53 .val_bits = 32, 54 .max_register = 0xFC, 55 }; 56 57 static int axi_pwmgen_apply(struct pwm_chip *chip, struct pwm_device *pwm, 58 const struct pwm_state *state) 59 { 60 struct axi_pwmgen_ddata *ddata = pwmchip_get_drvdata(chip); 61 unsigned int ch = pwm->hwpwm; 62 struct regmap *regmap = ddata->regmap; 63 u64 period_cnt, duty_cnt; 64 int ret; 65 66 if (state->polarity != PWM_POLARITY_NORMAL) 67 return -EINVAL; 68 69 if (state->enabled) { 70 period_cnt = mul_u64_u64_div_u64(state->period, ddata->clk_rate_hz, NSEC_PER_SEC); 71 if (period_cnt > UINT_MAX) 72 period_cnt = UINT_MAX; 73 74 if (period_cnt == 0) 75 return -EINVAL; 76 77 ret = regmap_write(regmap, AXI_PWMGEN_CHX_PERIOD(ch), period_cnt); 78 if (ret) 79 return ret; 80 81 duty_cnt = mul_u64_u64_div_u64(state->duty_cycle, ddata->clk_rate_hz, NSEC_PER_SEC); 82 if (duty_cnt > UINT_MAX) 83 duty_cnt = UINT_MAX; 84 85 ret = regmap_write(regmap, AXI_PWMGEN_CHX_DUTY(ch), duty_cnt); 86 if (ret) 87 return ret; 88 } else { 89 ret = regmap_write(regmap, AXI_PWMGEN_CHX_PERIOD(ch), 0); 90 if (ret) 91 return ret; 92 93 ret = regmap_write(regmap, AXI_PWMGEN_CHX_DUTY(ch), 0); 94 if (ret) 95 return ret; 96 } 97 98 return regmap_write(regmap, AXI_PWMGEN_REG_CONFIG, AXI_PWMGEN_LOAD_CONFIG); 99 } 100 101 static int axi_pwmgen_get_state(struct pwm_chip *chip, struct pwm_device *pwm, 102 struct pwm_state *state) 103 { 104 struct axi_pwmgen_ddata *ddata = pwmchip_get_drvdata(chip); 105 struct regmap *regmap = ddata->regmap; 106 unsigned int ch = pwm->hwpwm; 107 u32 cnt; 108 int ret; 109 110 ret = regmap_read(regmap, AXI_PWMGEN_CHX_PERIOD(ch), &cnt); 111 if (ret) 112 return ret; 113 114 state->enabled = cnt != 0; 115 116 state->period = DIV_ROUND_UP_ULL((u64)cnt * NSEC_PER_SEC, ddata->clk_rate_hz); 117 118 ret = regmap_read(regmap, AXI_PWMGEN_CHX_DUTY(ch), &cnt); 119 if (ret) 120 return ret; 121 122 state->duty_cycle = DIV_ROUND_UP_ULL((u64)cnt * NSEC_PER_SEC, ddata->clk_rate_hz); 123 124 state->polarity = PWM_POLARITY_NORMAL; 125 126 return 0; 127 } 128 129 static const struct pwm_ops axi_pwmgen_pwm_ops = { 130 .apply = axi_pwmgen_apply, 131 .get_state = axi_pwmgen_get_state, 132 }; 133 134 static int axi_pwmgen_setup(struct regmap *regmap, struct device *dev) 135 { 136 int ret; 137 u32 val; 138 139 ret = regmap_read(regmap, AXI_PWMGEN_REG_CORE_MAGIC, &val); 140 if (ret) 141 return ret; 142 143 if (val != AXI_PWMGEN_REG_CORE_MAGIC_VAL) 144 return dev_err_probe(dev, -ENODEV, 145 "failed to read expected value from register: got %08x, expected %08x\n", 146 val, AXI_PWMGEN_REG_CORE_MAGIC_VAL); 147 148 ret = regmap_read(regmap, AXI_PWMGEN_REG_CORE_VERSION, &val); 149 if (ret) 150 return ret; 151 152 if (ADI_AXI_PCORE_VER_MAJOR(val) != 2) { 153 return dev_err_probe(dev, -ENODEV, "Unsupported peripheral version %u.%u.%u\n", 154 ADI_AXI_PCORE_VER_MAJOR(val), 155 ADI_AXI_PCORE_VER_MINOR(val), 156 ADI_AXI_PCORE_VER_PATCH(val)); 157 } 158 159 /* Enable the core */ 160 ret = regmap_clear_bits(regmap, AXI_PWMGEN_REG_CONFIG, AXI_PWMGEN_REG_CONFIG_RESET); 161 if (ret) 162 return ret; 163 164 ret = regmap_read(regmap, AXI_PWMGEN_REG_NPWM, &val); 165 if (ret) 166 return ret; 167 168 /* Return the number of PWMs */ 169 return val; 170 } 171 172 static int axi_pwmgen_probe(struct platform_device *pdev) 173 { 174 struct device *dev = &pdev->dev; 175 struct regmap *regmap; 176 struct pwm_chip *chip; 177 struct axi_pwmgen_ddata *ddata; 178 struct clk *clk; 179 void __iomem *io_base; 180 int ret; 181 182 io_base = devm_platform_ioremap_resource(pdev, 0); 183 if (IS_ERR(io_base)) 184 return PTR_ERR(io_base); 185 186 regmap = devm_regmap_init_mmio(dev, io_base, &axi_pwmgen_regmap_config); 187 if (IS_ERR(regmap)) 188 return dev_err_probe(dev, PTR_ERR(regmap), 189 "failed to init register map\n"); 190 191 ret = axi_pwmgen_setup(regmap, dev); 192 if (ret < 0) 193 return ret; 194 195 chip = devm_pwmchip_alloc(dev, ret, sizeof(*ddata)); 196 if (IS_ERR(chip)) 197 return PTR_ERR(chip); 198 ddata = pwmchip_get_drvdata(chip); 199 ddata->regmap = regmap; 200 201 clk = devm_clk_get_enabled(dev, NULL); 202 if (IS_ERR(clk)) 203 return dev_err_probe(dev, PTR_ERR(clk), "failed to get clock\n"); 204 205 ret = devm_clk_rate_exclusive_get(dev, clk); 206 if (ret) 207 return dev_err_probe(dev, ret, "failed to get exclusive rate\n"); 208 209 ddata->clk_rate_hz = clk_get_rate(clk); 210 if (!ddata->clk_rate_hz || ddata->clk_rate_hz > NSEC_PER_SEC) 211 return dev_err_probe(dev, -EINVAL, 212 "Invalid clock rate: %lu\n", ddata->clk_rate_hz); 213 214 chip->ops = &axi_pwmgen_pwm_ops; 215 chip->atomic = true; 216 217 ret = devm_pwmchip_add(dev, chip); 218 if (ret) 219 return dev_err_probe(dev, ret, "could not add PWM chip\n"); 220 221 return 0; 222 } 223 224 static const struct of_device_id axi_pwmgen_ids[] = { 225 { .compatible = "adi,axi-pwmgen-2.00.a" }, 226 { } 227 }; 228 MODULE_DEVICE_TABLE(of, axi_pwmgen_ids); 229 230 static struct platform_driver axi_pwmgen_driver = { 231 .driver = { 232 .name = "axi-pwmgen", 233 .of_match_table = axi_pwmgen_ids, 234 }, 235 .probe = axi_pwmgen_probe, 236 }; 237 module_platform_driver(axi_pwmgen_driver); 238 239 MODULE_LICENSE("GPL"); 240 MODULE_AUTHOR("Sergiu Cuciurean <sergiu.cuciurean@analog.com>"); 241 MODULE_AUTHOR("Trevor Gamblin <tgamblin@baylibre.com>"); 242 MODULE_DESCRIPTION("Driver for the Analog Devices AXI PWM generator"); 243