xref: /linux/Documentation/devicetree/bindings/display/bridge/renesas,dsi-csi2-tx.yaml (revision 7340c6df49df1b261892d287444c255d0a378063) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/bridge/renesas,dsi-csi2-tx.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Renesas R-Car MIPI DSI/CSI-2 Encoder
8
9maintainers:
10  - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
11
12description: |
13  This binding describes the MIPI DSI/CSI-2 encoder embedded in the Renesas
14  R-Car Gen4 SoCs. The encoder can operate in either DSI or CSI-2 mode, with up
15  to four data lanes.
16
17properties:
18  compatible:
19    enum:
20      - renesas,r8a779a0-dsi-csi2-tx    # for V3U
21      - renesas,r8a779g0-dsi-csi2-tx    # for V4H
22
23  reg:
24    maxItems: 1
25
26  clocks:
27    items:
28      - description: Functional clock
29      - description: DSI (and CSI-2) functional clock
30      - description: PLL reference clock
31
32  clock-names:
33    items:
34      - const: fck
35      - const: dsi
36      - const: pll
37
38  power-domains:
39    maxItems: 1
40
41  resets:
42    maxItems: 1
43
44  ports:
45    $ref: /schemas/graph.yaml#/properties/ports
46
47    properties:
48      port@0:
49        $ref: /schemas/graph.yaml#/properties/port
50        description: Parallel input port
51
52      port@1:
53        $ref: /schemas/graph.yaml#/$defs/port-base
54        unevaluatedProperties: false
55        description: DSI/CSI-2 output port
56
57        properties:
58          endpoint:
59            $ref: /schemas/media/video-interfaces.yaml#
60            unevaluatedProperties: false
61
62            properties:
63              data-lanes:
64                minItems: 1
65                maxItems: 4
66
67            required:
68              - data-lanes
69
70    required:
71      - port@0
72      - port@1
73
74required:
75  - compatible
76  - reg
77  - clocks
78  - power-domains
79  - resets
80  - ports
81
82additionalProperties: false
83
84examples:
85  - |
86    #include <dt-bindings/clock/r8a779a0-cpg-mssr.h>
87    #include <dt-bindings/power/r8a779a0-sysc.h>
88
89    dsi0: dsi-encoder@fed80000 {
90        compatible = "renesas,r8a779a0-dsi-csi2-tx";
91        reg = <0xfed80000 0x10000>;
92        power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
93        clocks = <&cpg CPG_MOD 415>,
94                 <&cpg CPG_CORE R8A779A0_CLK_DSI>,
95                 <&cpg CPG_CORE R8A779A0_CLK_CP>;
96        clock-names = "fck", "dsi", "pll";
97        resets = <&cpg 415>;
98
99        ports {
100            #address-cells = <1>;
101            #size-cells = <0>;
102
103            port@0 {
104                reg = <0>;
105                dsi0_in: endpoint {
106                    remote-endpoint = <&du_out_dsi0>;
107                };
108            };
109
110            port@1 {
111                reg = <1>;
112                dsi0_out: endpoint {
113                    data-lanes = <1 2>;
114                    remote-endpoint = <&sn65dsi86_in>;
115                };
116            };
117        };
118    };
119...
120