1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * ADF4350/ADF4351 SPI Wideband Synthesizer driver 4 * 5 * Copyright 2012-2013 Analog Devices Inc. 6 */ 7 8 #include <linux/device.h> 9 #include <linux/kernel.h> 10 #include <linux/mod_devicetable.h> 11 #include <linux/module.h> 12 #include <linux/property.h> 13 #include <linux/slab.h> 14 #include <linux/sysfs.h> 15 #include <linux/spi/spi.h> 16 #include <linux/regulator/consumer.h> 17 #include <linux/err.h> 18 #include <linux/gcd.h> 19 #include <linux/gpio/consumer.h> 20 #include <asm/div64.h> 21 #include <linux/clk.h> 22 #include <linux/clk-provider.h> 23 24 #include <linux/iio/iio.h> 25 #include <linux/iio/sysfs.h> 26 #include <linux/iio/frequency/adf4350.h> 27 28 enum { 29 ADF4350_FREQ, 30 ADF4350_FREQ_REFIN, 31 ADF4350_FREQ_RESOLUTION, 32 ADF4350_PWRDOWN, 33 }; 34 35 struct adf4350_state { 36 struct spi_device *spi; 37 struct gpio_desc *lock_detect_gpiod; 38 struct adf4350_platform_data *pdata; 39 struct clk *clk; 40 struct clk *clkout; 41 const char *clk_out_name; 42 struct clk_hw hw; 43 unsigned long clkin; 44 unsigned long chspc; /* Channel Spacing */ 45 unsigned long fpfd; /* Phase Frequency Detector */ 46 unsigned long min_out_freq; 47 unsigned r0_fract; 48 unsigned r0_int; 49 unsigned r1_mod; 50 unsigned r4_rf_div_sel; 51 unsigned long regs[6]; 52 unsigned long regs_hw[6]; 53 unsigned long long freq_req; 54 /* 55 * Lock to protect the state of the device from potential concurrent 56 * writes. The device is configured via a sequence of SPI writes, 57 * and this lock is meant to prevent the start of another sequence 58 * before another one has finished. 59 */ 60 struct mutex lock; 61 /* 62 * DMA (thus cache coherency maintenance) may require that 63 * transfer buffers live in their own cache lines. 64 */ 65 __be32 val __aligned(IIO_DMA_MINALIGN); 66 }; 67 68 #define to_adf4350_state(_hw) container_of(_hw, struct adf4350_state, hw) 69 70 static struct adf4350_platform_data default_pdata = { 71 .channel_spacing = 10000, 72 .r2_user_settings = ADF4350_REG2_PD_POLARITY_POS | 73 ADF4350_REG2_CHARGE_PUMP_CURR_uA(2500), 74 .r3_user_settings = ADF4350_REG3_12BIT_CLKDIV_MODE(0), 75 .r4_user_settings = ADF4350_REG4_OUTPUT_PWR(3) | 76 ADF4350_REG4_MUTE_TILL_LOCK_EN, 77 }; 78 79 static int adf4350_sync_config(struct adf4350_state *st) 80 { 81 int ret, i, doublebuf = 0; 82 83 for (i = ADF4350_REG5; i >= ADF4350_REG0; i--) { 84 if ((st->regs_hw[i] != st->regs[i]) || 85 ((i == ADF4350_REG0) && doublebuf)) { 86 switch (i) { 87 case ADF4350_REG1: 88 case ADF4350_REG4: 89 doublebuf = 1; 90 break; 91 } 92 93 st->val = cpu_to_be32(st->regs[i] | i); 94 ret = spi_write(st->spi, &st->val, 4); 95 if (ret < 0) 96 return ret; 97 st->regs_hw[i] = st->regs[i]; 98 dev_dbg(&st->spi->dev, "[%d] 0x%X\n", 99 i, (u32)st->regs[i] | i); 100 } 101 } 102 return 0; 103 } 104 105 static int adf4350_reg_access(struct iio_dev *indio_dev, 106 unsigned reg, unsigned writeval, 107 unsigned *readval) 108 { 109 struct adf4350_state *st = iio_priv(indio_dev); 110 int ret; 111 112 if (reg > ADF4350_REG5) 113 return -EINVAL; 114 115 mutex_lock(&st->lock); 116 if (readval == NULL) { 117 st->regs[reg] = writeval & ~(BIT(0) | BIT(1) | BIT(2)); 118 ret = adf4350_sync_config(st); 119 } else { 120 *readval = st->regs_hw[reg]; 121 ret = 0; 122 } 123 mutex_unlock(&st->lock); 124 125 return ret; 126 } 127 128 static int adf4350_tune_r_cnt(struct adf4350_state *st, unsigned short r_cnt) 129 { 130 struct adf4350_platform_data *pdata = st->pdata; 131 132 do { 133 r_cnt++; 134 st->fpfd = (st->clkin * (pdata->ref_doubler_en ? 2 : 1)) / 135 (r_cnt * (pdata->ref_div2_en ? 2 : 1)); 136 } while (st->fpfd > ADF4350_MAX_FREQ_PFD); 137 138 return r_cnt; 139 } 140 141 static int adf4350_set_freq(struct adf4350_state *st, unsigned long long freq) 142 { 143 struct adf4350_platform_data *pdata = st->pdata; 144 u64 tmp; 145 u32 div_gcd, prescaler, chspc; 146 u16 mdiv, r_cnt = 0; 147 u8 band_sel_div; 148 149 if (freq > ADF4350_MAX_OUT_FREQ || freq < st->min_out_freq) 150 return -EINVAL; 151 152 if (freq > ADF4350_MAX_FREQ_45_PRESC) { 153 prescaler = ADF4350_REG1_PRESCALER; 154 mdiv = 75; 155 } else { 156 prescaler = 0; 157 mdiv = 23; 158 } 159 160 st->r4_rf_div_sel = 0; 161 162 while (freq < ADF4350_MIN_VCO_FREQ) { 163 freq <<= 1; 164 st->r4_rf_div_sel++; 165 } 166 167 /* 168 * Allow a predefined reference division factor 169 * if not set, compute our own 170 */ 171 if (pdata->ref_div_factor) 172 r_cnt = pdata->ref_div_factor - 1; 173 174 chspc = st->chspc; 175 176 do { 177 do { 178 do { 179 r_cnt = adf4350_tune_r_cnt(st, r_cnt); 180 st->r1_mod = st->fpfd / chspc; 181 if (r_cnt > ADF4350_MAX_R_CNT) { 182 /* try higher spacing values */ 183 chspc++; 184 r_cnt = 0; 185 } 186 } while ((st->r1_mod > ADF4350_MAX_MODULUS) && r_cnt); 187 } while (r_cnt == 0); 188 189 tmp = freq * (u64)st->r1_mod + (st->fpfd >> 1); 190 do_div(tmp, st->fpfd); /* Div round closest (n + d/2)/d */ 191 st->r0_fract = do_div(tmp, st->r1_mod); 192 st->r0_int = tmp; 193 } while (mdiv > st->r0_int); 194 195 band_sel_div = DIV_ROUND_UP(st->fpfd, ADF4350_MAX_BANDSEL_CLK); 196 197 if (st->r0_fract && st->r1_mod) { 198 div_gcd = gcd(st->r1_mod, st->r0_fract); 199 st->r1_mod /= div_gcd; 200 st->r0_fract /= div_gcd; 201 } else { 202 st->r0_fract = 0; 203 st->r1_mod = 1; 204 } 205 206 dev_dbg(&st->spi->dev, "VCO: %llu Hz, PFD %lu Hz\n" 207 "REF_DIV %d, R0_INT %d, R0_FRACT %d\n" 208 "R1_MOD %d, RF_DIV %d\nPRESCALER %s, BAND_SEL_DIV %d\n", 209 freq, st->fpfd, r_cnt, st->r0_int, st->r0_fract, st->r1_mod, 210 1 << st->r4_rf_div_sel, prescaler ? "8/9" : "4/5", 211 band_sel_div); 212 213 st->regs[ADF4350_REG0] = ADF4350_REG0_INT(st->r0_int) | 214 ADF4350_REG0_FRACT(st->r0_fract); 215 216 st->regs[ADF4350_REG1] = ADF4350_REG1_PHASE(1) | 217 ADF4350_REG1_MOD(st->r1_mod) | 218 prescaler; 219 220 st->regs[ADF4350_REG2] = 221 ADF4350_REG2_10BIT_R_CNT(r_cnt) | 222 ADF4350_REG2_DOUBLE_BUFF_EN | 223 (pdata->ref_doubler_en ? ADF4350_REG2_RMULT2_EN : 0) | 224 (pdata->ref_div2_en ? ADF4350_REG2_RDIV2_EN : 0) | 225 (pdata->r2_user_settings & (ADF4350_REG2_PD_POLARITY_POS | 226 ADF4350_REG2_LDP_6ns | ADF4350_REG2_LDF_INT_N | 227 ADF4350_REG2_CHARGE_PUMP_CURR_uA(5000) | 228 ADF4350_REG2_MUXOUT(0x7) | ADF4350_REG2_NOISE_MODE(0x3))); 229 230 st->regs[ADF4350_REG3] = pdata->r3_user_settings & 231 (ADF4350_REG3_12BIT_CLKDIV(0xFFF) | 232 ADF4350_REG3_12BIT_CLKDIV_MODE(0x3) | 233 ADF4350_REG3_12BIT_CSR_EN | 234 ADF4351_REG3_CHARGE_CANCELLATION_EN | 235 ADF4351_REG3_ANTI_BACKLASH_3ns_EN | 236 ADF4351_REG3_BAND_SEL_CLOCK_MODE_HIGH); 237 238 st->regs[ADF4350_REG4] = 239 ADF4350_REG4_FEEDBACK_FUND | 240 ADF4350_REG4_RF_DIV_SEL(st->r4_rf_div_sel) | 241 ADF4350_REG4_8BIT_BAND_SEL_CLKDIV(band_sel_div) | 242 ADF4350_REG4_RF_OUT_EN | 243 (pdata->r4_user_settings & 244 (ADF4350_REG4_OUTPUT_PWR(0x3) | 245 ADF4350_REG4_AUX_OUTPUT_PWR(0x3) | 246 ADF4350_REG4_AUX_OUTPUT_EN | 247 ADF4350_REG4_AUX_OUTPUT_FUND | 248 ADF4350_REG4_MUTE_TILL_LOCK_EN)); 249 250 st->regs[ADF4350_REG5] = ADF4350_REG5_LD_PIN_MODE_DIGITAL; 251 st->freq_req = freq; 252 253 return adf4350_sync_config(st); 254 } 255 256 static ssize_t adf4350_write(struct iio_dev *indio_dev, 257 uintptr_t private, 258 const struct iio_chan_spec *chan, 259 const char *buf, size_t len) 260 { 261 struct adf4350_state *st = iio_priv(indio_dev); 262 unsigned long long readin; 263 unsigned long tmp; 264 int ret; 265 266 ret = kstrtoull(buf, 10, &readin); 267 if (ret) 268 return ret; 269 270 mutex_lock(&st->lock); 271 switch ((u32)private) { 272 case ADF4350_FREQ: 273 ret = adf4350_set_freq(st, readin); 274 break; 275 case ADF4350_FREQ_REFIN: 276 if (readin > ADF4350_MAX_FREQ_REFIN) { 277 ret = -EINVAL; 278 break; 279 } 280 281 if (st->clk) { 282 tmp = clk_round_rate(st->clk, readin); 283 if (tmp != readin) { 284 ret = -EINVAL; 285 break; 286 } 287 ret = clk_set_rate(st->clk, tmp); 288 if (ret < 0) 289 break; 290 } 291 st->clkin = readin; 292 ret = adf4350_set_freq(st, st->freq_req); 293 break; 294 case ADF4350_FREQ_RESOLUTION: 295 if (readin == 0) 296 ret = -EINVAL; 297 else 298 st->chspc = readin; 299 break; 300 case ADF4350_PWRDOWN: 301 if (readin) 302 st->regs[ADF4350_REG2] |= ADF4350_REG2_POWER_DOWN_EN; 303 else 304 st->regs[ADF4350_REG2] &= ~ADF4350_REG2_POWER_DOWN_EN; 305 306 adf4350_sync_config(st); 307 break; 308 default: 309 ret = -EINVAL; 310 } 311 mutex_unlock(&st->lock); 312 313 return ret ? ret : len; 314 } 315 316 static ssize_t adf4350_read(struct iio_dev *indio_dev, 317 uintptr_t private, 318 const struct iio_chan_spec *chan, 319 char *buf) 320 { 321 struct adf4350_state *st = iio_priv(indio_dev); 322 unsigned long long val; 323 int ret = 0; 324 325 mutex_lock(&st->lock); 326 switch ((u32)private) { 327 case ADF4350_FREQ: 328 val = (u64)((st->r0_int * st->r1_mod) + st->r0_fract) * 329 (u64)st->fpfd; 330 do_div(val, st->r1_mod * (1 << st->r4_rf_div_sel)); 331 /* PLL unlocked? return error */ 332 if (st->lock_detect_gpiod) 333 if (!gpiod_get_value(st->lock_detect_gpiod)) { 334 dev_dbg(&st->spi->dev, "PLL un-locked\n"); 335 ret = -EBUSY; 336 } 337 break; 338 case ADF4350_FREQ_REFIN: 339 if (st->clk) 340 st->clkin = clk_get_rate(st->clk); 341 342 val = st->clkin; 343 break; 344 case ADF4350_FREQ_RESOLUTION: 345 val = st->chspc; 346 break; 347 case ADF4350_PWRDOWN: 348 val = !!(st->regs[ADF4350_REG2] & ADF4350_REG2_POWER_DOWN_EN); 349 break; 350 default: 351 ret = -EINVAL; 352 val = 0; 353 } 354 mutex_unlock(&st->lock); 355 356 return ret < 0 ? ret : sprintf(buf, "%llu\n", val); 357 } 358 359 #define _ADF4350_EXT_INFO(_name, _ident) { \ 360 .name = _name, \ 361 .read = adf4350_read, \ 362 .write = adf4350_write, \ 363 .private = _ident, \ 364 .shared = IIO_SEPARATE, \ 365 } 366 367 static const struct iio_chan_spec_ext_info adf4350_ext_info[] = { 368 /* Ideally we use IIO_CHAN_INFO_FREQUENCY, but there are 369 * values > 2^32 in order to support the entire frequency range 370 * in Hz. Using scale is a bit ugly. 371 */ 372 _ADF4350_EXT_INFO("frequency", ADF4350_FREQ), 373 _ADF4350_EXT_INFO("frequency_resolution", ADF4350_FREQ_RESOLUTION), 374 _ADF4350_EXT_INFO("refin_frequency", ADF4350_FREQ_REFIN), 375 _ADF4350_EXT_INFO("powerdown", ADF4350_PWRDOWN), 376 { }, 377 }; 378 379 static const struct iio_chan_spec adf4350_chan = { 380 .type = IIO_ALTVOLTAGE, 381 .indexed = 1, 382 .output = 1, 383 .ext_info = adf4350_ext_info, 384 }; 385 386 static const struct iio_info adf4350_info = { 387 .debugfs_reg_access = &adf4350_reg_access, 388 }; 389 390 static void adf4350_clk_del_provider(void *data) 391 { 392 struct adf4350_state *st = data; 393 394 of_clk_del_provider(st->spi->dev.of_node); 395 } 396 397 static unsigned long adf4350_clk_recalc_rate(struct clk_hw *hw, 398 unsigned long parent_rate) 399 { 400 struct adf4350_state *st = to_adf4350_state(hw); 401 unsigned long long tmp; 402 403 tmp = (u64)(st->r0_int * st->r1_mod + st->r0_fract) * st->fpfd; 404 do_div(tmp, st->r1_mod * (1 << st->r4_rf_div_sel)); 405 406 return tmp; 407 } 408 409 static int adf4350_clk_set_rate(struct clk_hw *hw, 410 unsigned long rate, 411 unsigned long parent_rate) 412 { 413 struct adf4350_state *st = to_adf4350_state(hw); 414 415 if (parent_rate == 0 || parent_rate > ADF4350_MAX_FREQ_REFIN) 416 return -EINVAL; 417 418 st->clkin = parent_rate; 419 420 return adf4350_set_freq(st, rate); 421 } 422 423 static int adf4350_clk_prepare(struct clk_hw *hw) 424 { 425 struct adf4350_state *st = to_adf4350_state(hw); 426 427 st->regs[ADF4350_REG2] &= ~ADF4350_REG2_POWER_DOWN_EN; 428 429 return adf4350_sync_config(st); 430 } 431 432 static void adf4350_clk_unprepare(struct clk_hw *hw) 433 { 434 struct adf4350_state *st = to_adf4350_state(hw); 435 436 st->regs[ADF4350_REG2] |= ADF4350_REG2_POWER_DOWN_EN; 437 438 adf4350_sync_config(st); 439 } 440 441 static int adf4350_clk_is_enabled(struct clk_hw *hw) 442 { 443 struct adf4350_state *st = to_adf4350_state(hw); 444 445 return (st->regs[ADF4350_REG2] & ADF4350_REG2_POWER_DOWN_EN); 446 } 447 448 static const struct clk_ops adf4350_clk_ops = { 449 .recalc_rate = adf4350_clk_recalc_rate, 450 .set_rate = adf4350_clk_set_rate, 451 .prepare = adf4350_clk_prepare, 452 .unprepare = adf4350_clk_unprepare, 453 .is_enabled = adf4350_clk_is_enabled, 454 }; 455 456 static int adf4350_clk_register(struct adf4350_state *st) 457 { 458 struct spi_device *spi = st->spi; 459 struct clk_init_data init; 460 struct clk *clk; 461 const char *parent_name; 462 int ret; 463 464 if (!device_property_present(&spi->dev, "#clock-cells")) 465 return 0; 466 467 if (device_property_read_string(&spi->dev, "clock-output-names", &init.name)) { 468 init.name = devm_kasprintf(&spi->dev, GFP_KERNEL, "%s-clk", 469 fwnode_get_name(dev_fwnode(&spi->dev))); 470 if (!init.name) 471 return -ENOMEM; 472 } 473 474 parent_name = of_clk_get_parent_name(spi->dev.of_node, 0); 475 if (!parent_name) 476 return -EINVAL; 477 478 init.ops = &adf4350_clk_ops; 479 init.parent_names = &parent_name; 480 init.num_parents = 1; 481 init.flags = CLK_SET_RATE_PARENT; 482 483 st->hw.init = &init; 484 clk = devm_clk_register(&spi->dev, &st->hw); 485 if (IS_ERR(clk)) 486 return PTR_ERR(clk); 487 488 ret = of_clk_add_provider(spi->dev.of_node, of_clk_src_simple_get, clk); 489 if (ret) 490 return ret; 491 492 st->clkout = clk; 493 494 return devm_add_action_or_reset(&spi->dev, adf4350_clk_del_provider, st); 495 } 496 497 static struct adf4350_platform_data *adf4350_parse_dt(struct device *dev) 498 { 499 struct adf4350_platform_data *pdata; 500 unsigned int tmp; 501 502 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 503 if (!pdata) 504 return NULL; 505 506 snprintf(pdata->name, sizeof(pdata->name), "%pfw", dev_fwnode(dev)); 507 508 tmp = 10000; 509 device_property_read_u32(dev, "adi,channel-spacing", &tmp); 510 pdata->channel_spacing = tmp; 511 512 tmp = 0; 513 device_property_read_u32(dev, "adi,power-up-frequency", &tmp); 514 pdata->power_up_frequency = tmp; 515 516 tmp = 0; 517 device_property_read_u32(dev, "adi,reference-div-factor", &tmp); 518 pdata->ref_div_factor = tmp; 519 520 pdata->ref_doubler_en = device_property_read_bool(dev, "adi,reference-doubler-enable"); 521 pdata->ref_div2_en = device_property_read_bool(dev, "adi,reference-div2-enable"); 522 523 /* r2_user_settings */ 524 pdata->r2_user_settings = 0; 525 if (device_property_read_bool(dev, "adi,phase-detector-polarity-positive-enable")) 526 pdata->r2_user_settings |= ADF4350_REG2_PD_POLARITY_POS; 527 if (device_property_read_bool(dev, "adi,lock-detect-precision-6ns-enable")) 528 pdata->r2_user_settings |= ADF4350_REG2_LDP_6ns; 529 if (device_property_read_bool(dev, "adi,lock-detect-function-integer-n-enable")) 530 pdata->r2_user_settings |= ADF4350_REG2_LDF_INT_N; 531 532 tmp = 2500; 533 device_property_read_u32(dev, "adi,charge-pump-current", &tmp); 534 pdata->r2_user_settings |= ADF4350_REG2_CHARGE_PUMP_CURR_uA(tmp); 535 536 tmp = 0; 537 device_property_read_u32(dev, "adi,muxout-select", &tmp); 538 pdata->r2_user_settings |= ADF4350_REG2_MUXOUT(tmp); 539 540 if (device_property_read_bool(dev, "adi,low-spur-mode-enable")) 541 pdata->r2_user_settings |= ADF4350_REG2_NOISE_MODE(0x3); 542 543 /* r3_user_settings */ 544 545 pdata->r3_user_settings = 0; 546 if (device_property_read_bool(dev, "adi,cycle-slip-reduction-enable")) 547 pdata->r3_user_settings |= ADF4350_REG3_12BIT_CSR_EN; 548 if (device_property_read_bool(dev, "adi,charge-cancellation-enable")) 549 pdata->r3_user_settings |= ADF4351_REG3_CHARGE_CANCELLATION_EN; 550 if (device_property_read_bool(dev, "adi,anti-backlash-3ns-enable")) 551 pdata->r3_user_settings |= ADF4351_REG3_ANTI_BACKLASH_3ns_EN; 552 if (device_property_read_bool(dev, "adi,band-select-clock-mode-high-enable")) 553 pdata->r3_user_settings |= ADF4351_REG3_BAND_SEL_CLOCK_MODE_HIGH; 554 555 tmp = 0; 556 device_property_read_u32(dev, "adi,12bit-clk-divider", &tmp); 557 pdata->r3_user_settings |= ADF4350_REG3_12BIT_CLKDIV(tmp); 558 559 tmp = 0; 560 device_property_read_u32(dev, "adi,clk-divider-mode", &tmp); 561 pdata->r3_user_settings |= ADF4350_REG3_12BIT_CLKDIV_MODE(tmp); 562 563 /* r4_user_settings */ 564 565 pdata->r4_user_settings = 0; 566 if (device_property_read_bool(dev, "adi,aux-output-enable")) 567 pdata->r4_user_settings |= ADF4350_REG4_AUX_OUTPUT_EN; 568 if (device_property_read_bool(dev, "adi,aux-output-fundamental-enable")) 569 pdata->r4_user_settings |= ADF4350_REG4_AUX_OUTPUT_FUND; 570 if (device_property_read_bool(dev, "adi,mute-till-lock-enable")) 571 pdata->r4_user_settings |= ADF4350_REG4_MUTE_TILL_LOCK_EN; 572 573 tmp = 0; 574 device_property_read_u32(dev, "adi,output-power", &tmp); 575 pdata->r4_user_settings |= ADF4350_REG4_OUTPUT_PWR(tmp); 576 577 tmp = 0; 578 device_property_read_u32(dev, "adi,aux-output-power", &tmp); 579 pdata->r4_user_settings |= ADF4350_REG4_AUX_OUTPUT_PWR(tmp); 580 581 return pdata; 582 } 583 584 static void adf4350_power_down(void *data) 585 { 586 struct iio_dev *indio_dev = data; 587 struct adf4350_state *st = iio_priv(indio_dev); 588 589 st->regs[ADF4350_REG2] |= ADF4350_REG2_POWER_DOWN_EN; 590 adf4350_sync_config(st); 591 } 592 593 static int adf4350_probe(struct spi_device *spi) 594 { 595 struct adf4350_platform_data *pdata; 596 struct iio_dev *indio_dev; 597 struct adf4350_state *st; 598 struct clk *clk = NULL; 599 int ret; 600 601 if (dev_fwnode(&spi->dev)) { 602 pdata = adf4350_parse_dt(&spi->dev); 603 if (pdata == NULL) 604 return -EINVAL; 605 } else { 606 pdata = spi->dev.platform_data; 607 } 608 609 if (!pdata) { 610 dev_warn(&spi->dev, "no platform data? using default\n"); 611 pdata = &default_pdata; 612 } 613 614 if (!pdata->clkin) { 615 clk = devm_clk_get_enabled(&spi->dev, "clkin"); 616 if (IS_ERR(clk)) 617 return PTR_ERR(clk); 618 } 619 620 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 621 if (indio_dev == NULL) 622 return -ENOMEM; 623 624 st = iio_priv(indio_dev); 625 626 ret = devm_regulator_get_enable(&spi->dev, "vcc"); 627 if (ret) 628 return ret; 629 630 st->spi = spi; 631 st->pdata = pdata; 632 633 indio_dev->name = (pdata->name[0] != 0) ? pdata->name : 634 spi_get_device_id(spi)->name; 635 636 indio_dev->info = &adf4350_info; 637 indio_dev->modes = INDIO_DIRECT_MODE; 638 639 mutex_init(&st->lock); 640 641 st->chspc = pdata->channel_spacing; 642 if (clk) { 643 st->clk = clk; 644 st->clkin = clk_get_rate(clk); 645 } else { 646 st->clkin = pdata->clkin; 647 } 648 649 st->min_out_freq = spi_get_device_id(spi)->driver_data == 4351 ? 650 ADF4351_MIN_OUT_FREQ : ADF4350_MIN_OUT_FREQ; 651 652 memset(st->regs_hw, 0xFF, sizeof(st->regs_hw)); 653 654 st->lock_detect_gpiod = devm_gpiod_get_optional(&spi->dev, NULL, 655 GPIOD_IN); 656 if (IS_ERR(st->lock_detect_gpiod)) 657 return PTR_ERR(st->lock_detect_gpiod); 658 659 if (pdata->power_up_frequency) { 660 ret = adf4350_set_freq(st, pdata->power_up_frequency); 661 if (ret) 662 return ret; 663 } 664 665 ret = adf4350_clk_register(st); 666 if (ret) 667 return ret; 668 669 if (!st->clkout) { 670 indio_dev->channels = &adf4350_chan; 671 indio_dev->num_channels = 1; 672 } 673 674 ret = devm_add_action_or_reset(&spi->dev, adf4350_power_down, indio_dev); 675 if (ret) 676 return dev_err_probe(&spi->dev, ret, 677 "Failed to add action to managed power down\n"); 678 679 return devm_iio_device_register(&spi->dev, indio_dev); 680 } 681 682 static const struct of_device_id adf4350_of_match[] = { 683 { .compatible = "adi,adf4350", }, 684 { .compatible = "adi,adf4351", }, 685 { /* sentinel */ }, 686 }; 687 MODULE_DEVICE_TABLE(of, adf4350_of_match); 688 689 static const struct spi_device_id adf4350_id[] = { 690 {"adf4350", 4350}, 691 {"adf4351", 4351}, 692 {} 693 }; 694 MODULE_DEVICE_TABLE(spi, adf4350_id); 695 696 static struct spi_driver adf4350_driver = { 697 .driver = { 698 .name = "adf4350", 699 .of_match_table = adf4350_of_match, 700 }, 701 .probe = adf4350_probe, 702 .id_table = adf4350_id, 703 }; 704 module_spi_driver(adf4350_driver); 705 706 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>"); 707 MODULE_DESCRIPTION("Analog Devices ADF4350/ADF4351 PLL"); 708 MODULE_LICENSE("GPL v2"); 709