perf arch events: Fix duplicate RISC-V SBI firmware event nameCurrently, the RISC-V firmware JSON file has duplicate event name"FW_SFENCE_VMA_RECEIVED". According to the RISC-V SBI PMU extension[1
perf arch events: Fix duplicate RISC-V SBI firmware event nameCurrently, the RISC-V firmware JSON file has duplicate event name"FW_SFENCE_VMA_RECEIVED". According to the RISC-V SBI PMU extension[1],the event name should be "FW_SFENCE_VMA_ASID_SENT".Before this patch:$ perf listfirmware: fw_access_load [Load access trap event. Unit: cpu] fw_access_store [Store access trap event. Unit: cpu].... fw_set_timer [Set timer event. Unit: cpu] fw_sfence_vma_asid_received [Received SFENCE.VMA with ASID request from other HART event. Unit: cpu] fw_sfence_vma_received [Sent SFENCE.VMA with ASID request to other HART event. Unit: cpu]After this patch:$ perf listfirmware: fw_access_load [Load access trap event. Unit: cpu] fw_access_store [Store access trap event. Unit: cpu]..... fw_set_timer [Set timer event. Unit: cpu] fw_sfence_vma_asid_received [Received SFENCE.VMA with ASID request from other HART event. Unit: cpu] fw_sfence_vma_asid_sent [Sent SFENCE.VMA with ASID request to other HART event. Unit: cpu] fw_sfence_vma_received [Received SFENCE.VMA request from other HART event. Unit: cpu]Link: https://github.com/riscv-non-isa/riscv-sbi-doc/blob/master/src/ext-pmu.adoc#event-firmware-events-type-15 [1]Fixes: 8f0dcb4e7364 ("perf arch events: riscv sbi firmware std event files")Fixes: c4f769d4093d ("perf vendor events riscv: add Sifive U74 JSON file")Fixes: acbf6de674ef ("perf vendor events riscv: Add StarFive Dubhe-80 JSON file")Fixes: 7340c6df49df ("perf vendor events riscv: add T-HEAD C9xx JSON file")Fixes: f5102e31c209 ("riscv: andes: Support specifying symbolic firmware and hardware raw event")Signed-off-by: Eric Lin <eric.lin@sifive.com>Reviewed-by: Samuel Holland <samuel.holland@sifive.com>Reviewed-by: Nikita Shubin <n.shubin@yadro.com>Reviewed-by: Inochi Amaoto <inochiama@outlook.com>Reviewed-by: Andrew Jones <ajones@ventanamicro.com>Reviewed-by: Atish Patra <atishp@rivosinc.com>Link: https://lore.kernel.org/r/20240719115018.27356-1-eric.lin@sifive.comSigned-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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perf vendor events riscv: Add StarFive Dubhe-80 JSON fileStarFive's Dubhe-80 supports raw event id 0x00 - 0x22. The raw eventsare enabled through PMU node of DT binding. Besides raw event, adds
perf vendor events riscv: Add StarFive Dubhe-80 JSON fileStarFive's Dubhe-80 supports raw event id 0x00 - 0x22. The raw eventsare enabled through PMU node of DT binding. Besides raw event, addstandard RISC-V firmware events to support monitoring of firmware event.Example of PMU DT node: pmu { compatible = "riscv,pmu"; riscv,raw-event-to-mhpmcounters = /* Event ID 1-31 */ <0x00 0x00 0xFFFFFFFF 0xFFFFFFE0 0x00007FF8>, /* Event ID 32-33 */ <0x00 0x20 0xFFFFFFFF 0xFFFFFFFE 0x00007FF8>, /* Event ID 34 */ <0x00 0x22 0xFFFFFFFF 0xFFFFFF22 0x00007FF8>; };Example of 'perf stat' output: [root@user]# perf stat -a \ -e access_mmu_stlb \ -e miss_mmu_stlb \ -e access_mmu_pte_c \ -e rob_flush \ -e btb_prediction_miss \ -e itlb_miss \ -e sync_del_fetch_g \ -e icache_miss \ -e bpu_br_retire \ -e bpu_br_miss \ -e ret_ins_retire \ -e ret_ins_miss \ -- openssl speed rsa2048 Doing 2048 bits private rsa's for 10s: 39 2048 bits private RSA's in 10.14s Doing 2048 bits public rsa's for 10s: 1563 2048 bits public RSA's in 10.00s version: 3.0.11 built on: Tue Sep 19 13:02:31 2023 UTC options: bn(64,64) CPUINFO: N/A sign verify sign/s verify/s rsa 2048 bits 0.260000s 0.006398s 3.8 156.3 Performance counter stats for 'system wide': 1338350 access_mmu_stlb 1154025 miss_mmu_stlb 1162691 access_mmu_pte_c 34067 rob_flush 11212384 btb_prediction_miss 1256242 itlb_miss 652523491 sync_del_fetch_g 384465 icache_miss 64635789 bpu_br_retire 323440 bpu_br_miss 8785143 ret_ins_retire 31236 ret_ins_miss 20.760822480 seconds time elapsedReviewed-by: Ian Rogers <irogers@google.com>Signed-off-by: Ji Sheng Teoh <jisheng.teoh@starfivetech.com>Cc: Adrian Hunter <adrian.hunter@intel.com>Cc: Albert Ou <aou@eecs.berkeley.edu>Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>Cc: Ingo Molnar <mingo@redhat.com>Cc: Jiri Olsa <jolsa@kernel.org>Cc: Ley Foon Tan <leyfoon.tan@starfivetech.com>Cc: Mark Rutland <mark.rutland@arm.com>Cc: Namhyung Kim <namhyung@kernel.org>Cc: Nikita Shubin <n.shubin@yadro.com>Cc: Palmer Dabbelt <palmer@dabbelt.com>Cc: Paul Walmsley <paul.walmsley@sifive.com>Cc: Peter Zijlstra <peterz@infradead.org>Cc: linux-riscv@lists.infradead.orgLink: https://lore.kernel.org/r/20231103082441.1389842-1-jisheng.teoh@starfivetech.comSigned-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>