| /freebsd/sys/contrib/device-tree/Bindings/counter/ |
| H A D | interrupt-counter.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/counter/interrupt-counter.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Interrupt counter
10 - Oleksij Rempel <o.rempel@pengutronix.de>
13 A generic interrupt counter to measure interrupt frequency. It was developed
17 Interrupts or gpios are required. If both are defined, the interrupt will
22 const: interrupt-counter
31 - compatible
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| /freebsd/sys/dev/tsec/ |
| H A D | if_tsecreg.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (C) 2008-2009 Semihalf, Piotr Ziecik
5 * Copyright (C) 2006-2007 Semihalf, Piotr Kruszynski
33 #define TSEC_REG_IEVENT 0x010 /* Interrupt event register */
34 #define TSEC_REG_IMASK 0x014 /* Interrupt mask register */
53 #define TSEC_REG_TXIC 0x110 /* Transmit interrupt coalescing
58 #define TSEC_REG_OSTBD 0x2b0 /* Out-of-sequence TxBD register */
59 #define TSEC_REG_OSTBDP 0x2b4 /* Out-of-sequence Tx data buffer pointer
66 #define TSEC_REG_RXIC 0x310 /* Receive interrupt coalescing
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| /freebsd/sys/contrib/device-tree/Bindings/timer/ |
| H A D | samsung,exynos4210-mct.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/timer/samsung,exynos4210-mct.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
14 global timer and CPU local timers. The global timer is a 64-bit free running
15 up-counter and can generate 4 interrupts when the counter reaches one of the
16 four preset counter values. The CPU local timers are 32-bit free running
17 down-counters and generate an interrupt when the counter expires. There is
23 - enum:
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| H A D | nvidia,tegra-timer.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/timer/nvidia,tegra-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Stephen Warren <swarren@nvidia.com>
13 - if:
17 const: nvidia,tegra210-timer
21 # Either a single combined interrupt or up to 14 individual interrupts
27 - if:
31 - items:
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| H A D | brcm,bcm2835-system-timer.txt | 3 The System Timer peripheral provides four 32-bit timer channels and a
4 single 64-bit free running counter. Each channel has an output compare
6 free running counter values, and generates an interrupt.
10 - compatible : should be "brcm,bcm2835-system-timer"
11 - reg : Specifies base physical address and size of the registers.
12 - interrupts : A list of 4 interrupt sinks; one per timer channel.
13 - clock-frequency : The frequency of the clock that drives the counter, in Hz.
18 compatible = "brcm,bcm2835-system-timer";
21 clock-frequency = <1000000>;
|
| H A D | ti,keystone-timer.txt | 3 This document provides bindings for the 64-bit timer in the KeyStone
4 architecture devices. The timer can be configured as a general-purpose 64-bit
5 timer, dual general-purpose 32-bit timers. When configured as dual 32-bit
9 It is global timer is a free running up-counter and can generate interrupt
10 when the counter reaches preset counter values.
17 - compatible : should be "ti,keystone-timer".
18 - reg : specifies base physical address and count of the registers.
19 - interrupts : interrupt generated by the timer.
20 - clocks : the clock feeding the timer clock.
25 compatible = "ti,keystone-timer";
|
| H A D | ti,davinci-timer.txt | 3 This document provides bindings for the 64-bit timer in the DaVinci
4 architecture devices. The timer can be configured as a general-purpose 64-bit
5 timer, dual general-purpose 32-bit timers. When configured as dual 32-bit
9 The timer is a free running up-counter and can generate interrupts when the
10 counter reaches preset counter values.
12 Also see ../watchdog/davinci-wdt.txt for timers that are configurable as
17 - compatible : should be "ti,da830-timer".
18 - reg : specifies base physical address and count of the registers.
19 - interrupts : interrupts generated by the timer.
20 - interrupt-names: should be "tint12", "tint34", "cmpint0", "cmpint1",
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| /freebsd/sys/amd64/vmm/io/ |
| H A D | vhpet.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
79 uint64_t isr; /* Interrupt Status */
80 uint32_t countbase; /* HPET counter base value */
85 uint64_t msireg; /* FSB interrupt routing */
89 sbintime_t callout_sbt; /* time when counter==compval */
94 #define VHPET_LOCK(vhp) mtx_lock(&((vhp)->mtx))
95 #define VHPET_UNLOCK(vhp) mtx_unlock(&((vhp)->mtx))
97 static void vhpet_start_timer(struct vhpet *vhpet, int n, uint32_t counter,
106 cap |= (VHPET_NUM_TIMERS - 1) << 8; /* number of timers */ in vhpet_capabilities()
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| /freebsd/sys/dev/ath/ath_hal/ar5212/ |
| H A D | ar5212reg.h | 1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2008 Atheros Communications, Inc.
26 /* DMA Control and Interrupt Registers */
30 #define AR_IER 0x0024 /* MAC Interrupt enable register */
46 #define AR_ISR 0x0080 /* MAC Primary interrupt status register */
47 #define AR_ISR_S0 0x0084 /* MAC Secondary interrupt status register 0 */
48 #define AR_ISR_S1 0x0088 /* MAC Secondary interrupt status register 1 */
49 #define AR_ISR_S2 0x008c /* MAC Secondary interrupt status register 2 */
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| /freebsd/sys/contrib/ncsw/inc/flib/ |
| H A D | fsl_fman_dtsec.h | 2 * Copyright 2008-2012 Freescale Semiconductor Inc.
44 * - fman_dtsec_defconfig() - This step is optional and yet recommended. Its
47 * - Change dtsec configuration in &dtsec_cfg. This structure will be used
50 * - fman_dtsec_init() - Applies the configuration on dTSEC hardware. Note that
53 * - fman_dtsec_set_mac_address() - Set the station address (mac address).
56 * - fman_dtsec_adjust_link() - Set the link speed and duplex parameters
59 * - dtsec_enable_tx() and dtsec_enable_rx() to enable transmission and
70 * DTSEC_IEVENT_GRSC bits. Alternatively the dTSEC interrupt mask can be set to
78 * DOC: dTSEC interrupt handling
80 * This code does not provide an interrupt handler for dTSEC. Instead this
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| H A D | fsl_fman.h | 50 uint8_t num_backup_pools; /**< Number of BM backup pools -
73 considered for depletion (Note - this
76 will be sent after a single-pool
80 considered for depletion (Note - this
137 uint32_t fm_rie; /**< FM Error Interrupt Enable 0x1c */
138 uint32_t fmfp_fcev[4]; /**< FPM FMan-Controller Event 1-4 0x20-0x2f */
139 uint32_t res0030[4]; /**< res 0x30 - 0x3f */
140 uint32_t fmfp_cee[4]; /**< PM FMan-Controller Event 1-4 0x40-0x4f */
141 uint32_t res0050[4]; /**< res 0x50-0x5f */
150 uint32_t fmfp_drd[16]; /**< FPM Data_Ram Data 0-15 0x80 - 0xbf */
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| /freebsd/sys/contrib/device-tree/Bindings/arm/ |
| H A D | arm,cci-400.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,cci-400.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
13 ARM multi-cluster systems maintain intra-cluster coherency through a cache
24 pattern: "^cci(@[0-9a-f]+)?$"
28 - arm,cci-400
29 - arm,cci-500
30 - arm,cci-550
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| H A D | cci.txt | 5 ARM multi-cluster systems maintain intra-cluster coherency through a
24 - compatible
28 "arm,cci-400"
29 "arm,cci-500"
30 "arm,cci-550"
32 - reg
40 - ranges:
53 - CCI control interface nodes
55 Node name must be "slave-if".
61 - compatible
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| /freebsd/sys/dev/ic/ |
| H A D | via6522reg.h | 1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
38 #define REG_T1CL 4 /* T1 low-order latch/low-order counter */
39 #define REG_T1CH 5 /* T1 high-order counter */
40 #define REG_T1LL 6 /* T1 low-order latches */
41 #define REG_T1LH 7 /* T1 high-order latches */
42 #define REG_T2CL 8 /* T2 low-order latch/low-order counter */
43 #define REG_T2CH 9 /* T2 high-order counter */
47 #define REG_IFR 13 /* Interrupt flag register */
48 #define REG_IER 14 /* Interrupt-enable register */
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| /freebsd/sys/contrib/alpine-hal/ |
| H A D | al_hal_nb_regs.h | 1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
101 /* [0x6c] Read-only that reflects CPU Cluster Local GIC base high address */
103 /* [0x70] Read-only that reflects CPU Cluster Local GIC base low address */
105 /* [0x74] Read-only that reflects the device's IOGIC base high address. */
107 /* [0x78] Read-only that reflects IOGIC base low address */
341 /* [0x0] Counter Configuration Register */
343 /* [0x4] Counter Control Register */
345 /* [0x8] Counter Control Register */
347 /* [0xc] Counter Control Register */
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| /freebsd/sys/contrib/device-tree/src/arm/st/ |
| H A D | stm32mp131.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
6 #include <dt-bindings/interrupt-controller/arm-gi
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| H A D | stm32mp151.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
6 #include <dt-bindings/interrupt-controller/arm-gi
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| /freebsd/share/doc/papers/timecounter/ |
| H A D | timecounter.ms | 5 .\" ----------------------------------------------------------------------------
6 .\" "THE BEER-WARE LICENSE" (Revision 42):
9 .\" this stuff is worth it, you can buy me a beer in return. Poul-Henning Kamp
10 .\" ----------------------------------------------------------------------------
16 .A "Poul-Henning Kamp" "The FreeBSD Project"
18 The FreeBSD timecounters are an architecture-independent implementation
21 multiplication to canonical timescales based on micro- or nano-seconds
23 synchronisation. Timecounters are implemented using lock-less
24 stable-storage based primitives which scale efficiently in SMP
80 for instance transport or consumption of a substance at a well-known
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| /freebsd/share/man/man4/ |
| H A D | hpet.4 | 35 .Bd -ragged -offset indent
41 .Bl -ohang
57 .Bd -literal
63 controls how much per-CPU event timers should driver attempt to register.
70 usually enumerated via ACPI) to supply kernel with one time counter and
72 This hardware includes single main counter with known increment frequency
75 When value of the main counter matches current value of any comparator,
76 interrupt can be generated.
77 Depending on hardware capabilities and configuration, interrupt can be
78 delivered as regular I/O APIC interrupt (ISA or PCI) in range from 0 to 31,
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| /freebsd/sys/dev/neta/ |
| H A D | if_mvnetareg.h | 46 /* XXX: Currently multi-queue can be used on the Tx side only */
53 #if MVNETA_TX_QNUM_MAX & (MVNETA_TX_QNUM_MAX - 1) != 0
56 #if MVNETA_RX_QNUM_MAX & (MVNETA_RX_QNUM_MAX - 1) != 0
62 #define MVNETA_TX_QUEUE_ALL ((1<<MVNETA_TX_QNUM_MAX)-1)
63 #define MVNETA_RX_QUEUE_ALL ((1<<MVNETA_RX_QNUM_MAX)-1)
86 #define MVNETA_EUIC 0x2080 /* Ethernet Unit Interrupt Cause */
87 #define MVNETA_EUIM 0x2084 /* Ethernet Unit Interrupt Mask */
119 #define MVNETA_PDFC 0x2484 /* Port Rx Discard Frame Counter */
120 #define MVNETA_POFC 0x2488 /* Port Overrun Frame Counter */
134 /* Rx DMA Wake on LAN Registers 0x3690 - 0x36b8 */
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| /freebsd/sys/contrib/xen/arch-x86/ |
| H A D | pmu.h | 26 /* x86-specific PMU definitions */
31 * Offsets to counter and control MSRs (relative to xen_pmu_arch.c.amd).
37 /* Counter MSRs */
45 uint64_t counter; member
53 * Offsets to fixed and architectural counter MSRs (relative to
69 /* Fixed and architectural counter MSRs */
95 * Architecture-specific information describing state of the processor at
96 * the time of PMU interrupt.
99 * hypervisor during PMU interrupt). Hypervisor will read updated data in
105 * Processor's registers at the time of interrupt.
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| /freebsd/sys/dev/qat/qat_hw/qat_c4xxx/ |
| H A D | adf_c4xxx_ras.c | 1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* Copyright(c) 2007-2022 Intel Corporation */
14 unsigned long counter = 0; in adf_sysctl_read_ras_correctable() local
16 if (accel_dev->ras_counters) in adf_sysctl_read_ras_correctable()
17 counter = atomic_read(&accel_dev->ras_counters[ADF_RAS_CORR]); in adf_sysctl_read_ras_correctable()
19 return SYSCTL_OUT(req, &counter, sizeof(counter)); in adf_sysctl_read_ras_correctable()
25 unsigned long counter = 0; in adf_sysctl_read_ras_uncorrectable() local
27 if (accel_dev->ras_counters) in adf_sysctl_read_ras_uncorrectable()
28 counter = atomic_read(&accel_dev->ras_counters[ADF_RAS_UNCORR]); in adf_sysctl_read_ras_uncorrectable()
30 return SYSCTL_OUT(req, &counter, sizeof(counter)); in adf_sysctl_read_ras_uncorrectable()
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| /freebsd/sys/dev/ath/ath_hal/ar5211/ |
| H A D | ar5211reg.h | 1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2006 Atheros Communications, Inc.
31 /* DMA Control and Interrupt Registers */
35 #define AR_IER 0x0024 /* Interrupt enable register */
49 #define AR_ISR 0x0080 /* Primary interrupt status register */
50 #define AR_ISR_S0 0x0084 /* Secondary interrupt status reg 0 */
51 #define AR_ISR_S1 0x0088 /* Secondary interrupt status reg 1 */
52 #define AR_ISR_S2 0x008c /* Secondary interrupt status reg 2 */
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| /freebsd/sys/dev/le/ |
| H A D | lancereg.h | 3 /*-
4 * SPDX-License-Identifier: BSD-2-Clause
34 /*-
70 * - Am7990 Local Area Network Controller for Ethernet (LANCE)
71 * (and its descendent Am79c90 C-LANCE).
73 * - Am79c900 Integrated Local Area Communications Controller (ILACC)
75 * - Am79c960 PCnet-ISA Single-Chip Ethernet Controller for ISA
77 * - Am79c961 PCnet-ISA+ Jumperless Single-Chip Ethernet Controller
80 * - Am79c961A PCnet-ISA II Jumperless Full-Duplex Single-Chip
83 * - Am79c965A PCnet-32 Single-Chip 32-bit Ethernet Controller
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| /freebsd/sys/dev/cas/ |
| H A D | if_casreg.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
30 * from: FreeBSD: if_gemreg.h 174987 2007-12-30 01:32:03Z marius
44 #define CAS_STATUS 0x000c /* interrupt status */
45 #define CAS_INTMASK 0x0010 /* interrupt mask */
47 #define CAS_STATUS_ALIAS 0x001c /* interrupt status alias */
59 #define CAS_INTMASK2 0x1038 /* interrupt mask 2 for INTB */
60 #define CAS_STATUS2 0x103c /* interrupt status 2 for INTB */
62 #define CAS_STATUS_ALIAS2 0x1044 /* interrupt status alias 2 for INTB */
63 #define CAS_INTMASK3 0x1048 /* interrupt mask 3 for INTC */
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