Lines Matching +full:interrupt +full:- +full:counter

26 /* x86-specific PMU definitions */
31      * Offsets to counter and control MSRs (relative to xen_pmu_arch.c.amd).
37     /* Counter MSRs */
45     uint64_t counter;  member
53     * Offsets to fixed and architectural counter MSRs (relative to
69     /* Fixed and architectural counter MSRs */
95  * Architecture-specific information describing state of the processor at
96  * the time of PMU interrupt.
99  * hypervisor during PMU interrupt). Hypervisor will read updated data in
105          * Processor's registers at the time of interrupt.
129      * Vendor-specific PMU registers.
153  * c-file-style: "BSD"
154  * c-basic-offset: 4
155  * tab-width: 4
156  * indent-tabs-mode: nil