Lines Matching +full:interrupt +full:- +full:counter

1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (C) 2008-2009 Semihalf, Piotr Ziecik
5 * Copyright (C) 2006-2007 Semihalf, Piotr Kruszynski
33 #define TSEC_REG_IEVENT 0x010 /* Interrupt event register */
34 #define TSEC_REG_IMASK 0x014 /* Interrupt mask register */
53 #define TSEC_REG_TXIC 0x110 /* Transmit interrupt coalescing
58 #define TSEC_REG_OSTBD 0x2b0 /* Out-of-sequence TxBD register */
59 #define TSEC_REG_OSTBDP 0x2b4 /* Out-of-sequence Tx data buffer pointer
66 #define TSEC_REG_RXIC 0x310 /* Receive interrupt coalescing
76 #define TSEC_REG_IPGIFG 0x508 /* Inter-packet gap/inter-frame gap
78 #define TSEC_REG_HAFDUP 0x50c /* Half-duplex register */
92 #define TSEC_REG_MON_TR64 0x680 /* Transmit and receive 64-byte
93 * frame counter register */
94 #define TSEC_REG_MON_TR127 0x684 /* Transmit and receive 65-127 byte
95 * frame counter register */
96 #define TSEC_REG_MON_TR255 0x688 /* Transmit and receive 128-255 byte
97 * frame counter register */
98 #define TSEC_REG_MON_TR511 0x68c /* Transmit and receive 256-511 byte
99 * frame counter register */
100 #define TSEC_REG_MON_TR1K 0x690 /* Transmit and receive 512-1023 byte
101 * frame counter register */
102 #define TSEC_REG_MON_TRMAX 0x694 /* Transmit and receive 1024-1518 byte
103 * frame counter register */
104 #define TSEC_REG_MON_TRMGV 0x698 /* Transmit and receive 1519-1522 byte
105 * good VLAN frame counter register */
108 #define TSEC_REG_MON_RBYT 0x69c /* Receive byte counter register */
109 #define TSEC_REG_MON_RPKT 0x6a0 /* Receive packet counter register */
110 #define TSEC_REG_MON_RFCS 0x6a4 /* Receive FCS error counter register */
111 #define TSEC_REG_MON_RMCA 0x6a8 /* Receive multicast packet counter
113 #define TSEC_REG_MON_RBCA 0x6ac /* Receive broadcast packet counter
115 #define TSEC_REG_MON_RXCF 0x6b0 /* Receive control frame packet counter
117 #define TSEC_REG_MON_RXPF 0x6b4 /* Receive pause frame packet counter
119 #define TSEC_REG_MON_RXUO 0x6b8 /* Receive unknown OP code counter
121 #define TSEC_REG_MON_RALN 0x6bc /* Receive alignment error counter
123 #define TSEC_REG_MON_RFLR 0x6c0 /* Receive frame length error counter
125 #define TSEC_REG_MON_RCDE 0x6c4 /* Receive code error counter register */
126 #define TSEC_REG_MON_RCSE 0x6c8 /* Receive carrier sense error counter
128 #define TSEC_REG_MON_RUND 0x6cc /* Receive undersize packet counter
130 #define TSEC_REG_MON_ROVR 0x6d0 /* Receive oversize packet counter
132 #define TSEC_REG_MON_RFRG 0x6d4 /* Receive fragments counter register */
133 #define TSEC_REG_MON_RJBR 0x6d8 /* Receive jabber counter register */
134 #define TSEC_REG_MON_RDRP 0x6dc /* Receive drop counter register */
137 #define TSEC_REG_MON_TBYT 0x6e0 /* Transmit byte counter register */
138 #define TSEC_REG_MON_TPKT 0x6e4 /* Transmit packet counter register */
139 #define TSEC_REG_MON_TMCA 0x6e8 /* Transmit multicast packet counter
141 #define TSEC_REG_MON_TBCA 0x6ec /* Transmit broadcast packet counter
143 #define TSEC_REG_MON_TXPF 0x6f0 /* Transmit PAUSE control frame counter
145 #define TSEC_REG_MON_TDFR 0x6f4 /* Transmit deferral packet counter
148 * counter register */
149 #define TSEC_REG_MON_TSCL 0x6fc /* Transmit single collision packet counter
151 #define TSEC_REG_MON_TMCL 0x700 /* Transmit multiple collision packet counter
153 #define TSEC_REG_MON_TLCL 0x704 /* Transmit late collision packet counter
156 * counter register */
157 #define TSEC_REG_MON_TNCL 0x70c /* Transmit total collision counter
159 #define TSEC_REG_MON_TDRP 0x714 /* Transmit drop frame counter register */
160 #define TSEC_REG_MON_TJBR 0x718 /* Transmit jabber frame counter register */
161 #define TSEC_REG_MON_TFCS 0x71c /* Transmit FCS error counter register */
162 #define TSEC_REG_MON_TXCF 0x720 /* Transmit control frame counter register */
163 #define TSEC_REG_MON_TOVR 0x724 /* Transmit oversize frame counter
165 #define TSEC_REG_MON_TUND 0x728 /* Transmit undersize frame counter
167 #define TSEC_REG_MON_TFRG 0x72c /* Transmit fragments frame counter
219 #define TSEC_RCRTL_PRSFM 0x00000020 /* FIFO-mode parsing */
236 #define TSEC_IEVENT_RXC 0x40000000 /* Receive control interrupt */
237 #define TSEC_IEVENT_BSY 0x20000000 /* Busy condition interrupt */
242 #define TSEC_IEVENT_TXC 0x00800000 /* Transmit control interrupt */
245 #define TSEC_IEVENT_TXF 0x00100000 /* Transmit frame interrupt */
254 #define TSEC_IEVENT_RXF 0x00000080 /* Receive frame interrupt */
256 #define TSEC_IMASK_BREN 0x80000000 /* Babbling receiver interrupt */
257 #define TSEC_IMASK_RXCEN 0x40000000 /* Receive control interrupt */
258 #define TSEC_IMASK_BSYEN 0x20000000 /* Busy interrupt */
260 #define TSEC_IMASK_MSROEN 0x04000000 /* MSTAT register overflow interrupt */
261 #define TSEC_IMASK_GTSCEN 0x02000000 /* Graceful transmit stop complete interrupt */
262 #define TSEC_IMASK_BTEN 0x01000000 /* Babbling transmitter interrupt */
263 #define TSEC_IMASK_TXCEN 0x00800000 /* Transmit control interrupt */
264 #define TSEC_IMASK_TXEEN 0x00400000 /* Transmit error interrupt */
265 #define TSEC_IMASK_TXBEN 0x00200000 /* Transmit buffer interrupt */
266 #define TSEC_IMASK_TXFEN 0x00100000 /* Transmit frame interrupt */
270 #define TSEC_IMASK_RXBEN 0x00008000 /* Receive buffer interrupt */
273 #define TSEC_IMASK_GRSCEN 0x00000100 /* Graceful receive stop complete interrupt */
274 #define TSEC_IMASK_RXFEN 0x00000080 /* Receive frame interrupt */
290 * to the receive stream (Read-only) */
293 * to the transmit stream (Read-only) */
309 #define TSEC_ECNTRL_TBIM 0x00000020 /* Ten-bit I/F mode */
311 #define TSEC_ECNTRL_RMM 0x00000004 /* Reduced-pin mode */
335 #define TSEC_TXBD_I 0x1000 /* Interrupt */
351 #define TSEC_RXBD_I 0x1000 /* Interrupt */
354 #define TSEC_RXBD_M 0x0100 /* Miss - The frame was received because
358 #define TSEC_RXBD_LG 0x0020 /* Large - Rx frame length violation */
359 #define TSEC_RXBD_NO 0x0010 /* Rx non-octet aligned frame */
371 /* Transmit Path Off-Load Frame Control Block flags */
379 #define TSEC_TX_FCB_FLAG_NO_PH_CSUM 0x0100 /* Disable pseudo-header checksum */
382 /* Receive Path Off-Load Frame Control Block flags */