Lines Matching +full:interrupt +full:- +full:counter
1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2006 Atheros Communications, Inc.
31 /* DMA Control and Interrupt Registers */
35 #define AR_IER 0x0024 /* Interrupt enable register */
49 #define AR_ISR 0x0080 /* Primary interrupt status register */
50 #define AR_ISR_S0 0x0084 /* Secondary interrupt status reg 0 */
51 #define AR_ISR_S1 0x0088 /* Secondary interrupt status reg 1 */
52 #define AR_ISR_S2 0x008c /* Secondary interrupt status reg 2 */
53 #define AR_ISR_S3 0x0090 /* Secondary interrupt status reg 3 */
54 #define AR_ISR_S4 0x0094 /* Secondary interrupt status reg 4 */
55 #define AR_IMR 0x00a0 /* Primary interrupt mask register */
56 #define AR_IMR_S0 0x00a4 /* Secondary interrupt mask reg 0 */
57 #define AR_IMR_S1 0x00a8 /* Secondary interrupt mask reg 1 */
58 #define AR_IMR_S2 0x00ac /* Secondary interrupt mask reg 2 */
59 #define AR_IMR_S3 0x00b0 /* Secondary interrupt mask reg 3 */
60 #define AR_IMR_S4 0x00b4 /* Secondary interrupt mask reg 4 */
61 #define AR_ISR_RAC 0x00c0 /* Primary interrupt status reg, */
62 /* Shadow copies with read-and-clear access */
63 #define AR_ISR_S0_S 0x00c4 /* Secondary interrupt status reg 0 */
64 #define AR_ISR_S1_S 0x00c8 /* Secondary interrupt status reg 1 */
65 #define AR_ISR_S2_S 0x00cc /* Secondary interrupt status reg 2 */
66 #define AR_ISR_S3_S 0x00d0 /* Secondary interrupt status reg 3 */
67 #define AR_ISR_S4_S 0x00d4 /* Secondary interrupt status reg 4 */
148 #define AR_D0_LCL_IFS 0x1040 /* DCU-specific IFS settings */
149 #define AR_D1_LCL_IFS 0x1044 /* DCU-specific IFS settings */
150 #define AR_D2_LCL_IFS 0x1048 /* DCU-specific IFS settings */
151 #define AR_D3_LCL_IFS 0x104c /* DCU-specific IFS settings */
152 #define AR_D4_LCL_IFS 0x1050 /* DCU-specific IFS settings */
153 #define AR_D5_LCL_IFS 0x1054 /* DCU-specific IFS settings */
154 #define AR_D6_LCL_IFS 0x1058 /* DCU-specific IFS settings */
155 #define AR_D7_LCL_IFS 0x105c /* DCU-specific IFS settings */
156 #define AR_D8_LCL_IFS 0x1060 /* DCU-specific IFS settings */
157 #define AR_D9_LCL_IFS 0x1064 /* DCU-specific IFS settings */
184 #define AR_D0_MISC 0x1100 /* Misc DCU-specific settings */
185 #define AR_D1_MISC 0x1104 /* Misc DCU-specific settings */
186 #define AR_D2_MISC 0x1108 /* Misc DCU-specific settings */
187 #define AR_D3_MISC 0x110c /* Misc DCU-specific settings */
188 #define AR_D4_MISC 0x1110 /* Misc DCU-specific settings */
189 #define AR_D5_MISC 0x1114 /* Misc DCU-specific settings */
190 #define AR_D6_MISC 0x1118 /* Misc DCU-specific settings */
191 #define AR_D7_MISC 0x111c /* Misc DCU-specific settings */
192 #define AR_D8_MISC 0x1120 /* Misc DCU-specific settings */
193 #define AR_D9_MISC 0x1124 /* Misc DCU-specific settings */
208 /* MAC DCU-global IFS settings */
224 #define AR_INTPEND 0x4008 /* Interrupt Pending register */
238 #define AR_STA_ID0 0x8000 /* station ID0 - low 32 bits */
239 #define AR_STA_ID1 0x8004 /* station ID1 - upper 16 bits */
242 #define AR_SLOT_TIME 0x8010 /* Time-out after a collision */
243 #define AR_TIME_OUT 0x8014 /* ACK & CTS time-out */
264 #define AR_RTS_OK 0x8088 /* RTS exchange success counter */
265 #define AR_RTS_FAIL 0x808c /* RTS exchange failure counter */
266 #define AR_ACK_FAIL 0x8090 /* ACK failure counter */
267 #define AR_FCS_FAIL 0x8094 /* FCS check failure counter */
268 #define AR_BEACON_CNT 0x8098 /* Valid beacon counter */
275 #define AR_CR_SWI 0x00000040 /* One-shot software interrupt */
283 #define AR_CFG_AP_ADHOC_INDICATION 0x00000020 /* AP/adhoc indication (0-AP, 1-Adhoc) */
292 #define AR_IER_ENABLE 0x00000001 /* Global interrupt enable */
293 #define AR_IER_DISABLE 0x00000000 /* Global interrupt disable */
333 /* Maui2/Spirit only - reserved on Oahu */
334 #define AR_RXCFG_ZLFDMA 0x00000010 /* Enable DMA of zero-length frame */
338 #define AR_MIBC_COW 0x00000001 /* counter overflow warning */
341 #define AR_MIBC_MCS 0x00000008 /* MIB counter strobe, increment all */
369 /* Interrupt Status Registers */
371 #define AR_ISR_RXDESC 0x00000002 /* Receive interrupt request */
372 #define AR_ISR_RXERR 0x00000004 /* Receive error interrupt */
374 #define AR_ISR_RXEOL 0x00000010 /* Received descriptor empty interrupt */
375 #define AR_ISR_RXORN 0x00000020 /* Receive FIFO overrun interrupt */
376 #define AR_ISR_TXOK 0x00000040 /* Transmit okay interrupt */
377 #define AR_ISR_TXDESC 0x00000080 /* Transmit interrupt request */
378 #define AR_ISR_TXERR 0x00000100 /* Transmit error interrupt */
379 #define AR_ISR_TXNOPKT 0x00000200 /* No frame transmitted interrupt */
380 #define AR_ISR_TXEOL 0x00000400 /* Transmit descriptor empty interrupt */
381 #define AR_ISR_TXURN 0x00000800 /* Transmit FIFO underrun interrupt */
382 #define AR_ISR_MIB 0x00001000 /* MIB interrupt - see MIBC */
383 #define AR_ISR_SWI 0x00002000 /* Software interrupt */
384 #define AR_ISR_RXPHY 0x00004000 /* PHY receive error interrupt */
385 #define AR_ISR_RXKCM 0x00008000 /* Key-cache miss interrupt */
386 #define AR_ISR_SWBA 0x00010000 /* Software beacon alert interrupt */
387 #define AR_ISR_BRSSI 0x00020000 /* Beacon threshold interrupt */
388 #define AR_ISR_BMISS 0x00040000 /* Beacon missed interrupt */
390 #define AR_ISR_BNR 0x00100000 /* Beacon not ready interrupt */
391 #define AR_ISR_TIM 0x00800000 /* TIM interrupt */
392 #define AR_ISR_GPIO 0x01000000 /* GPIO Interrupt */
393 #define AR_ISR_QCBROVF 0x02000000 /* QCU CBR overflow interrupt */
394 #define AR_ISR_QCBRURN 0x04000000 /* QCU CBR underrun interrupt */
395 #define AR_ISR_QTRIG 0x08000000 /* QCU scheduling trigger interrupt */
398 #define AR_ISR_S0_QCU_TXOK_M 0x000003FF /* Mask for TXOK (QCU 0-9) */
399 #define AR_ISR_S0_QCU_TXDESC_M 0x03FF0000 /* Mask for TXDESC (QCU 0-9) */
401 #define AR_ISR_S1_QCU_TXERR_M 0x000003FF /* Mask for TXERR (QCU 0-9) */
402 #define AR_ISR_S1_QCU_TXEOL_M 0x03FF0000 /* Mask for TXEOL (QCU 0-9) */
404 #define AR_ISR_S2_QCU_TXURN_M 0x000003FF /* Mask for TXURN (QCU 0-9) */
405 #define AR_ISR_S2_MCABT 0x00010000 /* Master cycle abort interrupt */
406 #define AR_ISR_S2_SSERR 0x00020000 /* SERR interrupt */
410 #define AR_ISR_S3_QCU_QCBROVF_M 0x000003FF /* Mask for QCBROVF (QCU 0-9) */
411 #define AR_ISR_S3_QCU_QCBRURN_M 0x03FF0000 /* Mask for QCBRURN (QCU 0-9) */
413 #define AR_ISR_S4_QCU_QTRIG_M 0x000003FF /* Mask for QTRIG (QCU 0-9) */
416 /* Interrupt Mask Registers */
418 #define AR_IMR_RXDESC 0x00000002 /* Receive interrupt request */
419 #define AR_IMR_RXERR 0x00000004 /* Receive error interrupt */
421 #define AR_IMR_RXEOL 0x00000010 /* Received descriptor empty interrupt */
422 #define AR_IMR_RXORN 0x00000020 /* Receive FIFO overrun interrupt */
423 #define AR_IMR_TXOK 0x00000040 /* Transmit okay interrupt */
424 #define AR_IMR_TXDESC 0x00000080 /* Transmit interrupt request */
425 #define AR_IMR_TXERR 0x00000100 /* Transmit error interrupt */
426 #define AR_IMR_TXNOPKT 0x00000200 /* No frame transmitted interrupt */
427 #define AR_IMR_TXEOL 0x00000400 /* Transmit descriptor empty interrupt */
428 #define AR_IMR_TXURN 0x00000800 /* Transmit FIFO underrun interrupt */
429 #define AR_IMR_MIB 0x00001000 /* MIB interrupt - see MIBC */
430 #define AR_IMR_SWI 0x00002000 /* Software interrupt */
431 #define AR_IMR_RXPHY 0x00004000 /* PHY receive error interrupt */
432 #define AR_IMR_RXKCM 0x00008000 /* Key-cache miss interrupt */
433 #define AR_IMR_SWBA 0x00010000 /* Software beacon alert interrupt */
434 #define AR_IMR_BRSSI 0x00020000 /* Beacon threshold interrupt */
435 #define AR_IMR_BMISS 0x00040000 /* Beacon missed interrupt */
437 #define AR_IMR_BNR 0x00100000 /* BNR interrupt */
438 #define AR_IMR_TIM 0x00800000 /* TIM interrupt */
439 #define AR_IMR_GPIO 0x01000000 /* GPIO Interrupt */
440 #define AR_IMR_QCBROVF 0x02000000 /* QCU CBR overflow interrupt */
441 #define AR_IMR_QCBRURN 0x04000000 /* QCU CBR underrun interrupt */
442 #define AR_IMR_QTRIG 0x08000000 /* QCU scheduling trigger interrupt */
445 #define AR_IMR_S0_QCU_TXOK 0x000003FF /* Mask for TXOK (QCU 0-9) */
447 #define AR_IMR_S0_QCU_TXDESC 0x03FF0000 /* Mask for TXDESC (QCU 0-9) */
448 #define AR_IMR_S0_QCU_TXDESC_S 16 /* Shift for TXDESC (QCU 0-9) */
450 #define AR_IMR_S1_QCU_TXERR 0x000003FF /* Mask for TXERR (QCU 0-9) */
452 #define AR_IMR_S1_QCU_TXEOL 0x03FF0000 /* Mask for TXEOL (QCU 0-9) */
453 #define AR_IMR_S1_QCU_TXEOL_S 16 /* Shift for TXEOL (QCU 0-9) */
455 #define AR_IMR_S2_QCU_TXURN 0x000003FF /* Mask for TXURN (QCU 0-9) */
457 #define AR_IMR_S2_MCABT 0x00010000 /* Master cycle abort interrupt */
458 #define AR_IMR_S2_SSERR 0x00020000 /* SERR interrupt */
462 #define AR_IMR_S3_QCU_QCBROVF_M 0x000003FF /* Mask for QCBROVF (QCU 0-9) */
463 #define AR_IMR_S3_QCU_QCBRURN_M 0x03FF0000 /* Mask for QCBRURN (QCU 0-9) */
464 #define AR_IMR_S3_QCU_QCBRURN_S 16 /* Shift for QCBRURN (QCU 0-9) */
466 #define AR_IMR_S4_QCU_QTRIG_M 0x000003FF /* Mask for QTRIG (QCU 0-9) */
469 /* Interrupt status registers (read-and-clear access, secondary shadow copies) */
472 #define AR_NUM_QCU 10 /* Only use QCU 0-9 for forward QCU compatibility */
484 #define AR_Q_TXE_M 0x000003FF /* Mask for TXE (QCU 0-9) */
486 #define AR_Q_TXD_M 0x000003FF /* Mask for TXD (QCU 0-9) */
499 #define AR_Q_ONESHOTARM_SC_M 0x0000FFFF /* Mask for MAC_Q_ONESHOTARM_SC (QCU 0-15) */
502 #define AR_Q_ONESHOTARM_CC_M 0x0000FFFF /* Mask for MAC_Q_ONESHOTARM_CC (QCU 0-15) */
510 #define AR_Q_MISC_FSP_BEACON_SENT_GATED 4 /* Beacon-sent-gated */
512 #define AR_Q_MISC_CBR_INCR_DIS1 0x00000020 /* Disable CBR expired counter
514 #define AR_Q_MISC_CBR_INCR_DIS0 0x00000040 /* Disable CBR expired counter
517 #define AR_Q_MISC_CBR_EXP_CNTR_LIMIT 0x00000100 /* CBR expired counter limit enable */
519 #define AR_Q_MISC_RESET_CBR_EXP_CTR 0x00000400 /* Reset CBR expired counter */
525 #define AR_Q_STS_CBR_EXP_CNT_M 0x0000FF00 /* Mask for CBR expired counter */
528 #define AR_Q_RDYTIMESHDN_M 0x000003FF /* Mask for ReadyTimeShutdown status (QCU 0-9) */
543 #define AR_D_QCUMASK_M 0x000003FF /* Mask for QCU Mask (QCU 0-9) */
582 #define AR_D_MISC_ARB_LOCKOUT_CNTRL_INTRA_FR 1 /* Intra-frame */
586 #define AR_D_MISC_POST_FR_BKOFF_DIS 0x00200000 /* Post-frame backoff disable */
604 #define AR_D_TXPSE_CTRL_M 0x000003FF /* Mask of DCUs to pause (DCUs 0-9) */
614 #define AR_RC_PCI 0x00000010 /* PCI-core reset */
628 * However, these have been pre-shifted with AR_SCR_SLE_S. The
638 #define AR_INTPEND_TRUE 0x00000001 /* interrupt pending */
656 #define AR_PCICFG_SL_INTEN 0x00000800 /* enable interrupt line assertion when asleep */
658 #define AR_PCICFG_SL_INPEN 0x00002000 /* Force asleep when an interrupt is pending */
697 #define AR_GPIOCR_INT_SHIFT 12 /* Interrupt select field shifter */
698 #define AR_GPIOCR_INT_MASK 0x00007000 /* Interrupt select field mask */
699 #define AR_GPIOCR_INT_SEL0 0x00000000 /* Select Interrupt Pin GPIO_0 */
700 #define AR_GPIOCR_INT_SEL1 0x00001000 /* Select Interrupt Pin GPIO_1 */
701 #define AR_GPIOCR_INT_SEL2 0x00002000 /* Select Interrupt Pin GPIO_2 */
702 #define AR_GPIOCR_INT_SEL3 0x00003000 /* Select Interrupt Pin GPIO_3 */
703 #define AR_GPIOCR_INT_SEL4 0x00004000 /* Select Interrupt Pin GPIO_4 */
704 #define AR_GPIOCR_INT_SEL5 0x00005000 /* Select Interrupt Pin GPIO_5 */
705 #define AR_GPIOCR_INT_ENA 0x00008000 /* Enable GPIO Interrupt */
706 #define AR_GPIOCR_INT_SELL 0x00000000 /* Generate Interrupt if selected pin is low */
707 #define AR_GPIOCR_INT_SELH 0x00010000 /* Generate Interrupt if selected pin is high */
762 #define AR_STA_ID1_ADHOC 0x00020000 /* Device is ad-hoc */
763 #define AR_STA_ID1_PWR_SAV 0x00040000 /* Power save reporting in self-generated frames */
780 #define AR_TIME_OUT_ACK 0x00001FFF /* Mask for ACK time-out */
781 #define AR_TIME_OUT_ACK_S 0 /* Shift for ACK time-out */
782 #define AR_TIME_OUT_CTS 0x1FFF0000 /* Mask for CTS time-out */
783 #define AR_TIME_OUT_CTS_S 16 /* Shift for CTS time-out */
841 #define AR_DIAG_SW_FRAME_NV0 0x00020000 /* accept frames of non-zero protocol version */
848 #define AR_KEYTABLE_KEY0(n) (AR_KEYTABLE(n) + 0) /* key bit 0-31 */
849 #define AR_KEYTABLE_KEY1(n) (AR_KEYTABLE(n) + 4) /* key bit 32-47 */
850 #define AR_KEYTABLE_KEY2(n) (AR_KEYTABLE(n) + 8) /* key bit 48-79 */
851 #define AR_KEYTABLE_KEY3(n) (AR_KEYTABLE(n) + 12) /* key bit 80-95 */
852 #define AR_KEYTABLE_KEY4(n) (AR_KEYTABLE(n) + 16) /* key bit 96-127 */
859 #define AR_KEYTABLE_MAC0(n) (AR_KEYTABLE(n) + 24) /* MAC address 1-32 */
860 #define AR_KEYTABLE_MAC1(n) (AR_KEYTABLE(n) + 28) /* MAC address 33-47 */