Lines Matching +full:interrupt +full:- +full:counter
1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
101 /* [0x6c] Read-only that reflects CPU Cluster Local GIC base high address */
103 /* [0x70] Read-only that reflects CPU Cluster Local GIC base low address */
105 /* [0x74] Read-only that reflects the device's IOGIC base high address. */
107 /* [0x78] Read-only that reflects IOGIC base low address */
341 /* [0x0] Counter Configuration Register */
343 /* [0x4] Counter Control Register */
345 /* [0x8] Counter Control Register */
347 /* [0xc] Counter Control Register */
398 /* [0x0] Counter Configuration Register */
480 /* Value read in the Cluster ID Affinity Level-1 field, bits[15:8], of the Multiprocessor Affinity
485 /* Value read in the Cluster ID Affinity Level-2 field, bits[23:16], of the Multiprocessor Affinity
512 By default, CPU0 only exits poreset when the CPUs cluster exits power-on-reset and then kicks other…
513 …t by primary CPU as part of the initialization process will initiate power-on-reset to this specif…
521 /* Force CPU init power-on-reset exit.
540 * Level IRQ indices: 12-13, 23, 24, 26-29
543 /* Cross trigger interrupt */
556 /* Error indicator for: L2 RAM double-bit ECC error, illegal writes to the GIC memory-map region. */
558 /* Coherent fabric error summary interrupt */
560 /* DDR Controller ECC Correctable error summary interrupt */
562 /* DDR Controller ECC Uncorrectable error summary interrupt */
564 /* DRAM parity error interrupt */
568 /* Error cause summary interrupt */
572 /* Received msix is not mapped to local GIC or IO-GIC spin */
578 /* SMMU 0/1 global non-secure fault interrupt */
581 /* SMMU 0/1 non-secure context interrupt */
584 /* SMMU0/1 Non-secure configuration access fault interrupt */
595 /* CPUs PMU Overflow interrupt */
616 /* Shared L2 memory system, interrupt controller and timer logic reset.
628 /* Individual CPU por-on-reset.
632 /* Wait for interrupt mask.
641 0x0 - cpu_core: Individual CPU core reset.
642 0x1 - cpu_poreset: Individual CPU power-on-reset.
643 0x2 - cpu_dbg: Individual CPU debug reset.
644 0x3 - cluster_no_dbg: A Cluster reset puts each core into core reset (no dbg) and also resets the i…
645 0x4 - cluster: A Cluster reset puts each core into power-on-reset and also resets the interrupt con…
646 0x5 - cluster_poreset: A Cluster power-on-reset puts each core into power-on-reset and also resets …
652 /* Individual CPU power-on-reset. */
661 /* A Cluster reset puts each core into power-on-reset and also r ... */
664 /* A Cluster power-on-reset puts each core into power-on-reset a ... */
670 /* CPUn wait for interrupt enable.
676 /* Shared L2 memory system, interrupt controller and timer logic reset */
686 /* Individual CPU por-on-reset */
691 /* Shared L2 memory system, interrupt controller and timer logic reset */
701 /* Individual CPU por-on-reset */
706 /* Shared L2 memory system, interrupt controller and timer logic reset */
716 /* Individual CPU por-on-reset */
721 /* Shared L2 memory system, interrupt controller and timer logic reset */
731 /* Individual CPU por-on-reset */
737 0 - Reset is deasserted.
738 1 - Reset is asserted (active). */
741 0 - Reset is deasserted.
742 1 - Reset is asserted.
746 0 - Reset is deasserted.
747 1 - Reset is asserted.
751 0 - Reset is deasserted.
752 1 - Reset is asserted.
756 0 - Reset is deasserted.
757 1 - Reset is asserted.
761 0 - Reset is deasserted.
762 1 - Reset is asserted. */
771 0x0 - fabric: Fabric reset
772 0x1 - gic: GIC reset
773 0x2 - smmu: SMMU reset */
785 /* CPUn waiting for interrupt enable.
792 …ors are in WFI mode or powered-down, the shared L2 memory system Power Management controller resum…
804 0 - Power down
805 1 - WFI
809 /* Enable external debugger over power-down.
833 non-bufferable. One bit exists for each master interface.
848 Enables 4k hazard of post-barrier vs pre-barrier transactions. Otherwise, 64B hazard granularity is…
878 If store and forward is disabled, splitter does not check non-active BE in the middle of a transact…
885 /* Write splitters unsplit non-coherent access.
886 Disables splitting of non-coherent access to cache-line chunks. */
935 When valid, an interrupt is set in the NB Cause Register. */
947 /* Received msix is not mapped to local GIC or IO-GIC spin */
961 /* Coherent fabric error summary interrupt */
965 /* Error indicator for: L2 RAM double-bit ECC error, illegal writes to the GIC memory-map region. */
967 /* DDR cause summery interrupt */
972 …g read transactions from SB masters is below this value, the CPU is assigned high-priority QoS. */
976 …ng read transactions from SB masters exceeds this value, the CPU is assigned high-priority QoS. */
980 …g write transactions from SB masters is below this value, the CPU is assigned high-priority QoS */
984 …g write transactions from SB masters exceeds this value, the CPU is assigned high-priority QoS. */
1004 /* SB Low-priority Write QoS */
1021 Performance optimization feature to chop non-active data beats to the DDR. */
1023 /* Disable SB-2-SB path through NB fabric. */
1025 /* Disable ETR tracing to non-DDR. */
1027 /* Disable ETR tracing to non-DDR. */
1030 By default, the CPU can set any MSIx message results by setting any SPIn bit in the local and IO-GI…
1033 By default, an MSIx transaction is downgraded to non-coherent. */
1043 On DSB from CPU, PoS blocks the progress of post-barrier reads and writes until all pre-barrier wri…
1046 …CPU, the PoS blocks the progress of post-barrier non-buffereable reads or writes when there are ou…
1047 Other access types are hazard check against the pre-barrier requests. */
1055 /* Disable counter (wait 1000 NB cycles) before applying PoS enable/disable configuration */
1061 /* Override the address parity calucation for write transactions going to IO-fabric */
1063 /* Override the data parity calucation for write transactions going to IO-fabric */
1065 /* Override the address parity calucation for read transactions going to IO-fabric */
1071 /* Enable wire interrupts connectivity to IO-GIC IRQs */
1170 …the ROM table physical address to the physical address where the debug registers are memory-mapped.
1174 …the ROM table physical address to the physical address where the debug registers are memory-mapped.
1198 /* System counter enable
1199 Counter is enabled after reset. */
1201 /* System counter restart
1205 /* Disable CTI trigger out that halt the counter progress */
1207 /* System counter tick
1208 Specifies the counter tick rate relative to the Northbridge clock, e.g., the counter is incremented…
1323 /* NB PMC HVT35 counter value */
1326 /* NB PMC SVT31 counter value */
1418 [3:2] Target queue - 0:ASI, 1: AMI
1419 [1:0]: Target Processor Cluster - 0: Cluster0, 1: Cluster1 */
1447 little - 0x0: Little endian
1448 bit - 0x1: Bit endian */
1456 low - 0x0: Exception vectors start at address 0x00000000.
1457 high - 0x1: Exception vectors start at address 0xFFFF0000. */
1485 poweredoff: 0x3: Powered-off power mode */
1494 /* Powered-off power mode */
1503 /* Disable wakeup from Local--GIC FIQ. */
1505 /* Disable wakeup from Local-GIC IRQ. */
1507 /* Disable wakeup from IO-GIC FIQ. */
1509 /* Disable wakeup from IO-GIC IRQ. */
1511 /* Disable scheduling of interrrupts in GIC(500) to non-active CPU */
1515 /* Read-only bits that reflect the individual CPU power mode status.
1516 Default value for non-exist CPU is 2b11:
1517 normal - 0x0: Normal mode
1518 por - 0x1: por on reset mode
1519 deep_idle - 0x2: Dormant power mode state
1520 poweredoff - 0x3: Powered-off power mode */
1532 /* Powered-off power mode */
1577 When this bit is clear, counter state is determined through the specific counter control register */
1580 When this bit is clear, counter state is determined through the specific counter control register. …
1582 /* Overflow interrupt enable:
1583 disable - 0x0: Disable interrupt on overflow.
1584 enable - 0x1: Enable interrupt on overflow. */
1598 /* Enable setting of counter low overflow status bit:
1599 disable - 0x0: Disable setting.
1600 enable - 0x1: Enable setting. */
1602 /* Enable setting of counter high overflow status bit:
1603 disable - 0x0: Disable setting.
1604 enable - 0x1: Enable setting. */
1607 disable - 0x0: Disable pause.
1608 enable - 0x1: Enable pause. */
1611 Trigger is generated whenever counter reaches <granule> value:
1612 disable - 0x0: Disable trigger out.
1613 enable - 0x1: Enable trigger out. */
1617 0x0: 1 - Trigger out on every event occurrence.
1618 0x1: 2 - Trigger out on every two events.
1620 0xn: 2^(n-1) - Trigger out on event 2^(n-1) events.
1626 If set for counter <i>, current counter pauses counting when counter<i> is overflowed, including se…
1627 Bit [16]: counter 0
1628 Bit [17]: counter 1
1634 /* Set the counter state to disable, enable, or pause:
1635 0x0 - disable: Disable counter.
1636 0x1 - enable: Enable counter.
1637 0x3 - pause: Pause counter. */
1640 /* Disable counter. */
1643 /* Enable counter. */
1646 /* Pause counter. */
1651 /* Counter high value */
1679 /* Target-ID */
1714 /* This interrupt is asserted when a correctable ECC error is detected */
1716 /* This interrupt is asserted when a uncorrectable ECC error is detected */
1718 /* This interrupt is asserted when a parity or CRC error is detected on the DFI interface */
1720 /* On-Chip Write data parity error interrupt on output */
1722 /* This interrupt is asserted when a parity error due to MRS is detected on the DFI interface */
1724 /* This interrupt is asserted when the CRC/parity retry counter reaches it maximum value */
1726 /* AXI Read address parity error interrupt.
1727 This interrupt is asserted when an on-chip parity error occurred on the DDR controller AXI read add…
1729 /* AXI Read data parity error interrupt.
1730 This interrupt is asserted when an on-chip parity error occurred on the DDR controller AXI read dat…
1732 /* AXI Write address parity error interrupt.
1733 This interrupt is asserted when an on-chip parity error occurred on the DDR controller AXI write ad…
1735 /* AXI Write data parity error interrupt on input.
1736 This interrupt is asserted when an on-chip parity error occurred on the DDR controller AXI write da…
1757 When set, addrmap_row_b2-5 are used inside DDR controler instead of the built in address mapping re…