Lines Matching +full:interrupt +full:- +full:counter
3 /*-
4 * SPDX-License-Identifier: BSD-2-Clause
34 /*-
70 * - Am7990 Local Area Network Controller for Ethernet (LANCE)
71 * (and its descendent Am79c90 C-LANCE).
73 * - Am79c900 Integrated Local Area Communications Controller (ILACC)
75 * - Am79c960 PCnet-ISA Single-Chip Ethernet Controller for ISA
77 * - Am79c961 PCnet-ISA+ Jumperless Single-Chip Ethernet Controller
80 * - Am79c961A PCnet-ISA II Jumperless Full-Duplex Single-Chip
83 * - Am79c965A PCnet-32 Single-Chip 32-bit Ethernet Controller
86 * - Am79c970 PCnet-PCI Single-Chip Ethernet Controller for PCI
89 * - Am79c970A PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller
92 * - Am79c971 PCnet-FAST Single-Chip Full-Duplex 10/100Mbps
95 * - Am79c972 PCnet-FAST+ Enhanced 10/100Mbps PCI Ethernet Controller
98 * - Am79c973/Am79c975 PCnet-FAST III Single-Chip 10/100Mbps PCI
101 * - Am79c978 PCnet-Home Single-Chip 1/10 Mbps PCI Home
107 * 16-bit software model (LANCE) am7990reg.h
109 * 32-bit software model (ILACC) am79900reg.h
112 * belong to follow-on chips to the original LANCE. Only CSR0-CSR3 are
122 #define LEMINSIZE (ETHER_MIN_LEN - ETHER_CRC_LEN)
124 #define LE_INITADDR(sc) (sc->sc_initaddr)
125 #define LE_RMDADDR(sc, bix) (sc->sc_rmdaddr + sizeof(struct lermd) * (bix))
126 #define LE_TMDADDR(sc, bix) (sc->sc_tmdaddr + sizeof(struct letmd) * (bix))
127 #define LE_RBUFADDR(sc, bix) (sc->sc_rbufaddr + LEBLEN * (bix))
128 #define LE_TBUFADDR(sc, bix) (sc->sc_tbufaddr + LEBLEN * (bix))
144 #define LE_CSR5 0x0005 /* Extended control and Interrupt 1 */
146 #define LE_CSR7 0x0007 /* Extended control and interrupt 2 */
185 #define LE_CSR46 0x002e /* Tx Poll Time Counter */
187 #define LE_CSR48 0x0030 /* Rx Poll Time Counter */
198 #define LE_CSR72 0x0048 /* Receive Ring Counter */
199 #define LE_CSR74 0x004a /* Transmit Ring Counter */
202 #define LE_CSR80 0x0050 /* DMA Transfer Counter and FIFO
207 #define LE_CSR86 0x0056 /* Buffer Byte Counter */
229 #define LE_BCR9 0x0009 /* Full-duplex Control */
270 #define LE_C0_RINT 0x0400 /* receiver interrupt */
271 #define LE_C0_TINT 0x0200 /* transmitter interrupt */
273 #define LE_C0_INTR 0x0080 /* interrupt condition */
274 #define LE_C0_INEA 0x0040 /* interrupt enable */
290 #define LE_C3_RINTM 0x0400 /* receive interrupt mask */
291 #define LE_C3_TINTM 0x0200 /* transmit interrupt mask */
303 #define LE_C4_DMAPLUS 0x4000 /* always set (PCnet-PCI) */
308 #define LE_C4_MFCO 0x0200 /* missed frame counter overflow */
310 #define LE_C4_UINTCMD 0x0080 /* user interrupt command */
311 #define LE_C4_UINT 0x0040 /* user interrupt */
312 #define LE_C4_RCVCCO 0x0020 /* receive collision counter overflow */
313 #define LE_C4_RCVCCOM 0x0010 /* receive collision counter overflow
319 #define LE_C5_TOKINTD 0x8000 /* transmit ok interrupt disable */
320 #define LE_C5_LTINTEN 0x4000 /* last transmit interrupt enable */
321 #define LE_C5_SINT 0x0800 /* system interrupt */
322 #define LE_C5_SINTE 0x0400 /* system interrupt enable */
323 #define LE_C5_EXDINT 0x0080 /* excessive deferral interrupt */
324 #define LE_C5_EXDINTE 0x0040 /* excessive deferral interrupt enbl */
327 #define LE_C5_MPINT 0x0010 /* magic packet interrupt */
328 #define LE_C5_MPINTE 0x0008 /* magic packet interrupt enable */
341 #define LE_C7_STINT 0x0800 /* software timer interrupt */
342 #define LE_C7_STINTE 0x0400 /* software timer interrupt enable */
346 #define LE_C7_MAPINT 0x0080 /* PHY management auto-poll intr */
347 #define LE_C7_MAPINTE 0x0040 /* PHY management auto-poll intr
350 interrupt */
352 interrupt enable */
354 internal interrupt */
356 internal interrupt enable */
358 interrupt */
360 interrupt enable */
367 #define LE_C15_DAPC 0x0800 /* disable auto-polarity correction */
393 #define LE_C80_DMATC 0x00ff /* DMA transfer counter */
413 #define LE_C125_IPG 0xff00 /* inter-packet gap */
414 #define LE_C125_IFS1 0x00ff /* inter-frame spacing part 1 */
431 #define LE_B2_ASEL 0x0002 /* auto-select PORTSEL */
444 #define LE_B4_FDLSE 0x0100 /* full-duplex link status enable */
455 #define LE_B9_FDRPAD 0x0004 /* full-duplex runt packet accept
457 #define LE_B9_AUIFD 0x0002 /* AUI full-duplex */
458 #define LE_B9_FDEN 0x0001 /* full-duplex enable */
465 #define LE_B18_DWIO 0x0080 /* double-word I/O */
488 #define LE_B20_CSRPCNET 0x0200 /* PCnet-style CSRs (0 = ILACC) */
489 #define LE_B20_SSIZE32 0x0100 /* Software Size 32-bit */
491 #define LE_B20_SSTYLE_LANCE 0 /* LANCE/PCnet-ISA (16-bit) */
492 #define LE_B20_SSTYLE_ILACC 1 /* ILACC (32-bit) */
493 #define LE_B20_SSTYLE_PCNETPCI2 2 /* PCnet-PCI (32-bit) */
494 #define LE_B20_SSTYLE_PCNETPCI3 3 /* PCnet-PCI II (32-bit) */
536 #define LE_B32_APEP 0x0800 /* auto-poll PHY */
537 #define LE_B32_APDW 0x0700 /* auto-poll dwell time */
541 #define LE_B32_XPHYFD 0x0010 /* PHY full-duplex */
550 #define LE_B33_FDX 0x0800 /* full-duplex */
560 #define LE_B49_PCNET 0x8000 /* PCnet mode - Must Be One */
572 /* 0x4000 - 0x0080 are not available on LANCE 7990. */