Lines Matching +full:interrupt +full:- +full:counter
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
30 * from: FreeBSD: if_gemreg.h 174987 2007-12-30 01:32:03Z marius
44 #define CAS_STATUS 0x000c /* interrupt status */
45 #define CAS_INTMASK 0x0010 /* interrupt mask */
47 #define CAS_STATUS_ALIAS 0x001c /* interrupt status alias */
59 #define CAS_INTMASK2 0x1038 /* interrupt mask 2 for INTB */
60 #define CAS_STATUS2 0x103c /* interrupt status 2 for INTB */
62 #define CAS_STATUS_ALIAS2 0x1044 /* interrupt status alias 2 for INTB */
63 #define CAS_INTMASK3 0x1048 /* interrupt mask 3 for INTC */
64 #define CAS_STATUS3 0x104c /* interrupt status 3 for INTC */
66 #define CAS_STATUS_ALIAS3 0x1054 /* interrupt status alias 3 for INTC */
67 #define CAS_INTMASK4 0x1058 /* interrupt mask 4 for INTD */
68 #define CAS_STATUS4 0x105c /* interrupt status 4 for INTD */
70 #define CAS_STATUS_ALIAS4 0x1064 /* interrupt status alias 4 for INTD */
82 * shared interrupt bits for CAS_STATUS, CAS_INTMASK, CAS_CLEAR_ALIAS and
84 * Bits 0-9 of CAS_STATUS auto-clear when read. CAS_CLEAR_ALIAS specifies
85 * which of bits 0-9 auto-clear when reading CAS_STATUS_ALIAS.
98 #define CAS_INTR_SUMMARY 0x00001000 /* summary interrupt bit */
99 #define CAS_INTR_PCS_INT 0x00002000 /* PCS interrupt */
100 #define CAS_INTR_TX_MAC_INT 0x00004000 /* TX MAC interrupt */
101 #define CAS_INTR_RX_MAC_INT 0x00008000 /* RX MAC interrupt */
102 #define CAS_INTR_MAC_CTRL_INT 0x00010000 /* MAC control interrupt */
103 #define CAS_INTR_MIF 0x00020000 /* MIF interrupt */
104 #define CAS_INTR_PCI_ERROR_INT 0x00040000 /* PCI error interrupt */
116 #define CAS_BIM_CONF_BD64_DIS 0x00000004 /* 64-bit mode disable */
118 #define CAS_BIM_CONF_BUS32_WIDE 0x00000010 /* PCI bus is 32-bit (ro). */
161 * interrupt bits for CAS_INTMASK[2-4], CAS_STATUS[2-4], CAS_CLEAR_ALIAS[2-4]
162 * and CAS_STATUS_ALIAS[2-4].
163 * CAS_STATUS[2-4] auto-clear when read. CAS_CLEAR_ALIAS[2-4] specifies which
164 * of bits 0-9 auto-clear when reading the corresponding CAS_STATUS_ALIAS[2-4].
172 /* INTn enable bit for CAS_INTMASK[2-4] */
173 #define CAS_INTMASKN_EN 0x00000080 /* INT[B-D] enable */
179 #define CAS_SATURN_PCFG_RLA 0x00000010 /* PHY full-duplex LED */
192 #define CAS_TX_FIFO_PKT_CNT 0x2024 /* FIFO packet counter */
243 #define CAS_TX_CONF_PICWB_DIS 0x20000000 /* pre-intr. compl. W/B dis. */
303 #define CAS_RX_IPP_PKT_CNT 0x4054 /* RX IPP packet counter */
649 #define CAS_MAC_NORM_COLL_CNT 0x61a0 /* normal collision counter */
650 #define CAS_MAC_FIRST_COLL_CNT 0x61a4 /* 1st attempt suc. collision counter */
651 #define CAS_MAC_EXCESS_COLL_CNT 0x61a8 /* excess collision counter */
652 #define CAS_MAC_LATE_COLL_CNT 0x61ac /* late collision counter */
655 #define CAS_MAC_RX_FRAME_COUNT 0x61b8 /* receive frame counter */
656 #define CAS_MAC_RX_LEN_ERR_CNT 0x61bc /* length error counter */
657 #define CAS_MAC_RX_ALIGN_ERR 0x61c0 /* alignment error counter */
658 #define CAS_MAC_RX_CRC_ERR_CNT 0x61c4 /* FCS error counter */
659 #define CAS_MAC_RX_CODE_VIOL 0x61c8 /* RX code violation error counter */
671 #define CAS_MAC_TX_NCC_EXP 0x00000008 /* normal coll. counter wrap */
672 #define CAS_MAC_TX_ECC_EXP 0x00000010 /* excess coll. counter wrap */
673 #define CAS_MAC_TX_LCC_EXP 0x00000020 /* late coll. counter wrap */
674 #define CAS_MAC_TX_FCC_EXP 0x00000040 /* 1st coll. counter wrap */
676 #define CAS_MAC_TX_PEAK_EXP 0x00000100 /* peak attempts counter wrap */
681 #define CAS_MAC_RX_FRAME_EXP 0x00000004 /* RX frame counter wrap */
683 #define CAS_MAC_RX_CRC_EXP 0x00000010 /* CRC error counter wrap */
684 #define CAS_MAC_RX_LEN_EXP 0x00000020 /* length error counter wrap */
698 #define CAS_MAC_TX_CONF_EN_IPG0 0x00000008 /* extend RX-to-TX IPG */
742 * The bit-bang registers use the low bit only.
744 #define CAS_MIF_BB_CLOCK 0x6200 /* MIF bit-bang clock */
745 #define CAS_MIF_BB_DATA 0x6204 /* MIF bit-bang data */
746 #define CAS_MIF_BB_OUTPUT_EN 0x6208 /* MIF bit-bang output enable */
774 #define CAS_MIF_CONF_BB_MODE 0x00000004 /* bit-bang mode enable */
799 #define CAS_PCS_INTR_STATUS 0x9018 /* PCS interrupt status */
804 #define CAS_PCS_PKT_CNT 0x9060 /* PCS packet counter */
808 #define CAS_PCS_CTRL_FDX 0x00000100 /* full-duplex, always 0 */
809 #define CAS_PCS_CTRL_RANEG 0x00000200 /* restart auto-negotiation */
812 #define CAS_PCS_CTRL_ANEG_EN 0x00001000 /* auto-negotiation enable */
819 #define CAS_PCS_STATUS_ANEG_ABL 0x00000008 /* auto-negotiation ability */
821 #define CAS_PCS_STATUS_ANEG_CPT 0x00000020 /* auto-negotiate complete */
825 #define CAS_PCS_ANEG_FDX 0x00000020 /* full-duplex */
826 #define CAS_PCS_ANEG_HDX 0x00000040 /* half-duplex */
829 #define CAS_PCS_ANEG_RFLT_FAIL 0x00001000 /* remote fault - fail */
830 #define CAS_PCS_ANEG_RFLT_OFF 0x00002000 /* remote fault - off-line */
838 #define CAS_PCS_CONF_SDL 0x00000004 /* signal detect active-low */
839 #define CAS_PCS_CONF_JS_NORM 0x00000000 /* jitter study - normal op. */
840 #define CAS_PCS_CONF_JS_HF 0x00000008 /* jitter study - HF test */
841 #define CAS_PCS_CONF_JS_LF 0x00000010 /* jitter study - LF test */
843 #define CAS_PCS_CONF_ANEG_TO 0x00000020 /* auto-neg. timer override */
856 #define CAS_PCS_SM_LOSS_C 0x00100000 /* link-loss due to C codes */
857 #define CAS_PCS_SM_LOSS_SYNC 0x00200000 /* link-loss due to sync-loss */
873 #define CAS_PCS_DATAPATH_SERDES 0x00000002 /* SERDES via 10-bit */
875 #define CAS_PCS_SERDES_CTRL_LBK 0x00000001 /* loopback at 10-bit enable */
963 #define CAS_RC1_TYPE_RNRP 0x8000000000000000ULL /* non-reas. pkt... */
977 #define CAS_RC3_SMALL_PKT 0x0000000000000001ULL /* pkt. <= 256 - SOFF */