Lines Matching +full:interrupt +full:- +full:counter
1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2008 Atheros Communications, Inc.
26 /* DMA Control and Interrupt Registers */
30 #define AR_IER 0x0024 /* MAC Interrupt enable register */
46 #define AR_ISR 0x0080 /* MAC Primary interrupt status register */
47 #define AR_ISR_S0 0x0084 /* MAC Secondary interrupt status register 0 */
48 #define AR_ISR_S1 0x0088 /* MAC Secondary interrupt status register 1 */
49 #define AR_ISR_S2 0x008c /* MAC Secondary interrupt status register 2 */
50 #define AR_ISR_S3 0x0090 /* MAC Secondary interrupt status register 3 */
51 #define AR_ISR_S4 0x0094 /* MAC Secondary interrupt status register 4 */
52 #define AR_IMR 0x00a0 /* MAC Primary interrupt mask register */
53 #define AR_IMR_S0 0x00a4 /* MAC Secondary interrupt mask register 0 */
54 #define AR_IMR_S1 0x00a8 /* MAC Secondary interrupt mask register 1 */
55 #define AR_IMR_S2 0x00ac /* MAC Secondary interrupt mask register 2 */
56 #define AR_IMR_S3 0x00b0 /* MAC Secondary interrupt mask register 3 */
57 #define AR_IMR_S4 0x00b4 /* MAC Secondary interrupt mask register 4 */
58 #define AR_ISR_RAC 0x00c0 /* ISR read-and-clear access */
59 /* Shadow copies with read-and-clear access */
78 #define AR_CPC_0 0x0610 /* Compression performance counter 0 */
79 #define AR_CPC_1 0x0614 /* Compression performance counter 1 */
80 #define AR_CPC_2 0x0618 /* Compression performance counter 2 */
81 #define AR_CPC_3 0x061c /* Compression performance counter 3 */
97 #define AR_Q_TXE_M 0x000003FF /* Mask for TXE (QCU 0-9) */
99 #define AR_Q_TXD_M 0x000003FF /* Mask for TXD (QCU 0-9) */
169 #define AR_D0_LCL_IFS 0x1040 /* MAC DCU-specific IFS settings */
170 #define AR_D1_LCL_IFS 0x1044 /* MAC DCU-specific IFS settings */
171 #define AR_D2_LCL_IFS 0x1048 /* MAC DCU-specific IFS settings */
172 #define AR_D3_LCL_IFS 0x104c /* MAC DCU-specific IFS settings */
173 #define AR_D4_LCL_IFS 0x1050 /* MAC DCU-specific IFS settings */
174 #define AR_D5_LCL_IFS 0x1054 /* MAC DCU-specific IFS settings */
175 #define AR_D6_LCL_IFS 0x1058 /* MAC DCU-specific IFS settings */
176 #define AR_D7_LCL_IFS 0x105c /* MAC DCU-specific IFS settings */
177 #define AR_D8_LCL_IFS 0x1060 /* MAC DCU-specific IFS settings */
178 #define AR_D9_LCL_IFS 0x1064 /* MAC DCU-specific IFS settings */
205 #define AR_D0_MISC 0x1100 /* MAC Miscellaneous DCU-specific settings */
206 #define AR_D1_MISC 0x1104 /* MAC Miscellaneous DCU-specific settings */
207 #define AR_D2_MISC 0x1108 /* MAC Miscellaneous DCU-specific settings */
208 #define AR_D3_MISC 0x110c /* MAC Miscellaneous DCU-specific settings */
209 #define AR_D4_MISC 0x1110 /* MAC Miscellaneous DCU-specific settings */
210 #define AR_D5_MISC 0x1114 /* MAC Miscellaneous DCU-specific settings */
211 #define AR_D6_MISC 0x1118 /* MAC Miscellaneous DCU-specific settings */
212 #define AR_D7_MISC 0x111c /* MAC Miscellaneous DCU-specific settings */
213 #define AR_D8_MISC 0x1120 /* MAC Miscellaneous DCU-specific settings */
214 #define AR_D9_MISC 0x1124 /* MAC Miscellaneous DCU-specific settings */
219 /* MAC DCU-global IFS settings */
233 #define AR_INTPEND 0x4008 /* Interrupt Pending register */
253 #define AR_STA_ID0 0x8000 /* MAC station ID0 register - low 32 bits */
254 #define AR_STA_ID1 0x8004 /* MAC station ID1 register - upper 16 bits */
257 #define AR_SLOT_TIME 0x8010 /* MAC Time-out after a collision */
258 #define AR_TIME_OUT 0x8014 /* MAC ACK & CTS time-out */
283 #define AR_RTS_OK 0x8088 /* MAC RTS exchange success counter */
284 #define AR_RTS_FAIL 0x808c /* MAC RTS exchange failure counter */
285 #define AR_ACK_FAIL 0x8090 /* MAC ACK failure counter */
286 #define AR_FCS_FAIL 0x8094 /* FCS check failure counter */
287 #define AR_BEACON_CNT 0x8098 /* Valid beacon counter */
298 #define AR_CCCNT 0x80f8 /* Profile count, cycle counter */
321 /* Hainan MIB counter registers */
324 #define AR_PHYCNT1 0x812c /* Phy Error 1 counter */
325 #define AR_PHYCNTMASK1 0x8130 /* Phy Error 1 counter mask */
326 #define AR_PHYCNT2 0x8134 /* Phy Error 2 counter */
327 #define AR_PHYCNTMASK2 0x8138 /* Phy Error 2 counter mask */
328 #define AR_PHY_COUNTMAX (3 << 22) /* Max value in counter before intr */
331 #define AR_RATE_DURATION_0 0x8700 /* base of multi-rate retry */
341 #define AR_CR_SWI 0x00000040 /* One-shot software interrupt */
348 #define AR_CFG_AP_ADHOC_INDICATION 0x00000020 /* AP/adhoc indication (0-AP, 1-Adhoc) */
355 #define AR_IER_ENABLE 0x00000001 /* Global interrupt enable */
356 #define AR_IER_DISABLE 0x00000000 /* Global interrupt disable */
375 #define AR_RXCFG_ZLFDMA 0x00000010 /* Enable DMA of zero-length frame */
377 #define AR_MIBC_COW 0x00000001 /* counter overflow warning */
380 #define AR_MIBC_MCS 0x00000008 /* MIB counter strobe, increment all */
405 * Interrupt Status Registers
409 * the secondary interrupt status/mask registers control what bits
410 * are set in the primary interrupt status register; however the
413 * and IMR_P is non-zero. The secondary interrupt mask/status
418 #define AR_ISR_RXDESC 0x00000002 /* Receive interrupt request */
419 #define AR_ISR_RXERR 0x00000004 /* Receive error interrupt */
421 #define AR_ISR_RXEOL 0x00000010 /* Received descriptor empty interrupt */
422 #define AR_ISR_RXORN 0x00000020 /* Receive FIFO overrun interrupt */
423 #define AR_ISR_TXOK 0x00000040 /* Transmit okay interrupt */
424 #define AR_ISR_TXDESC 0x00000080 /* Transmit interrupt request */
425 #define AR_ISR_TXERR 0x00000100 /* Transmit error interrupt */
426 #define AR_ISR_TXNOPKT 0x00000200 /* No frame transmitted interrupt */
427 #define AR_ISR_TXEOL 0x00000400 /* Transmit descriptor empty interrupt */
428 #define AR_ISR_TXURN 0x00000800 /* Transmit FIFO underrun interrupt */
429 #define AR_ISR_MIB 0x00001000 /* MIB interrupt - see MIBC */
430 #define AR_ISR_SWI 0x00002000 /* Software interrupt */
431 #define AR_ISR_RXPHY 0x00004000 /* PHY receive error interrupt */
432 #define AR_ISR_RXKCM 0x00008000 /* Key-cache miss interrupt */
433 #define AR_ISR_SWBA 0x00010000 /* Software beacon alert interrupt */
434 #define AR_ISR_BRSSI 0x00020000 /* Beacon threshold interrupt */
435 #define AR_ISR_BMISS 0x00040000 /* Beacon missed interrupt */
437 #define AR_ISR_BNR 0x00100000 /* Beacon not ready interrupt */
442 #define AR_ISR_TIM 0x00800000 /* TIM interrupt */
443 #define AR_ISR_GPIO 0x01000000 /* GPIO Interrupt */
444 #define AR_ISR_QCBROVF 0x02000000 /* QCU CBR overflow interrupt */
445 #define AR_ISR_QCBRURN 0x04000000 /* QCU CBR underrun interrupt */
446 #define AR_ISR_QTRIG 0x08000000 /* QCU scheduling trigger interrupt */
449 #define AR_ISR_S0_QCU_TXOK 0x000003FF /* Mask for TXOK (QCU 0-9) */
451 #define AR_ISR_S0_QCU_TXDESC 0x03FF0000 /* Mask for TXDESC (QCU 0-9) */
454 #define AR_ISR_S1_QCU_TXERR 0x000003FF /* Mask for TXERR (QCU 0-9) */
456 #define AR_ISR_S1_QCU_TXEOL 0x03FF0000 /* Mask for TXEOL (QCU 0-9) */
459 #define AR_ISR_S2_QCU_TXURN 0x000003FF /* Mask for TXURN (QCU 0-9) */
460 #define AR_ISR_S2_MCABT 0x00010000 /* Master cycle abort interrupt */
461 #define AR_ISR_S2_SSERR 0x00020000 /* SERR interrupt */
472 #define AR_ISR_S3_QCU_QCBROVF 0x000003FF /* Mask for QCBROVF (QCU 0-9) */
473 #define AR_ISR_S3_QCU_QCBRURN 0x03FF0000 /* Mask for QCBRURN (QCU 0-9) */
475 #define AR_ISR_S4_QCU_QTRIG 0x000003FF /* Mask for QTRIG (QCU 0-9) */
479 * Interrupt Mask Registers
482 * output will be asserted. The bits in the secondary interrupt
484 * interrupt status register; however the IMR_S* registers
488 #define AR_IMR_RXDESC 0x00000002 /* Receive interrupt request */
489 #define AR_IMR_RXERR 0x00000004 /* Receive error interrupt */
491 #define AR_IMR_RXEOL 0x00000010 /* Received descriptor empty interrupt */
492 #define AR_IMR_RXORN 0x00000020 /* Receive FIFO overrun interrupt */
493 #define AR_IMR_TXOK 0x00000040 /* Transmit okay interrupt */
494 #define AR_IMR_TXDESC 0x00000080 /* Transmit interrupt request */
495 #define AR_IMR_TXERR 0x00000100 /* Transmit error interrupt */
496 #define AR_IMR_TXNOPKT 0x00000200 /* No frame transmitted interrupt */
497 #define AR_IMR_TXEOL 0x00000400 /* Transmit descriptor empty interrupt */
498 #define AR_IMR_TXURN 0x00000800 /* Transmit FIFO underrun interrupt */
499 #define AR_IMR_MIB 0x00001000 /* MIB interrupt - see MIBC */
500 #define AR_IMR_SWI 0x00002000 /* Software interrupt */
501 #define AR_IMR_RXPHY 0x00004000 /* PHY receive error interrupt */
502 #define AR_IMR_RXKCM 0x00008000 /* Key-cache miss interrupt */
503 #define AR_IMR_SWBA 0x00010000 /* Software beacon alert interrupt */
504 #define AR_IMR_BRSSI 0x00020000 /* Beacon threshold interrupt */
505 #define AR_IMR_BMISS 0x00040000 /* Beacon missed interrupt */
507 #define AR_IMR_BNR 0x00100000 /* BNR interrupt */
508 #define AR_IMR_RXCHIRP 0x00200000 /* RXCHIRP interrupt */
510 #define AR_IMR_TIM 0x00800000 /* TIM interrupt */
511 #define AR_IMR_GPIO 0x01000000 /* GPIO Interrupt */
512 #define AR_IMR_QCBROVF 0x02000000 /* QCU CBR overflow interrupt */
513 #define AR_IMR_QCBRURN 0x04000000 /* QCU CBR underrun interrupt */
514 #define AR_IMR_QTRIG 0x08000000 /* QCU scheduling trigger interrupt */
517 #define AR_IMR_S0_QCU_TXOK 0x000003FF /* TXOK (QCU 0-9) */
519 #define AR_IMR_S0_QCU_TXDESC 0x03FF0000 /* TXDESC (QCU 0-9) */
522 #define AR_IMR_S1_QCU_TXERR 0x000003FF /* TXERR (QCU 0-9) */
524 #define AR_IMR_S1_QCU_TXEOL 0x03FF0000 /* TXEOL (QCU 0-9) */
527 #define AR_IMR_S2_QCU_TXURN 0x000003FF /* Mask for TXURN (QCU 0-9) */
529 #define AR_IMR_S2_MCABT 0x00010000 /* Master cycle abort interrupt */
530 #define AR_IMR_S2_SSERR 0x00020000 /* SERR interrupt */
547 #define AR_IMR_S3_QCU_QCBROVF 0x000003FF /* Mask for QCBROVF (QCU 0-9) */
548 #define AR_IMR_S3_QCU_QCBRURN 0x03FF0000 /* Mask for QCBRURN (QCU 0-9) */
549 #define AR_IMR_S3_QCU_QCBRURN_S 16 /* Shift for QCBRURN (QCU 0-9) */
551 #define AR_IMR_S4_QCU_QTRIG 0x000003FF /* Mask for QTRIG (QCU 0-9) */
555 #define AR_NUM_QCU 10 /* Only use QCU 0-9 for forward QCU compatibility */
575 /* bits 25-31 are reserved */
582 #define AR_Q_MISC_FSP_BEACON_SENT_GATED 4 /* Beacon-sent-gated */
585 #define AR_Q_MISC_CBR_INCR_DIS1 0x00000020 /* Disable CBR expired counter incr
587 #define AR_Q_MISC_CBR_INCR_DIS0 0x00000040 /* Disable CBR expired counter incr
590 #define AR_Q_MISC_CBR_EXP_CNTR_LIMIT 0x00000100 /* CBR expired counter limit enable */
592 #define AR_Q_MISC_RESET_CBR_EXP_CTR 0x00000400 /* Reset CBR expired counter */
599 #define AR_Q_STS_CBR_EXP_CNT 0x0000FF00 /* Mask for CBR expired counter */
615 #define AR_D_QCUMASK 0x000003FF /* Mask for QCU Mask (QCU 0-9) */
669 #define AR_D_MISC_ARB_LOCKOUT_CNTRL_INTRA_FR 1 /* Intra-frame */
673 #define AR_D_MISC_POST_FR_BKOFF_DIS 0x00200000 /* Post-frame backoff disable */
693 #define AR_RC_PCI 0x00000010 /* PCI-core reset */
708 #define AR_INTPEND_TRUE 0x00000001 /* interrupt pending */
728 #define AR_PCICFG_SL_INTEN 0x00000800 /* enable interrupt line assertion when asleep */
730 #define AR_PCICFG_SL_INPEN 0x00002000 /* Force asleep when an interrupt is pending */
756 #define AR_GPIOCR_INT_SHIFT 12 /* Interrupt select field shifter */
758 #define AR_GPIOCR_INT_MASK 0x00007000 /* Interrupt select field mask */
759 #define AR_GPIOCR_INT_ENA 0x00008000 /* Enable GPIO Interrupt */
855 #define AR_STA_ID1_ADHOC 0x00020000 /* Device is ad-hoc */
857 self-generated frames */
867 self-generated frames */
869 #define AR_STA_ID1_KSRCH_MODE 0x10000000 /* Look-up key when keyID != 0 */
880 #define AR_TIME_OUT_ACK 0x00003FFF /* ACK time-out */
882 #define AR_TIME_OUT_CTS 0x3FFF0000 /* CTS time-out */
926 #define AR_DIAG_FRAME_NV0 0x00020000 /* Accept frames of non-zero
978 #define AR_MISC_MODE_TX_ADD_TSF 0x8 /* Beacon/Probe-Rsp timestamp add (not replace) */
980 #define AR_KEYTABLE_KEY0(_n) (AR_KEYTABLE(_n) + 0) /* key bit 0-31 */
981 #define AR_KEYTABLE_KEY1(_n) (AR_KEYTABLE(_n) + 4) /* key bit 32-47 */
982 #define AR_KEYTABLE_KEY2(_n) (AR_KEYTABLE(_n) + 8) /* key bit 48-79 */
983 #define AR_KEYTABLE_KEY3(_n) (AR_KEYTABLE(_n) + 12) /* key bit 80-95 */
984 #define AR_KEYTABLE_KEY4(_n) (AR_KEYTABLE(_n) + 16) /* key bit 96-127 */
994 #define AR_KEYTABLE_MAC0(_n) (AR_KEYTABLE(_n) + 24) /* MAC address 1-32 */
995 #define AR_KEYTABLE_MAC1(_n) (AR_KEYTABLE(_n) + 28) /* MAC address 33-47 */
1000 #define AR_CCFG_MIB_INT_EN 0x00000008 /* compression performance MIB counter int enable */