Lines Matching +full:interrupt +full:- +full:counter
50 uint8_t num_backup_pools; /**< Number of BM backup pools -
73 considered for depletion (Note - this
76 will be sent after a single-pool
80 considered for depletion (Note - this
137 uint32_t fm_rie; /**< FM Error Interrupt Enable 0x1c */
138 uint32_t fmfp_fcev[4]; /**< FPM FMan-Controller Event 1-4 0x20-0x2f */
139 uint32_t res0030[4]; /**< res 0x30 - 0x3f */
140 uint32_t fmfp_cee[4]; /**< PM FMan-Controller Event 1-4 0x40-0x4f */
141 uint32_t res0050[4]; /**< res 0x50-0x5f */
150 uint32_t fmfp_drd[16]; /**< FPM Data_Ram Data 0-15 0x80 - 0xbf */
159 uint32_t fmfp_cev[4]; /**< FPM CPU Event 1-4 0xe0-0xef */
160 uint32_t res00f0[4]; /**< res 0xf0-0xff */
161 uint32_t fmfp_ps[64]; /**< FPM Port Status 0x100-0x1ff */
174 uint32_t res0230[116]; /**< res 0x230 - 0x3ff */
175 uint32_t fmfp_ts[128]; /**< 0x400: FPM Task Status 0x400 - 0x5ff */
176 uint32_t res0600[0x400 - 384];
183 uint32_t res000c[5]; /**< 0x0c - 0x1f */
184 uint32_t fmbm_ievr; /**< Interrupt Event Register 0x20 */
185 uint32_t fmbm_ier; /**< Interrupt Enable Register 0x24 */
186 uint32_t fmbm_ifr; /**< Interrupt Force Register 0x28 */
187 uint32_t res002c[5]; /**< 0x2c - 0x3f */
188 uint32_t fmbm_arb[8]; /**< BMI Arbitration 0x40 - 0x5f */
189 uint32_t res0060[12]; /**<0x60 - 0x8f */
190 uint32_t fmbm_dtc[3]; /**< Debug Trap Counter 0x90 - 0x9b */
192 uint32_t fmbm_dcv[3][4]; /**< Debug Compare val 0xa0-0xcf */
193 uint32_t fmbm_dcm[3][4]; /**< Debug Compare Mask 0xd0-0xff */
195 uint32_t fmbm_pp[63]; /**< BMI Port Parameters 0x104 - 0x1ff */
197 uint32_t fmbm_pfs[63]; /**< BMI Port FIFO Size 0x204 - 0x2ff */
199 uint32_t fmbm_spliodn[63]; /**< Port Partition ID 0x304 - 0x3ff */
205 uint32_t fmqm_eie; /**< Error Interrupt Event Register 0x08 */
206 uint32_t fmqm_eien; /**< Error Interrupt Enable Register 0x0c */
207 uint32_t fmqm_eif; /**< Error Interrupt Force Register 0x10 */
208 uint32_t fmqm_ie; /**< Interrupt Event Register 0x14 */
209 uint32_t fmqm_ien; /**< Interrupt Enable Register 0x18 */
210 uint32_t fmqm_if; /**< Interrupt Force Register 0x1c */
213 uint32_t fmqm_etfc; /**< Enqueue Total Frame Counter 0x28 */
214 uint32_t fmqm_dtfc; /**< Dequeue Total Frame Counter 0x2c */
215 uint32_t fmqm_dc0; /**< Dequeue Counter 0 0x30 */
216 uint32_t fmqm_dc1; /**< Dequeue Counter 1 0x34 */
217 uint32_t fmqm_dc2; /**< Dequeue Counter 2 0x38 */
218 uint32_t fmqm_dc3; /**< Dequeue Counter 3 0x3c */
219 uint32_t fmqm_dfdc; /**< Dequeue FQID from Default Counter 0x40 */
220 uint32_t fmqm_dfcc; /**< Dequeue FQID from Context Counter 0x44 */
221 uint32_t fmqm_dffc; /**< Dequeue FQID from FD Counter 0x48 */
222 uint32_t fmqm_dcc; /**< Dequeue Confirm Counter 0x4c */
223 uint32_t res0050[7]; /**< 0x50 - 0x6b */
225 uint32_t fmqm_dmcvc; /**< Dequeue MAC Command Valid Counter 0x70 */
226 uint32_t fmqm_difdcc; /**< Dequeue Invalid FD Command Counter 0x74 */
227 uint32_t fmqm_da1v; /**< Dequeue A1 Valid Counter 0x78 */
229 uint32_t fmqm_dtc; /**< 0x80 Debug Trap Counter 0x80 */
231 uint32_t res0088[2]; /**< 0x88 - 0x8f */
236 uint32_t fmqm_dtc1; /**< Debug Trap Counter 1 Register 0x0c */
241 } dbg_traps[3]; /**< 0x90 - 0xef */
242 uint8_t res00f0[0x400 - 0xf0]; /**< 0xf0 - 0x3ff */
256 uint32_t fmdmwcr; /**< FM DMA CAM watchdog counter value 0x28 */
266 uint32_t fmdmssrc; /**< FM DMA Semaphore SYNC Reject Counter 0x50 */
267 uint32_t fmdmdcr; /**< FM DMA Debug Counter 0x54 */
270 uint32_t fmdmplr[FMAN_LIODN_TBL / 2]; /**< DMA LIODN regs 0x60-0xdf */
271 uint32_t res00e0[0x400 - 56];
301 E_FMAN_DMA_DBG_CNT_RAW_WAR_PROT /**< RAW & WAR protection counter */
412 E_FMAN_COUNTERS_ENQ_TOTAL_FRAME = 0, /**< QMI tot enQ frames counter */
413 E_FMAN_COUNTERS_DEQ_TOTAL_FRAME, /**< QMI tot deQ frames counter */
414 E_FMAN_COUNTERS_DEQ_0, /**< QMI 0 frames from QMan counter */
415 E_FMAN_COUNTERS_DEQ_1, /**< QMI 1 frames from QMan counter */
416 E_FMAN_COUNTERS_DEQ_2, /**< QMI 2 frames from QMan counter */
417 E_FMAN_COUNTERS_DEQ_3, /**< QMI 3 frames from QMan counter */
421 E_FMAN_COUNTERS_DEQ_CONFIRM, /**< QMI dequeue confirm counter */
424 E_FMAN_COUNTERS_SEMAPHOR_SYNC_REJECT /**< DMA sync counter */