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Searched refs:WR4 (Results 1 – 25 of 80) sorted by relevance

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/freebsd/sys/arm/freescale/imx/
H A Dimx6_ccm.c73 WR4(struct ccm_softc *sc, bus_size_t off, uint32_t val) in WR4() function
95 WR4(sc, CCM_CCGR0, reg); in ccm_init_gates()
100 WR4(sc, CCM_CCGR1, reg); in ccm_init_gates()
107 WR4(sc, CCM_CCGR2, reg); in ccm_init_gates()
112 WR4(sc, CCM_CCGR3, reg); in ccm_init_gates()
117 WR4(sc, CCM_CCGR4, reg); in ccm_init_gates()
122 WR4(sc, CCM_CCGR5, reg); in ccm_init_gates()
127 WR4(sc, CCM_CCGR6, reg); in ccm_init_gates()
179 WR4(sc, CCM_CGPR, reg); in ccm_attach()
182 WR4(sc, CCM_CLPCR, reg); in ccm_attach()
[all …]
/freebsd/sys/arm/nvidia/drm2/
H A Dtegra_dc.c55 #define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, 4 * (_r), (_v)) macro
423 WR4(sc, DC_CMD_DISPLAY_WINDOW_HEADER, val); in dc_setup_window()
426 WR4(sc, DC_WIN_POSITION, WIN_POSITION(win->dst_x, win->dst_y)); in dc_setup_window()
427 WR4(sc, DC_WIN_SIZE, WIN_SIZE(win->dst_w, win->dst_h)); in dc_setup_window()
428 WR4(sc, DC_WIN_PRESCALED_SIZE, WIN_PRESCALED_SIZE(h_size, v_size)); in dc_setup_window()
431 WR4(sc, DC_WIN_DDA_INCREMENT, in dc_setup_window()
433 WR4(sc, DC_WIN_H_INITIAL_DDA, h_init_dda); in dc_setup_window()
434 WR4(sc, DC_WIN_V_INITIAL_DDA, v_init_dda); in dc_setup_window()
437 WR4(sc, DC_WINBUF_START_ADDR, win->base[0]); in dc_setup_window()
439 WR4(sc, DC_WINBUF_START_ADDR_U, win->base[1]); in dc_setup_window()
[all …]
H A Dtegra_hdmi.c58 #define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, 4 * (_r), (_v)) macro
354 WR4(sc, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER, in avi_setup_infoframe()
356 WR4(sc, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW, in avi_setup_infoframe()
358 WR4(sc, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH, in avi_setup_infoframe()
360 WR4(sc, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW, in avi_setup_infoframe()
362 WR4(sc, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH, in avi_setup_infoframe()
365 WR4(sc, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL, in avi_setup_infoframe()
385 WR4(sc, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER, in audio_setup_infoframe()
387 WR4(sc, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW, in audio_setup_infoframe()
389 WR4(sc, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH, in audio_setup_infoframe()
[all …]
/freebsd/sys/arm/xilinx/
H A Duart_dev_cdnc.c56 #define WR4(bas, reg, value) \ macro
208 WR4(bas, CDNC_UART_BAUDDIV_REG, best_bauddiv); in cdnc_uart_set_baud()
209 WR4(bas, CDNC_UART_BAUDGEN_REG, best_baudgen); in cdnc_uart_set_baud()
256 WR4(bas, CDNC_UART_MODE_REG, mode_reg_value); in cdnc_uart_set_params()
269 WR4(bas, CDNC_UART_CTRL_REG, in cdnc_uart_hw_init()
273 WR4(bas, CDNC_UART_IDIS_REG, CDNC_UART_INT_ALL); in cdnc_uart_hw_init()
274 WR4(bas, CDNC_UART_ISTAT_REG, CDNC_UART_INT_ALL); in cdnc_uart_hw_init()
277 WR4(bas, CDNC_UART_MODEM_STAT_REG, in cdnc_uart_hw_init()
282 WR4(bas, CDNC_UART_RX_WATER_REG, UART_FIFO_SIZE/2); in cdnc_uart_hw_init()
283 WR4(bas, CDNC_UART_RX_TIMEO_REG, 10); in cdnc_uart_hw_init()
[all …]
H A Dzy7_qspi.c106 #define WR4(sc, off, val) (bus_write_4((sc)->mem_res, (off), (val))) macro
251 WR4(sc, ZY7_QSPI_TXD1_REG, data); in zy7_qspi_write_fifo()
254 WR4(sc, ZY7_QSPI_TXD2_REG, data); in zy7_qspi_write_fifo()
257 WR4(sc, ZY7_QSPI_TXD3_REG, data); in zy7_qspi_write_fifo()
260 WR4(sc, ZY7_QSPI_TXD0_REG, data); in zy7_qspi_write_fifo()
321 WR4(sc, ZY7_QSPI_INTR_DIS_REG, in zy7_qspi_abort_transfer()
351 WR4(sc, ZY7_QSPI_INTR_STAT_REG, in zy7_qspi_intr()
361 WR4(sc, ZY7_QSPI_INTR_DIS_REG, in zy7_qspi_intr()
375 WR4(sc, ZY7_QSPI_INTR_STAT_REG, in zy7_qspi_intr()
390 WR4(sc, ZY7_QSPI_INTR_DIS_REG, in zy7_qspi_intr()
[all …]
H A Dzy7_spi.c93 #define WR4(sc, off, val) (bus_write_4((sc)->mem_res, (off), (val))) macro
163 WR4(sc, ZY7_SPI_TX_DATA_REG, (uint32_t)byte); in zy7_spi_write_fifo()
206 WR4(sc, ZY7_SPI_INTR_DIS_REG, in zy7_spi_abort_transfer()
236 WR4(sc, ZY7_SPI_INTR_STAT_REG, in zy7_spi_intr()
246 WR4(sc, ZY7_SPI_INTR_DIS_REG, in zy7_spi_intr()
256 WR4(sc, ZY7_SPI_INTR_STAT_REG, in zy7_spi_intr()
270 WR4(sc, ZY7_SPI_INTR_DIS_REG, in zy7_spi_intr()
272 WR4(sc, ZY7_SPI_INTR_EN_REG, in zy7_spi_intr()
284 WR4(sc, ZY7_SPI_CONFIG_REG, sc->cfg_reg_shadow); in zy7_spi_intr()
316 WR4(sc, ZY7_SPI_CONFIG_REG, sc->cfg_reg_shadow); in zy7_spi_init_hw()
[all …]
H A Dzy7_devcfg.c97 #define WR4(sc, off, val) (bus_write_4((sc)->mem_res, (off), (val))) macro
402 WR4(sc, ZY7_DEVCFG_CTRL, in zy7_devcfg_init_hw()
415 WR4(sc, ZY7_DEVCFG_MCTRL, RD4(sc, ZY7_DEVCFG_MCTRL) & in zy7_devcfg_init_hw()
431 WR4(sc, ZY7_DEVCFG_INT_STATUS, ZY7_DEVCFG_INT_ALL); in zy7_devcfg_reset_pl()
432 WR4(sc, ZY7_DEVCFG_INT_MASK, ~ZY7_DEVCFG_INT_PCFG_INIT_PE); in zy7_devcfg_reset_pl()
436 WR4(sc, ZY7_DEVCFG_CTRL, devcfg_ctl); in zy7_devcfg_reset_pl()
445 WR4(sc, ZY7_DEVCFG_INT_MASK, ~0); in zy7_devcfg_reset_pl()
456 WR4(sc, ZY7_DEVCFG_CTRL, devcfg_ctl); in zy7_devcfg_reset_pl()
468 WR4(sc, ZY7_DEVCFG_INT_STATUS, ZY7_DEVCFG_INT_ALL); in zy7_devcfg_reset_pl()
469 WR4(sc, ZY7_DEVCFG_INT_MASK, ~ZY7_DEVCFG_INT_PCFG_INIT_PE); in zy7_devcfg_reset_pl()
[all …]
H A Dzy7_slcr.c74 #define WR4(sc, off, val) (bus_write_4((sc)->mem_res, (off), (val))) macro
114 WR4(sc, ZY7_SLCR_UNLOCK, ZY7_SLCR_UNLOCK_MAGIC); in zy7_slcr_unlock()
122 WR4(sc, ZY7_SLCR_LOCK, ZY7_SLCR_LOCK_MAGIC); in zy7_slcr_lock()
136 WR4(sc, ZY7_SLCR_REBOOT_STAT, in zy7_slcr_cpu_reset()
140 WR4(sc, ZY7_SLCR_PSS_RST_CTRL, ZY7_SLCR_PSS_RST_CTRL_SOFT_RESET); in zy7_slcr_cpu_reset()
163 WR4(sc, ZY7_SLCR_FPGA_RST_CTRL, ZY7_SLCR_FPGA_RST_CTRL_RST_ALL); in zy7_slcr_preload_pl()
166 WR4(sc, ZY7_SLCR_LVL_SHFTR_EN, 0); in zy7_slcr_preload_pl()
194 WR4(sc, ZY7_SLCR_LVL_SHFTR_EN, ZY7_SLCR_LVL_SHFTR_EN_ALL); in zy7_slcr_postload_pl()
197 WR4(sc, ZY7_SLCR_FPGA_RST_CTRL, 0); in zy7_slcr_postload_pl()
239 WR4(sc, unit ? ZY7_SLCR_GEM1_CLK_CTRL : ZY7_SLCR_GEM0_CLK_CTRL, in cgem_set_ref_clk()
[all …]
/freebsd/sys/dev/ffec/
H A Dif_ffec.c232 WR4(struct ffec_softc *sc, bus_size_t off, uint32_t val) in WR4()
325 WR4(sc, FEC_IER_REG, FEC_IER_MII); in ffec_miibus_readreg()
327 WR4(sc, FEC_MMFR_REG, FEC_MMFR_OP_READ | in ffec_miibus_readreg()
349 WR4(sc, FEC_IER_REG, FEC_IER_MII); in ffec_miibus_writereg()
351 WR4(sc, FEC_MMFR_REG, FEC_MMFR_OP_WRITE | in ffec_miibus_writereg()
437 WR4(sc, FEC_RCR_REG, rcr); in ffec_miibus_statchg()
438 WR4(sc, FEC_TCR_REG, tcr); in ffec_miibus_statchg()
439 WR4(sc, FEC_ECR_REG, ecr); in ffec_miibus_statchg()
491 WR4(sc, FEC_MIBC_REG, mibc | FEC_MIBC_CLEAR); in ffec_clear_stats()
492 WR4(s in ffec_clear_stats()
231 WR4(struct ffec_softc *sc, bus_size_t off, uint32_t val) WR4() function
[all...]
/freebsd/sys/arm64/broadcom/genet/
H A Dif_genet.c81 #define WR4(sc, reg, val) bus_write_4((sc)->res[_RES_MAC], (reg), (val)) macro
460 WR4(sc, GENET_SYS_RBUF_FLUSH_CTRL, val); in gen_reset()
464 WR4(sc, GENET_SYS_RBUF_FLUSH_CTRL, val); in gen_reset()
467 WR4(sc, GENET_SYS_RBUF_FLUSH_CTRL, 0); in gen_reset()
470 WR4(sc, GENET_UMAC_CMD, 0); in gen_reset()
471 WR4(sc, GENET_UMAC_CMD, in gen_reset()
474 WR4(sc, GENET_UMAC_CMD, 0); in gen_reset()
476 WR4(sc, GENET_UMAC_MIB_CTRL, GENET_UMAC_MIB_RESET_RUNT | in gen_reset()
478 WR4(sc, GENET_UMAC_MIB_CTRL, 0); in gen_reset()
486 WR4(sc, GENET_UMAC_MAX_FRAME_LEN, 1536); in gen_enable()
[all …]
/freebsd/sys/arm64/nvidia/tegra210/
H A Dtegra210_xusbpadctl.c324 #define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, (_r), (_v)) macro
573 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2, reg); in uphy_pex_enable()
578 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL5, reg); in uphy_pex_enable()
582 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1, reg); in uphy_pex_enable()
586 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2, reg); in uphy_pex_enable()
590 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8, reg); in uphy_pex_enable()
601 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL4, reg); in uphy_pex_enable()
607 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1, reg); in uphy_pex_enable()
611 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1, reg); in uphy_pex_enable()
615 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1, reg); in uphy_pex_enable()
[all …]
H A Dtegra210_clk_pll.c607 WR4(sc, sc->base_reg, reg); in pll_enable()
620 WR4(sc, sc->base_reg, reg); in pll_disable()
760 WR4(sc, sc->base_reg, reg); in plle_enable()
766 WR4(sc, PLLE_AUX, reg); in plle_enable()
776 WR4(sc, sc->misc_reg, reg); in plle_enable()
781 WR4(sc, PLLE_SS_CNTL, reg); in plle_enable()
785 WR4(sc, sc->base_reg, reg); in plle_enable()
802 WR4(sc, PLLE_SS_CNTL, reg); in plle_enable()
805 WR4(sc, PLLE_SS_CNTL, reg); in plle_enable()
809 WR4(sc, PLLE_SS_CNTL, reg); in plle_enable()
[all …]
/freebsd/sys/arm/nvidia/
H A Dtegra_i2c.c191 #define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, (_r), (_v)) macro
244 WR4(sc, I2C_FIFO_CONTROL, reg); in tegra_i2c_flush_fifo()
272 WR4(sc, I2C_CLK_DIVISOR, in tegra_i2c_setup_clk()
283 WR4(sc, I2C_BUS_CLEAR_CONFIG, in tegra_i2c_bus_clear()
288 WR4(sc, I2C_CONFIG_LOAD, I2C_CONFIG_LOAD_MSTR_CONFIG_LOAD); in tegra_i2c_bus_clear()
298 WR4(sc, I2C_BUS_CLEAR_CONFIG,reg); in tegra_i2c_bus_clear()
332 WR4(sc, I2C_INTERRUPT_MASK_REGISTER, 0); in tegra_i2c_hw_init()
333 WR4(sc, I2C_INTERRUPT_STATUS_REGISTER, 0xFFFFFFFF); in tegra_i2c_hw_init()
334 WR4(sc, I2C_CNFG, I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN | in tegra_i2c_hw_init()
339 WR4(sc, I2C_FIFO_CONTROL, I2C_FIFO_CONTROL_TX_FIFO_TRIG(7) | in tegra_i2c_hw_init()
[all …]
H A Dtegra_usbphy.c309 #define WR4(sc, offs, val) \ macro
336 WR4(sc, CTRL_USB_HOSTPC1_DEVLC, val); in usbphy_utmi_phy_clk()
356 WR4(sc, IF_USB_SUSP_CTRL, val); in usbphy_utmi_enable()
360 WR4(sc, UTMIP_TX_CFG0, val); in usbphy_utmi_enable()
367 WR4(sc, UTMIP_HSRX_CFG0, val); in usbphy_utmi_enable()
372 WR4(sc, UTMIP_HSRX_CFG1, val); in usbphy_utmi_enable()
377 WR4(sc, UTMIP_DEBOUNCE_CFG0, val); in usbphy_utmi_enable()
381 WR4(sc, UTMIP_MISC_CFG0, val); in usbphy_utmi_enable()
387 WR4(sc, IF_USB_SUSP_CTRL, val); in usbphy_utmi_enable()
391 WR4(sc, UTMIP_BAT_CHRG_CFG0, val); in usbphy_utmi_enable()
[all …]
/freebsd/sys/arm/nvidia/tegra124/
H A Dtegra124_xusbpadctl.c170 #define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, (_r), (_v)) macro
375 WR4(sc, XUSB_PADCTL_SS_PORT_MAP, reg); in usb3_port_init()
384 WR4(sc, XUSB_PADCTL_IOPHY_USB3_PAD_CTL2(port->idx), reg); in usb3_port_init()
386 WR4(sc, XUSB_PADCTL_IOPHY_USB3_PAD_CTL4(port->idx), in usb3_port_init()
391 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg); in usb3_port_init()
396 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg); in usb3_port_init()
401 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg); in usb3_port_init()
415 WR4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL1, reg); in pcie_powerup()
422 WR4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL2, reg); in pcie_powerup()
427 WR4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL1, reg); in pcie_powerup()
[all …]
H A Dtegra124_clk_pll.c421 WR4(sc, sc->base_reg, reg); in pll_enable()
434 WR4(sc, sc->base_reg, reg); in pll_disable()
568 WR4(sc, sc->base_reg, reg); in plle_enable()
573 WR4(sc, PLLE_AUX, reg); in plle_enable()
583 WR4(sc, sc->misc_reg, reg); in plle_enable()
588 WR4(sc, PLLE_SS_CNTL, reg); in plle_enable()
594 WR4(sc, sc->base_reg, reg); in plle_enable()
607 WR4(sc, PLLE_SS_CNTL, reg); in plle_enable()
610 WR4(sc, PLLE_SS_CNTL, reg); in plle_enable()
614 WR4(sc, PLLE_SS_CNTL, reg); in plle_enable()
[all …]
/freebsd/sys/dev/eqos/
H A Dif_eqos.c98 #define WR4(sc, o, v) bus_write_4(sc->res[EQOS_RES_MEM], (o), (v)) macro
121 WR4(sc, GMAC_MAC_MDIO_ADDRESS, addr); in eqos_miibus_readreg()
148 WR4(sc, GMAC_MAC_MDIO_DATA, val); in eqos_miibus_writereg()
154 WR4(sc, GMAC_MAC_MDIO_ADDRESS, addr); in eqos_miibus_writereg()
217 WR4(sc, GMAC_MAC_CONFIGURATION, reg); in eqos_miibus_statchg()
221 WR4(sc, GMAC_MAC_1US_TIC_COUNTER, (sc->csr_clock / 1000000) - 1); in eqos_miibus_statchg()
372 WR4(sc, GMAC_DMA_CHAN0_INTR_ENABLE, in eqos_enable_intr()
382 WR4(sc, GMAC_DMA_CHAN0_INTR_ENABLE, 0); in eqos_disable_intr()
439 WR4(sc, GMAC_MAC_ADDRESS0_HIGH, val); in eqos_setup_rxfilter()
442 WR4(sc, GMAC_MAC_ADDRESS0_LOW, val); in eqos_setup_rxfilter()
[all …]
/freebsd/sys/arm64/rockchip/
H A Drk_tsadc.c100 #define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, (_r), (_v)) macro
484 WR4(sc, TSADC_INT_EN, val); in tsadc_init_tsensor()
488 WR4(sc, TSADC_COMP_SHUT(sensor->channel), val); in tsadc_init_tsensor()
491 WR4(sc, TSADC_AUTO_CON, val); in tsadc_init_tsensor()
495 WR4(sc, TSADC_COMP_INT(sensor->channel), val); in tsadc_init_tsensor()
498 WR4(sc, TSADC_INT_EN, val); in tsadc_init_tsensor()
514 WR4(sc, TSADC_AUTO_CON, val); in tsadc_init()
519 WR4(sc, TSADC_AUTO_PERIOD, 250); /* 250 ms */ in tsadc_init()
520 WR4(sc, TSADC_AUTO_PERIOD_HT, 50); /* 50 ms */ in tsadc_init()
521 WR4(sc, TSADC_HIGHT_INT_DEBOUNCE, 4); in tsadc_init()
[all …]
/freebsd/sys/dev/sdhci/
H A Dsdhci_fsl_fdt.c57 #define WR4 (sc->write) macro
325 WR4(sc, SDHCI_CLOCK_CONTROL, val32 & ~SDHCI_FSL_CLK_SDCLKEN); in fsl_sdhc_fdt_set_clock()
372 WR4(sc, SDHCI_CLOCK_CONTROL, val32); in fsl_sdhc_fdt_set_clock()
492 WR4(sc, SDHCI_FSL_PROT_CTRL, val32); in sdhci_fsl_fdt_write_1()
500 WR4(sc, off & ~3, val32); in sdhci_fsl_fdt_write_1()
529 WR4(sc, SDHCI_TRANSFER_MODE, sc->cmd_and_mode); in sdhci_fsl_fdt_write_2()
543 WR4(sc, off & ~3, val32); in sdhci_fsl_fdt_write_2()
572 WR4(sc, off, val); in sdhci_fsl_fdt_write_4()
723 WR4(sc, SDHCI_FSL_PROT_CTRL, val); in sdhci_fsl_fdt_switch_vccq()
747 WR4(sc, SDHCI_FSL_PROT_CTRL, val_old); in sdhci_fsl_fdt_switch_vccq()
[all …]
H A Dfsl_sdhci.c197 WR4(struct fsl_sdhci_softc *sc, bus_size_t off, uint32_t val) in WR4() function
398 WR4(sc, SDHC_PROT_CTRL, val32); in fsl_sdhci_write_1()
416 WR4(sc, off & ~3, val32); in fsl_sdhci_write_1()
456 WR4(sc, SDHCI_INT_ENABLE, slot->intmask | SDHCI_INT_RESPONSE); in fsl_sdhci_write_2()
457 WR4(sc, SDHCI_SIGNAL_ENABLE, slot->intmask | SDHCI_INT_RESPONSE); in fsl_sdhci_write_2()
476 WR4(sc, USDHC_MIX_CONTROL, val32); in fsl_sdhci_write_2()
487 WR4(sc, SDHCI_TRANSFER_MODE, sc->cmd_and_mode); in fsl_sdhci_write_2()
495 WR4(sc, off & ~3, val32); in fsl_sdhci_write_2()
508 WR4(sc, off, val); in fsl_sdhci_write_4()
592 WR4(sc, SDHCI_CLOCK_CONTROL, val32 & ~SDHC_CLK_SDCLKEN); in fsl_sdhc_set_clock()
[all …]
/freebsd/sys/arm/broadcom/bcm2835/
H A Dbcm2835_sdhost.c243 WR4(struct bcm_sdhost_softc *sc, bus_size_t off, uint32_t val) in WR4() function
279 WR4(sc, off & ~3, val32); in WR2()
290 WR4(sc, off & ~3, val32); in WR1()
346 WR4(sc, HC_POWER, 0); in bcm_sdhost_reset()
348 WR4(sc, HC_COMMAND, 0); in bcm_sdhost_reset()
349 WR4(sc, HC_ARGUMENT, 0); in bcm_sdhost_reset()
350 WR4(sc, HC_TIMEOUTCOUNTER, HC_TIMEOUT_DEFAULT); in bcm_sdhost_reset()
351 WR4(sc, HC_CLOCKDIVISOR, 0); in bcm_sdhost_reset()
352 WR4(sc, HC_HOSTSTATUS, HC_HSTST_RESET); in bcm_sdhost_reset()
353 WR4(sc, HC_HOSTCONFIG, 0); in bcm_sdhost_reset()
[all …]
/freebsd/sys/arm64/qoriq/
H A Dqoriq_therm.c196 WR4(struct qoriq_therm_softc *sc, bus_size_t addr, uint32_t val) in WR4() function
315 WR4(sc, TMU_TTRCR(i), ranges[i]); in qoriq_therm_fdt_calib()
326 WR4(sc, TMU_TTCFGR, calibs[i]); in qoriq_therm_fdt_calib()
327 WR4(sc, TMU_TSCFGR, calibs[i + 1]); in qoriq_therm_fdt_calib()
423 WR4(sc, TMU_TMR, 0); in qoriq_therm_attach()
427 WR4(sc, TMU_TIER, 0); in qoriq_therm_attach()
431 WR4(sc, TMUV1_TMTMIR, 0x0F); in qoriq_therm_attach()
433 WR4(sc, TMUV2_TMTMIR, 0x0F); /* disable */ in qoriq_therm_attach()
435 WR4(sc, TMUV2_TEUMR(0), 0x51009c00); in qoriq_therm_attach()
437 WR4(sc, TMUV2_TMSAR(sc->tsensors[i].site_id), 0xE); in qoriq_therm_attach()
[all …]
/freebsd/sys/arm/mv/
H A Dmv_cp110_icu.c100 #define WR4(sc, reg, val) bus_write_4((sc)->res, (reg), (val)) macro
161 WR4(sc, ICU_INT_CFG(i), 0); in mv_cp110_icu_attach()
249 WR4(sc, ICU_SETSPI_NSR_AL, addr & UINT32_MAX); in mv_cp110_icu_init()
250 WR4(sc, ICU_SETSPI_NSR_AH, (addr >> 32) & UINT32_MAX); in mv_cp110_icu_init()
252 WR4(sc, ICU_CLRSPI_NSR_AL, addr & UINT32_MAX); in mv_cp110_icu_init()
253 WR4(sc, ICU_CLRSPI_NSR_AH, (addr >> 32) & UINT32_MAX); in mv_cp110_icu_init()
256 WR4(sc, ICU_SETSPI_SEI_AL, addr & UINT32_MAX); in mv_cp110_icu_init()
257 WR4(sc, ICU_SETSPI_SEI_AH, (addr >> 32) & UINT32_MAX); in mv_cp110_icu_init()
319 WR4(sc, ICU_INT_CFG(irq_no), vector); in mv_cp110_icu_map_intr()
329 WR4(sc, ICU_INT_CFG(ICU_INT_SATA1), vector); in mv_cp110_icu_map_intr()
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/freebsd/sys/dev/hwpmc/
H A Dpmu_dmc620.c70 #define WR4(sc, r, v) bus_write_4((sc)->sc_res[0], (r), (v)) macro
71 #define MD4(sc, r, c, s) WR4((sc), (r), (RD4((sc), (r)) & ~(c)) | (s))
99 WR4(sc, DMC620_REG(cntr, reg), val); in pmu_dmc620_wr4()
155 WR4(sc, DMC620_OVERFLOW_STATUS_CLKDIV2, 0); in pmu_dmc620_acpi_attach()
156 WR4(sc, DMC620_OVERFLOW_STATUS_CLK, 0); in pmu_dmc620_acpi_attach()
224 WR4(sc, DMC620_REG(i, DMC620_COUNTER_CONTROL), in pmu_dmc620_counter_overflow_intr()
234 WR4(sc, DMC620_OVERFLOW_STATUS_CLKDIV2, 0); in pmu_dmc620_counter_overflow_intr()
242 WR4(sc, DMC620_OVERFLOW_STATUS_CLK, 0); in pmu_dmc620_counter_overflow_intr()
247 WR4(sc, DMC620_REG(i, DMC620_COUNTER_CONTROL), in pmu_dmc620_counter_overflow_intr()
/freebsd/sys/dev/cadence/
H A Dif_cgem.c221 #define WR4(sc, off, val) (bus_write_4((sc)->mem_res, (off), (val))) macro
281 WR4(sc, CGEM_SPEC_ADDR_LOW(0), (eaddr[3] << 24) | in cgem_get_mac()
283 WR4(sc, CGEM_SPEC_ADDR_HI(0), (eaddr[5] << 8) | eaddr[4]); in cgem_get_mac()
286 WR4(sc, CGEM_SPEC_ADDR_LOW(i), 0); in cgem_get_mac()
287 WR4(sc, CGEM_SPEC_ADDR_HI(i), 0); in cgem_get_mac()
359 WR4(sc, CGEM_HASH_TOP, hashes[0]); in cgem_rx_filter()
360 WR4(sc, CGEM_HASH_BOT, hashes[1]); in cgem_rx_filter()
361 WR4(sc, CGEM_NET_CFG, sc->net_cfg_shadow); in cgem_rx_filter()
399 WR4(sc, CGEM_RX_QN_BAR(n), sc->null_qs_physaddr); in cgem_null_qs()
400 WR4(sc, CGEM_TX_QN_BAR(n), sc->null_qs_physaddr + in cgem_null_qs()
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