Lines Matching refs:WR4
74 #define WR4(sc, off, val) (bus_write_4((sc)->mem_res, (off), (val))) macro
114 WR4(sc, ZY7_SLCR_UNLOCK, ZY7_SLCR_UNLOCK_MAGIC); in zy7_slcr_unlock()
122 WR4(sc, ZY7_SLCR_LOCK, ZY7_SLCR_LOCK_MAGIC); in zy7_slcr_lock()
136 WR4(sc, ZY7_SLCR_REBOOT_STAT, in zy7_slcr_cpu_reset()
140 WR4(sc, ZY7_SLCR_PSS_RST_CTRL, ZY7_SLCR_PSS_RST_CTRL_SOFT_RESET); in zy7_slcr_cpu_reset()
163 WR4(sc, ZY7_SLCR_FPGA_RST_CTRL, ZY7_SLCR_FPGA_RST_CTRL_RST_ALL); in zy7_slcr_preload_pl()
166 WR4(sc, ZY7_SLCR_LVL_SHFTR_EN, 0); in zy7_slcr_preload_pl()
194 WR4(sc, ZY7_SLCR_LVL_SHFTR_EN, ZY7_SLCR_LVL_SHFTR_EN_ALL); in zy7_slcr_postload_pl()
197 WR4(sc, ZY7_SLCR_FPGA_RST_CTRL, 0); in zy7_slcr_postload_pl()
239 WR4(sc, unit ? ZY7_SLCR_GEM1_CLK_CTRL : ZY7_SLCR_GEM0_CLK_CTRL, in cgem_set_ref_clk()
274 WR4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit), reg); in zy7_pl_fclk_set_source()
366 WR4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit), reg); in zy7_pl_fclk_set_freq()
445 WR4(sc, ZY7_SLCR_FPGA_THR_CTRL(unit), 0); in zy7_pl_fclk_enable()
446 WR4(sc, ZY7_SLCR_FPGA_THR_CNT(unit), 0); in zy7_pl_fclk_enable()
469 WR4(sc, ZY7_SLCR_FPGA_THR_CTRL(unit), 0); in zy7_pl_fclk_disable()
470 WR4(sc, ZY7_SLCR_FPGA_THR_CNT(unit), 1); in zy7_pl_fclk_disable()
523 WR4(sc, ZY7_SLCR_LVL_SHFTR_EN, ZY7_SLCR_LVL_SHFTR_EN_ALL); in zy7_pl_level_shifters_enable()
538 WR4(sc, ZY7_SLCR_LVL_SHFTR_EN, 0); in zy7_pl_level_shifters_disable()