Lines Matching refs:WR4
93 #define WR4(sc, off, val) (bus_write_4((sc)->mem_res, (off), (val))) macro
163 WR4(sc, ZY7_SPI_TX_DATA_REG, (uint32_t)byte); in zy7_spi_write_fifo()
206 WR4(sc, ZY7_SPI_INTR_DIS_REG, in zy7_spi_abort_transfer()
236 WR4(sc, ZY7_SPI_INTR_STAT_REG, in zy7_spi_intr()
246 WR4(sc, ZY7_SPI_INTR_DIS_REG, in zy7_spi_intr()
256 WR4(sc, ZY7_SPI_INTR_STAT_REG, in zy7_spi_intr()
270 WR4(sc, ZY7_SPI_INTR_DIS_REG, in zy7_spi_intr()
272 WR4(sc, ZY7_SPI_INTR_EN_REG, in zy7_spi_intr()
284 WR4(sc, ZY7_SPI_CONFIG_REG, sc->cfg_reg_shadow); in zy7_spi_intr()
316 WR4(sc, ZY7_SPI_CONFIG_REG, sc->cfg_reg_shadow); in zy7_spi_init_hw()
319 WR4(sc, ZY7_SPI_TX_THRESH_REG, 32); in zy7_spi_init_hw()
320 WR4(sc, ZY7_SPI_RX_THRESH_REG, 1); in zy7_spi_init_hw()
323 WR4(sc, ZY7_SPI_INTR_STAT_REG, ~0); in zy7_spi_init_hw()
324 WR4(sc, ZY7_SPI_INTR_DIS_REG, ~0); in zy7_spi_init_hw()
327 WR4(sc, ZY7_SPI_EN_REG, ZY7_SPI_ENABLE); in zy7_spi_init_hw()
460 WR4(sc, ZY7_SPI_EN_REG, 0); in zy7_spi_detach()
463 WR4(sc, ZY7_SPI_INTR_STAT_REG, ~0); in zy7_spi_detach()
464 WR4(sc, ZY7_SPI_INTR_DIS_REG, ~0); in zy7_spi_detach()
535 WR4(sc, ZY7_SPI_INTR_EN_REG, in zy7_spi_transfer()
548 WR4(sc, ZY7_SPI_CONFIG_REG, sc->cfg_reg_shadow); in zy7_spi_transfer()