607 	WR4(sc, sc->base_reg, reg);  in pll_enable()
620 	WR4(sc, sc->base_reg, reg);  in pll_disable()
760 	WR4(sc, sc->base_reg, reg);  in plle_enable()
766 	WR4(sc, PLLE_AUX, reg);  in plle_enable()
776 	WR4(sc, sc->misc_reg, reg);  in plle_enable()
781 	WR4(sc, PLLE_SS_CNTL, reg);  in plle_enable()
785 	WR4(sc, sc->base_reg, reg);  in plle_enable()
802 	WR4(sc, PLLE_SS_CNTL, reg);  in plle_enable()
805 	WR4(sc, PLLE_SS_CNTL, reg);  in plle_enable()
809 	WR4(sc, PLLE_SS_CNTL, reg);  in plle_enable()
815 	WR4(sc, sc->misc_reg, reg);  in plle_enable()
822 	WR4(sc, PLLE_AUX, reg);  in plle_enable()
826 	WR4(sc, PLLE_AUX, reg);  in plle_enable()
835 	WR4(sc, XUSBIO_PLL_CFG0, reg);  in plle_enable()
839 	WR4(sc, XUSBIO_PLL_CFG0, reg);  in plle_enable()
853 	WR4(sc, SATA_PLL_CFG0, reg);  in plle_enable()
856 	WR4(sc, SATA_PLL_CFG0, reg);  in plle_enable()
861 	WR4(sc, PCIE_PLL_CFG, reg);  in plle_enable()
894 	WR4(sc, sc->base_reg, reg);  in tegra210_pll_get_gate()
935 	WR4(sc, sc->base_reg, reg);  in pll_set_std()
940 	WR4(sc, sc->base_reg, reg);  in pll_set_std()
945 	WR4(sc, sc->misc_reg, reg);  in pll_set_std()
952 		WR4(sc, sc->base_reg, reg);  in pll_set_std()
1156 		WR4(sc, sc->base_reg, reg);  in pllx_set_freq()
1164 	WR4(sc, PLLX_MISC_2, reg);  in pllx_set_freq()
1170 	WR4(sc, PLLX_MISC_2, reg);  in pllx_set_freq()
1175 	WR4(sc, PLLX_MISC_2, reg);  in pllx_set_freq()
1193 	WR4(sc, sc->base_reg, reg);  in pllx_set_freq()
1198 	WR4(sc, PLLX_MISC_2, reg);  in pllx_set_freq()
1211 		WR4(sc, sc->base_reg, reg);  in pllx_set_freq()
1228 	WR4(sc, PLLX_MISC, reg);  in pllx_init()
1234 	WR4(sc, PLLX_MISC_2, reg);  in pllx_init()
1238 	WR4(sc, PLLX_MISC_4, reg);  in pllx_init()
1239 	WR4(sc, PLLX_MISC_5, reg);  in pllx_init()
1320 		WR4(sc, sc->misc_reg, reg);  in tegra210_pll_init()
1325 		WR4(sc, sc->misc_reg, reg);  in tegra210_pll_init()