98 #define	WR4(sc, o, v)		bus_write_4(sc->res[EQOS_RES_MEM], (o), (v))  macro
122 	WR4(sc, GMAC_MAC_MDIO_ADDRESS, addr);  in eqos_miibus_readreg()
149 	WR4(sc, GMAC_MAC_MDIO_DATA, val);  in eqos_miibus_writereg()
156 	WR4(sc, GMAC_MAC_MDIO_ADDRESS, addr);  in eqos_miibus_writereg()
219 	WR4(sc, GMAC_MAC_CONFIGURATION, reg);  in eqos_miibus_statchg()
223 	WR4(sc, GMAC_MAC_1US_TIC_COUNTER, (sc->csr_clock / 1000000) - 1);  in eqos_miibus_statchg()
374 	WR4(sc, GMAC_DMA_CHAN0_INTR_ENABLE,  in eqos_enable_intr()
386 	WR4(sc, GMAC_DMA_CHAN0_INTR_ENABLE, 0);  in eqos_disable_intr()
443 	WR4(sc, GMAC_MAC_ADDRESS0_HIGH, val);  in eqos_setup_rxfilter()
445 	WR4(sc, GMAC_MAC_ADDRESS0_LOW, val);  in eqos_setup_rxfilter()
448 	WR4(sc, GMAC_MAC_HASH_TABLE_REG0, hash[0]);  in eqos_setup_rxfilter()
449 	WR4(sc, GMAC_MAC_HASH_TABLE_REG1, hash[1]);  in eqos_setup_rxfilter()
452 	WR4(sc, GMAC_MAC_PACKET_FILTER, pfil);  in eqos_setup_rxfilter()
461 	WR4(sc, GMAC_DMA_MODE, GMAC_DMA_MODE_SWR);  in eqos_reset()
475 	WR4(sc, GMAC_DMA_CHAN0_TX_BASE_ADDR_HI,  in eqos_init_rings()
477 	WR4(sc, GMAC_DMA_CHAN0_TX_BASE_ADDR,  in eqos_init_rings()
479 	WR4(sc, GMAC_DMA_CHAN0_TX_RING_LEN, TX_DESC_COUNT - 1);  in eqos_init_rings()
481 	WR4(sc, GMAC_DMA_CHAN0_RX_BASE_ADDR_HI,  in eqos_init_rings()
483 	WR4(sc, GMAC_DMA_CHAN0_RX_BASE_ADDR,  in eqos_init_rings()
485 	WR4(sc, GMAC_DMA_CHAN0_RX_RING_LEN, RX_DESC_COUNT - 1);  in eqos_init_rings()
487 	WR4(sc, GMAC_DMA_CHAN0_RX_END_ADDR,  in eqos_init_rings()
508 	WR4(sc, GMAC_MAC_1US_TIC_COUNTER, (sc->csr_clock / 1000000) - 1);  in eqos_init()
516 	WR4(sc, GMAC_DMA_CHAN0_CONTROL, val);  in eqos_init()
522 	WR4(sc, GMAC_DMA_CHAN0_TX_CONTROL, val);  in eqos_init()
529 	WR4(sc, GMAC_DMA_CHAN0_RX_CONTROL, val);  in eqos_init()
532 	WR4(sc, GMAC_MMC_CONTROL,  in eqos_init()
546 	WR4(sc, GMAC_MTL_TXQ0_OPERATION_MODE,  in eqos_init()
549 	WR4(sc, GMAC_MTL_RXQ0_OPERATION_MODE,  in eqos_init()
558 	WR4(sc, GMAC_MAC_Q0_TX_FLOW_CTRL, val);  in eqos_init()
561 	WR4(sc, GMAC_MAC_RX_FLOW_CTRL, val);  in eqos_init()
564 	WR4(sc, GMAC_RXQ_CTRL0, (GMAC_RXQ_CTRL0_EN_MASK << 16) |  in eqos_init()
575 	WR4(sc, GMAC_MAC_CONFIGURATION, val);  in eqos_init()
625 		WR4(sc, GMAC_DMA_CHAN0_TX_END_ADDR,  in eqos_start_locked()
657 	WR4(sc, GMAC_MAC_CONFIGURATION, val);  in eqos_stop()
662 	WR4(sc, GMAC_DMA_CHAN0_RX_CONTROL, val);  in eqos_stop()
667 	WR4(sc, GMAC_DMA_CHAN0_TX_CONTROL, val);  in eqos_stop()
672 	WR4(sc, GMAC_MTL_TXQ0_OPERATION_MODE, val);  in eqos_stop()
685 	WR4(sc, GMAC_MAC_CONFIGURATION, val);  in eqos_stop()
737 		WR4(sc, GMAC_DMA_CHAN0_RX_END_ADDR,  in eqos_rxintr()
807 			WR4(sc, GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS, mtl_clear);  in eqos_intr_mtl()
859 		WR4(sc, GMAC_DMA_CHAN0_STATUS, dma_status);  in eqos_intr()
993 	WR4(sc, GMAC_DMA_SYSBUS_MODE, val);  in eqos_axi_configure()