Lines Matching refs:WR4
58 #define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, 4 * (_r), (_v)) macro
354 WR4(sc, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER, in avi_setup_infoframe()
356 WR4(sc, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW, in avi_setup_infoframe()
358 WR4(sc, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH, in avi_setup_infoframe()
360 WR4(sc, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW, in avi_setup_infoframe()
362 WR4(sc, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH, in avi_setup_infoframe()
365 WR4(sc, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL, in avi_setup_infoframe()
385 WR4(sc, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER, in audio_setup_infoframe()
387 WR4(sc, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW, in audio_setup_infoframe()
389 WR4(sc, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH, in audio_setup_infoframe()
392 WR4(sc, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL, in audio_setup_infoframe()
413 WR4(sc, HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR, val); in init_hda_eld()
415 WR4(sc,HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE, in init_hda_eld()
543 WR4(sc, HDMI_NV_PDISP_SOR_AUDIO_CNTRL0, in audio_setup()
549 WR4(sc, HDMI_NV_PDISP_SOR_AUDIO_SPARE0, val); in audio_setup()
551 WR4(sc, HDMI_NV_PDISP_HDMI_ACR_CTRL, 0); in audio_setup()
553 WR4(sc, HDMI_NV_PDISP_AUDIO_N, in audio_setup()
558 WR4(sc, HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH, in audio_setup()
561 WR4(sc, HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW, in audio_setup()
564 WR4(sc, HDMI_NV_PDISP_HDMI_SPARE, in audio_setup()
569 WR4(sc, HDMI_NV_PDISP_AUDIO_N, val); in audio_setup()
571 WR4(sc, aval_reg, audio_aval); in audio_setup()
583 WR4(sc, HDMI_NV_PDISP_HDMI_GENERIC_CTRL, val); in audio_disable()
588 WR4(sc, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL, val); in audio_disable()
601 WR4(sc, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL, val); in audio_enable()
606 WR4(sc, HDMI_NV_PDISP_HDMI_GENERIC_CTRL, val); in audio_enable()
650 WR4(sc, HDMI_NV_PDISP_SOR_PLL0, tmds->pll0); in tmds_init()
651 WR4(sc, HDMI_NV_PDISP_SOR_PLL1, tmds->pll1); in tmds_init()
652 WR4(sc, HDMI_NV_PDISP_PE_CURRENT, tmds->pe_c); in tmds_init()
653 WR4(sc, HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT, tmds->drive_c); in tmds_init()
654 WR4(sc, HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT, tmds->peak_c); in tmds_init()
655 WR4(sc, HDMI_NV_PDISP_SOR_PAD_CTLS0, tmds->pad_ctls); in tmds_init()
669 WR4(sc, HDMI_NV_PDISP_SOR_PLL0, val); in hdmi_sor_start()
674 WR4(sc, HDMI_NV_PDISP_SOR_PLL0, val); in hdmi_sor_start()
676 WR4(sc, HDMI_NV_PDISP_SOR_PWR, SOR_PWR_SETTING_NEW); in hdmi_sor_start()
677 WR4(sc, HDMI_NV_PDISP_SOR_PWR, 0); in hdmi_sor_start()
699 WR4(sc, HDMI_NV_PDISP_SOR_STATE2, val); in hdmi_sor_start()
701 WR4(sc, HDMI_NV_PDISP_SOR_STATE1, SOR_STATE1_ASY_ORMODE_NORMAL | in hdmi_sor_start()
704 WR4(sc, HDMI_NV_PDISP_SOR_STATE0, 0); in hdmi_sor_start()
705 WR4(sc, HDMI_NV_PDISP_SOR_STATE0, SOR_STATE0_UPDATE); in hdmi_sor_start()
709 WR4(sc, HDMI_NV_PDISP_SOR_STATE1, val); in hdmi_sor_start()
711 WR4(sc, HDMI_NV_PDISP_SOR_STATE0, 0); in hdmi_sor_start()
737 WR4(sc, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL, val); in hdmi_disable()
740 WR4(sc, HDMI_NV_PDISP_INT_ENABLE, 0); in hdmi_disable()
741 WR4(sc, HDMI_NV_PDISP_INT_MASK, 0); in hdmi_disable()
791 WR4(sc, HDMI_NV_PDISP_SOR_PLL0, val); in hdmi_enable()
796 WR4(sc, HDMI_NV_PDISP_SOR_PLL0, val); in hdmi_enable()
800 WR4(sc, HDMI_NV_PDISP_HDMI_VSYNC_WINDOW, in hdmi_enable()
810 WR4(sc, HDMI_NV_PDISP_INPUT_CONTROL, val); in hdmi_enable()
815 WR4(sc, HDMI_NV_PDISP_SOR_REFCLK, val); in hdmi_enable()
830 WR4(sc, HDMI_NV_PDISP_HDMI_CTRL, val); in hdmi_enable()
841 WR4(sc, HDMI_NV_PDISP_SOR_SEQ_CTL, in hdmi_enable()
849 WR4(sc, HDMI_NV_PDISP_SOR_SEQ_INST(0), val); in hdmi_enable()
850 WR4(sc, HDMI_NV_PDISP_SOR_SEQ_INST(8), val); in hdmi_enable()
859 WR4(sc, HDMI_NV_PDISP_SOR_CSTM, val); in hdmi_enable()
871 WR4(sc, HDMI_NV_PDISP_INT_MASK, INT_CODEC_SCRATCH0); in hdmi_enable()
872 WR4(sc, HDMI_NV_PDISP_INT_ENABLE, INT_CODEC_SCRATCH0); in hdmi_enable()
1165 WR4(sc, HDMI_NV_PDISP_INT_STATUS, status); in hdmi_intr()