324 #define	WR4(_sc, _r, _v)	bus_write_4((_sc)->mem_res, (_r), (_v))  macro
573 	WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2, reg);  in uphy_pex_enable()
578 	WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL5, reg);  in uphy_pex_enable()
582 	WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1, reg);  in uphy_pex_enable()
586 	WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2, reg);  in uphy_pex_enable()
590 	WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8, reg);  in uphy_pex_enable()
601 	WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL4, reg);  in uphy_pex_enable()
607 	WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1, reg);  in uphy_pex_enable()
611 	WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1, reg);  in uphy_pex_enable()
615 	WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1, reg);  in uphy_pex_enable()
623 	WR4(sc,  XUSB_PADCTL_UPHY_PLL_P0_CTL4, reg);  in uphy_pex_enable()
628 	WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2, reg);  in uphy_pex_enable()
644 	WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2, reg);  in uphy_pex_enable()
661 	WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1, reg);  in uphy_pex_enable()
679 	WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8, reg);  in uphy_pex_enable()
696 	WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8, reg);  in uphy_pex_enable()
714 	WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8, reg);  in uphy_pex_enable()
721 	WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1, reg);  in uphy_pex_enable()
725 	WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2, reg);  in uphy_pex_enable()
729 	WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8, reg);  in uphy_pex_enable()
796 	WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2, reg);  in uphy_sata_enable()
801 	WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL5, reg);  in uphy_sata_enable()
805 	WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1, reg);  in uphy_sata_enable()
809 	WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL2, reg);  in uphy_sata_enable()
813 	WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8, reg);  in uphy_sata_enable()
842 	WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1, reg);  in uphy_sata_enable()
846 	WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1, reg);  in uphy_sata_enable()
850 	WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1, reg);  in uphy_sata_enable()
858 	WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL4, reg);  in uphy_sata_enable()
863 	WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL2, reg);  in uphy_sata_enable()
879 	WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL2, reg);  in uphy_sata_enable()
896 	WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1, reg);  in uphy_sata_enable()
914 	WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8, reg);  in uphy_sata_enable()
930 	WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8, reg);  in uphy_sata_enable()
946 	WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8, reg);  in uphy_sata_enable()
953 	WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1, reg);  in uphy_sata_enable()
957 	WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL2, reg);  in uphy_sata_enable()
961 	WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8, reg);  in uphy_sata_enable()
1014 	WR4(sc, XUSB_PADCTL_SS_PORT_MAP, reg);  in usb3_port_init()
1028 	WR4(sc, XUSB_PADCTL_UPHY_USB3_PAD_ECTL1(port->idx), reg);  in usb3_port_init()
1033 	WR4(sc, XUSB_PADCTL_UPHY_USB3_PAD_ECTL2(port->idx), reg);  in usb3_port_init()
1035 	WR4(sc, XUSB_PADCTL_UPHY_USB3_PAD_ECTL3(port->idx), 0xc0077f1f);  in usb3_port_init()
1040 	WR4(sc, XUSB_PADCTL_UPHY_USB3_PAD_ECTL4(port->idx), reg);  in usb3_port_init()
1042 	WR4(sc, XUSB_PADCTL_UPHY_USB3_PAD_ECTL6(port->idx), 0xfcf01368);  in usb3_port_init()
1053 	WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg);  in usb3_port_init()
1058 	WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg);  in usb3_port_init()
1063 	WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg);  in usb3_port_init()
1081 	WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg);  in pcie_enable()
1093 	WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg);  in pcie_disable()
1113 	WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg);  in sata_enable()
1125 	WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg);  in sata_disable()
1156 	WR4(sc, XUSB_PADCTL_HSIC_STRB_TRIM_CONTROL, sc->strobe_trim);  in hsic_enable()
1161 	WR4(sc, XUSB_PADCTL_HSIC_PAD_CTL1(lane->idx), reg);  in hsic_enable()
1170 	WR4(sc, XUSB_PADCTL_HSIC_PAD_CTL2(lane->idx), reg);  in hsic_enable()
1188 	WR4(sc, XUSB_PADCTL_HSIC_PAD_CTL0(lane->idx), reg);  in hsic_enable()
1204 	WR4(sc, XUSB_PADCTL_HSIC_PAD_TRK_CTL, reg);  in hsic_enable()
1210 	WR4(sc, XUSB_PADCTL_HSIC_PAD_TRK_CTL, reg);  in hsic_enable()
1240 	WR4(sc, XUSB_PADCTL_HSIC_PAD_CTL1(lane->idx), reg);  in hsic_disable()
1273 	WR4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0, reg);  in usb2_enable()
1278 	WR4(sc, XUSB_PADCTL_USB2_PORT_CAP, reg);  in usb2_enable()
1289 	WR4(sc, XUSB_PADCTL_USB2_OTG_PAD_CTL0(lane->idx), reg);  in usb2_enable()
1299 	WR4(sc, XUSB_PADCTL_USB2_OTG_PAD_CTL1(lane->idx), reg);  in usb2_enable()
1304 	WR4(sc, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1(lane->idx), reg);  in usb2_enable()
1327 	WR4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL1, reg);  in usb2_enable()
1331 	WR4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0, reg);  in usb2_enable()
1352 	WR4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0, reg);  in usb2_disable()
1381 	WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg);  in pad_common_enable()
1386 	WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg);  in pad_common_enable()
1391 	WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg);  in pad_common_enable()
1404 	WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg);  in pad_common_disable()
1409 	WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg);  in pad_common_disable()
1414 	WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg);  in pad_common_disable()
1589 	WR4(sc, lane->reg, reg);  in config_lane()