Lines Matching refs:WR4
55 #define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, 4 * (_r), (_v)) macro
423 WR4(sc, DC_CMD_DISPLAY_WINDOW_HEADER, val); in dc_setup_window()
426 WR4(sc, DC_WIN_POSITION, WIN_POSITION(win->dst_x, win->dst_y)); in dc_setup_window()
427 WR4(sc, DC_WIN_SIZE, WIN_SIZE(win->dst_w, win->dst_h)); in dc_setup_window()
428 WR4(sc, DC_WIN_PRESCALED_SIZE, WIN_PRESCALED_SIZE(h_size, v_size)); in dc_setup_window()
431 WR4(sc, DC_WIN_DDA_INCREMENT, in dc_setup_window()
433 WR4(sc, DC_WIN_H_INITIAL_DDA, h_init_dda); in dc_setup_window()
434 WR4(sc, DC_WIN_V_INITIAL_DDA, v_init_dda); in dc_setup_window()
437 WR4(sc, DC_WINBUF_START_ADDR, win->base[0]); in dc_setup_window()
439 WR4(sc, DC_WINBUF_START_ADDR_U, win->base[1]); in dc_setup_window()
440 WR4(sc, DC_WINBUF_START_ADDR_V, win->base[2]); in dc_setup_window()
441 WR4(sc, DC_WIN_LINE_STRIDE, in dc_setup_window()
444 WR4(sc, DC_WIN_LINE_STRIDE, win->stride[0]); in dc_setup_window()
448 WR4(sc, DC_WINBUF_ADDR_H_OFFSET, h_offset); in dc_setup_window()
449 WR4(sc, DC_WINBUF_ADDR_V_OFFSET, v_offset); in dc_setup_window()
452 WR4(sc, DC_WIN_COLOR_DEPTH, win->color_mode); in dc_setup_window()
453 WR4(sc, DC_WIN_BYTE_SWAP, win->swap); in dc_setup_window()
459 WR4(sc, DC_WINBUF_SURFACE_KIND, val); in dc_setup_window()
463 WR4(sc, DC_WINC_CSC_YOF, 0x00f0); in dc_setup_window()
464 WR4(sc, DC_WINC_CSC_KYRGB, 0x012a); in dc_setup_window()
465 WR4(sc, DC_WINC_CSC_KUR, 0x0000); in dc_setup_window()
466 WR4(sc, DC_WINC_CSC_KVR, 0x0198); in dc_setup_window()
467 WR4(sc, DC_WINC_CSC_KUG, 0x039b); in dc_setup_window()
468 WR4(sc, DC_WINC_CSC_KVG, 0x032f); in dc_setup_window()
469 WR4(sc, DC_WINC_CSC_KUB, 0x0204); in dc_setup_window()
470 WR4(sc, DC_WINC_CSC_KVB, 0x0000); in dc_setup_window()
484 WR4(sc, DC_WINC_WIN_OPTIONS, val); in dc_setup_window()
488 WR4(sc, DC_WINBUF_UFLOW_CTRL, UFLOW_CTR_ENABLE); in dc_setup_window()
489 WR4(sc, DC_WINBUF_UFLOW_DBG_PIXEL, 0xFFFF0000); in dc_setup_window()
537 WR4(sc, DC_CMD_STATE_CONTROL, WIN_A_UPDATE << plane->index); in dc_plane_update()
538 WR4(sc, DC_CMD_STATE_CONTROL, WIN_A_ACT_REQ << plane->index); in dc_plane_update()
561 WR4(sc, DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT << idx); in dc_plane_disable()
565 WR4(sc, DC_WINC_WIN_OPTIONS, val); in dc_plane_disable()
569 WR4(sc, DC_CMD_STATE_CONTROL, WIN_A_UPDATE << idx); in dc_plane_disable()
570 WR4(sc, DC_CMD_STATE_CONTROL, WIN_A_ACT_REQ << idx); in dc_plane_disable()
662 WR4(sc, DC_DISP_DISP_TIMING_OPTIONS, 0); in dc_crtc_mode_set()
664 WR4(sc, DC_DISP_REF_TO_SYNC, in dc_crtc_mode_set()
668 WR4(sc, DC_DISP_SYNC_WIDTH, in dc_crtc_mode_set()
672 WR4(sc, DC_DISP_BACK_PORCH, in dc_crtc_mode_set()
676 WR4(sc, DC_DISP_FRONT_PORCH, in dc_crtc_mode_set()
680 WR4(sc, DC_DISP_DISP_ACTIVE, in dc_crtc_mode_set()
683 WR4(sc, DC_DISP_DISP_INTERFACE_CONTROL, DISP_DATA_FORMAT(DF1P1C)); in dc_crtc_mode_set()
685 WR4(sc,DC_DISP_DISP_CLOCK_CONTROL, in dc_crtc_mode_set()
727 WR4(sc, DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE); in dc_crtc_mode_set_base()
728 WR4(sc, DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ); in dc_crtc_mode_set_base()
743 WR4(sc, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL, SYNCPT_CNTRL_NO_STALL); in dc_crtc_prepare()
745 WR4(sc, DC_CMD_CONT_SYNCPT_VSYNC, SYNCPT_VSYNC_ENABLE | in dc_crtc_prepare()
748 WR4(sc, DC_CMD_DISPLAY_POWER_CONTROL, in dc_crtc_prepare()
754 WR4(sc, DC_CMD_DISPLAY_COMMAND, val); in dc_crtc_prepare()
756 WR4(sc, DC_CMD_INT_MASK, in dc_crtc_prepare()
760 WR4(sc, DC_CMD_INT_ENABLE, in dc_crtc_prepare()
775 WR4(sc, DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE); in dc_crtc_commit()
779 WR4(sc, DC_CMD_INT_MASK, val); in dc_crtc_commit()
783 WR4(sc, DC_CMD_INT_ENABLE, val); in dc_crtc_commit()
785 WR4(sc, DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ); in dc_crtc_commit()
848 WR4(sc, DC_CMD_INT_MASK, val); in tegra_dc_enable_vblank()
865 WR4(sc, DC_CMD_INT_MASK, val); in tegra_dc_disable_vblank()
892 WR4(sc, DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT); in dc_finish_page_flip()
893 WR4(sc, DC_CMD_STATE_ACCESS, READ_MUX); in dc_finish_page_flip()
895 WR4(sc, DC_CMD_STATE_ACCESS, 0); in dc_finish_page_flip()
962 WR4(sc, DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE); in dc_page_flip()
1030 WR4(sc, DC_DISP_CURSOR_START_ADDR, val); in dc_cursor_set()
1039 WR4(sc, DC_DISP_BLEND_CURSOR_CONTROL, val); in dc_cursor_set()
1043 WR4(sc, DC_DISP_DISP_WIN_OPTIONS, val); in dc_cursor_set()
1047 WR4(sc, DC_DISP_DISP_WIN_OPTIONS, val); in dc_cursor_set()
1051 WR4(sc, DC_DISP_CURSOR_UNDERFLOW_CTRL, CURSOR_UFLOW_CYA); in dc_cursor_set()
1053 WR4(sc, DC_CMD_STATE_CONTROL, GENERAL_UPDATE | CURSOR_UPDATE ); in dc_cursor_set()
1054 WR4(sc, DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | CURSOR_ACT_REQ); in dc_cursor_set()
1066 WR4(sc, DC_DISP_CURSOR_POSITION, CURSOR_POSITION(x, y)); in dc_cursor_move()
1068 WR4(sc, DC_CMD_STATE_CONTROL, CURSOR_UPDATE); in dc_cursor_move()
1069 WR4(sc, DC_CMD_STATE_CONTROL, CURSOR_ACT_REQ); in dc_cursor_move()
1126 WR4(sc, DC_CMD_DISPLAY_COMMAND, DISPLAY_CTRL_MODE(val)); in dc_display_enable()
1129 WR4(sc, DC_CMD_STATE_CONTROL, GENERAL_UPDATE); in dc_display_enable()
1130 WR4(sc, DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ); in dc_display_enable()
1146 WR4(sc, DC_DISP_DISP_WIN_OPTIONS, val); in dc_hdmi_enable()
1158 WR4(sc, DC_DISP_DISP_TIMING_OPTIONS, VSYNC_H_POSITION(1)); in dc_setup_timing()
1159 WR4(sc, DC_DISP_DISP_COLOR_CONTROL, in dc_setup_timing()
1162 WR4(sc, DC_DISP_DISP_SIGNAL_OPTIONS0, H_PULSE2_ENABLE); in dc_setup_timing()
1163 WR4(sc, DC_DISP_H_PULSE2_CONTROL, in dc_setup_timing()
1166 WR4(sc, DC_DISP_H_PULSE2_POSITION_A, in dc_setup_timing()
1180 WR4(sc, DC_CMD_INT_STATUS, status); in dc_intr()
1209 WR4(sc, DC_CMD_INT_TYPE, in dc_init_client()
1213 WR4(sc, DC_CMD_INT_POLARITY, in dc_init_client()
1217 WR4(sc, DC_CMD_INT_ENABLE, 0); in dc_init_client()
1218 WR4(sc, DC_CMD_INT_MASK, 0); in dc_init_client()