170 #define	WR4(_sc, _r, _v)	bus_write_4((_sc)->mem_res, (_r), (_v))  macro
375 	WR4(sc, XUSB_PADCTL_SS_PORT_MAP, reg);  in usb3_port_init()
384 	WR4(sc, XUSB_PADCTL_IOPHY_USB3_PAD_CTL2(port->idx), reg);  in usb3_port_init()
386 	WR4(sc, XUSB_PADCTL_IOPHY_USB3_PAD_CTL4(port->idx),  in usb3_port_init()
391 	WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg);  in usb3_port_init()
396 	WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg);  in usb3_port_init()
401 	WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg);  in usb3_port_init()
415 	WR4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL1, reg);  in pcie_powerup()
422 	WR4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL2, reg);  in pcie_powerup()
427 	WR4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL1, reg);  in pcie_powerup()
442 	WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg);  in pcie_powerup()
454 	WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg);  in pcie_powerdown()
458 	WR4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL1, reg);  in pcie_powerdown()
474 	WR4(sc, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1, reg);  in sata_powerup()
479 	WR4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1, reg);  in sata_powerup()
483 	WR4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1, reg);  in sata_powerup()
487 	WR4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1, reg);  in sata_powerup()
501 	WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg);  in sata_powerup()
505 	WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg);  in sata_powerup()
517 	WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg);  in sata_powerdown()
521 	WR4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1, reg);  in sata_powerdown()
526 	WR4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1, reg);  in sata_powerdown()
532 	WR4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1, reg);  in sata_powerdown()
538 	WR4(sc, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1, reg);  in sata_powerdown()
561 	WR4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0, reg);  in usb2_powerup()
566 	WR4(sc, XUSB_PADCTL_USB2_PORT_CAP, reg);  in usb2_powerup()
584 	WR4(sc, XUSB_PADCTL_USB2_OTG_PAD_CTL0(lane->idx), reg);  in usb2_powerup()
595 	WR4(sc, XUSB_PADCTL_USB2_OTG_PAD_CTL1(lane->idx), reg);  in usb2_powerup()
607 	WR4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0, reg);  in usb2_powerup()
626 	WR4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0, reg);  in usb2_powerdown()
646 	WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg);  in phy_powerup()
651 	WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg);  in phy_powerup()
656 	WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg);  in phy_powerup()
669 	WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg);  in phy_powerdown()
674 	WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg);  in phy_powerdown()
679 	WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg);  in phy_powerdown()
852 	WR4(sc, lane->reg, reg);  in config_lane()