221 #define WR4(sc, off, val)	(bus_write_4((sc)->mem_res, (off), (val)))  macro
281 	WR4(sc, CGEM_SPEC_ADDR_LOW(0), (eaddr[3] << 24) |  in cgem_get_mac()
283 	WR4(sc, CGEM_SPEC_ADDR_HI(0), (eaddr[5] << 8) | eaddr[4]);  in cgem_get_mac()
286 		WR4(sc, CGEM_SPEC_ADDR_LOW(i), 0);  in cgem_get_mac()
287 		WR4(sc, CGEM_SPEC_ADDR_HI(i), 0);  in cgem_get_mac()
359 	WR4(sc, CGEM_HASH_TOP, hashes[0]);  in cgem_rx_filter()
360 	WR4(sc, CGEM_HASH_BOT, hashes[1]);  in cgem_rx_filter()
361 	WR4(sc, CGEM_NET_CFG, sc->net_cfg_shadow);  in cgem_rx_filter()
399 		WR4(sc, CGEM_RX_QN_BAR(n), sc->null_qs_physaddr);  in cgem_null_qs()
400 		WR4(sc, CGEM_TX_QN_BAR(n), sc->null_qs_physaddr +  in cgem_null_qs()
856 		WR4(sc, CGEM_NET_CTRL, sc->net_ctl_shadow |  in cgem_start_locked()
963 		WR4(sc, CGEM_NET_CTRL, sc->net_ctl_shadow &  in cgem_tick()
966 		WR4(sc, CGEM_NET_CTRL, sc->net_ctl_shadow);  in cgem_tick()
991 	WR4(sc, CGEM_INTR_STAT, istatus);  in cgem_intr()
1005 		WR4(sc, CGEM_RX_STAT, CGEM_RX_STAT_HRESP_NOT_OK);  in cgem_intr()
1011 		WR4(sc, CGEM_RX_STAT, CGEM_RX_STAT_OVERRUN);  in cgem_intr()
1017 		WR4(sc, CGEM_NET_CTRL, sc->net_ctl_shadow |  in cgem_intr()
1050 	WR4(sc, CGEM_NET_CTRL, 0);  in cgem_reset()
1051 	WR4(sc, CGEM_NET_CFG, sc->net_cfg_shadow);  in cgem_reset()
1052 	WR4(sc, CGEM_NET_CTRL, CGEM_NET_CTRL_CLR_STAT_REGS);  in cgem_reset()
1053 	WR4(sc, CGEM_TX_STAT, CGEM_TX_STAT_ALL);  in cgem_reset()
1054 	WR4(sc, CGEM_RX_STAT, CGEM_RX_STAT_ALL);  in cgem_reset()
1055 	WR4(sc, CGEM_INTR_DIS, CGEM_INTR_ALL);  in cgem_reset()
1056 	WR4(sc, CGEM_HASH_BOT, 0);  in cgem_reset()
1057 	WR4(sc, CGEM_HASH_TOP, 0);  in cgem_reset()
1058 	WR4(sc, CGEM_TX_QBAR, 0);	/* manual says do this. */  in cgem_reset()
1059 	WR4(sc, CGEM_RX_QBAR, 0);  in cgem_reset()
1063 	WR4(sc, CGEM_NET_CFG, sc->net_cfg_shadow);  in cgem_reset()
1066 	WR4(sc, CGEM_NET_CTRL, sc->net_ctl_shadow);  in cgem_reset()
1097 	WR4(sc, CGEM_NET_CFG, sc->net_cfg_shadow);  in cgem_config()
1113 	WR4(sc, CGEM_DMA_CFG, dma_cfg);  in cgem_config()
1116 	WR4(sc, CGEM_RX_QBAR, (uint32_t)sc->rxring_physaddr);  in cgem_config()
1117 	WR4(sc, CGEM_TX_QBAR, (uint32_t)sc->txring_physaddr);  in cgem_config()
1119 	WR4(sc, CGEM_RX_QBAR_HI, (uint32_t)(sc->rxring_physaddr >> 32));  in cgem_config()
1120 	WR4(sc, CGEM_TX_QBAR_HI, (uint32_t)(sc->txring_physaddr >> 32));  in cgem_config()
1125 	WR4(sc, CGEM_NET_CTRL, sc->net_ctl_shadow);  in cgem_config()
1128 	WR4(sc, CGEM_SPEC_ADDR_LOW(0), (eaddr[3] << 24) |  in cgem_config()
1130 	WR4(sc, CGEM_SPEC_ADDR_HI(0), (eaddr[5] << 8) | eaddr[4]);  in cgem_config()
1133 	WR4(sc, CGEM_INTR_EN, CGEM_INTR_RX_COMPLETE | CGEM_INTR_RX_OVERRUN |  in cgem_config()
1289 				WR4(sc, CGEM_DMA_CFG,  in cgem_ioctl()
1298 				WR4(sc, CGEM_DMA_CFG,  in cgem_ioctl()
1310 				WR4(sc, CGEM_NET_CFG, sc->net_cfg_shadow);  in cgem_ioctl()
1317 				WR4(sc, CGEM_NET_CFG, sc->net_cfg_shadow);  in cgem_ioctl()
1378 	WR4(sc, CGEM_PHY_MAINT, CGEM_PHY_MAINT_CLAUSE_22 |  in cgem_miibus_readreg()
1411 	WR4(sc, CGEM_PHY_MAINT, CGEM_PHY_MAINT_CLAUSE_22 |  in cgem_miibus_writereg()
1499 	WR4(sc, CGEM_NET_CFG, sc->net_cfg_shadow);  in cgem_mediachange()