Lines Matching refs:WR4
421 WR4(sc, sc->base_reg, reg); in pll_enable()
434 WR4(sc, sc->base_reg, reg); in pll_disable()
568 WR4(sc, sc->base_reg, reg); in plle_enable()
573 WR4(sc, PLLE_AUX, reg); in plle_enable()
583 WR4(sc, sc->misc_reg, reg); in plle_enable()
588 WR4(sc, PLLE_SS_CNTL, reg); in plle_enable()
594 WR4(sc, sc->base_reg, reg); in plle_enable()
607 WR4(sc, PLLE_SS_CNTL, reg); in plle_enable()
610 WR4(sc, PLLE_SS_CNTL, reg); in plle_enable()
614 WR4(sc, PLLE_SS_CNTL, reg); in plle_enable()
620 WR4(sc, sc->misc_reg, reg); in plle_enable()
627 WR4(sc, PLLE_AUX, reg); in plle_enable()
631 WR4(sc, PLLE_AUX, reg); in plle_enable()
638 WR4(sc, XUSBIO_PLL_CFG0, reg); in plle_enable()
642 WR4(sc, XUSBIO_PLL_CFG0, reg); in plle_enable()
655 WR4(sc, SATA_PLL_CFG0, reg); in plle_enable()
658 WR4(sc, SATA_PLL_CFG0, reg); in plle_enable()
663 WR4(sc, PCIE_PLL_CFG0, reg); in plle_enable()
696 WR4(sc, sc->base_reg, reg); in tegra124_pll_get_gate()
737 WR4(sc, sc->base_reg, reg); in pll_set_std()
742 WR4(sc, sc->base_reg, reg); in pll_set_std()
747 WR4(sc, sc->misc_reg, reg); in pll_set_std()
754 WR4(sc, sc->base_reg, reg); in pll_set_std()
916 WR4(sc, sc->base_reg, reg); in pllx_set_freq()
924 WR4(sc, sc->base_reg, reg); in pllx_set_freq()
931 WR4(sc, sc->misc_reg, reg); in pllx_set_freq()
936 WR4(sc, sc->base_reg, reg); in pllx_set_freq()
943 WR4(sc, sc->base_reg, reg); in pllx_set_freq()
1009 WR4(sc, sc->misc_reg, reg); in tegra124_pll_init()
1014 WR4(sc, sc->misc_reg, reg); in tegra124_pll_init()