Lines Matching refs:WR4

57 #define	WR4	(sc->write)  macro
325 WR4(sc, SDHCI_CLOCK_CONTROL, val32 & ~SDHCI_FSL_CLK_SDCLKEN); in fsl_sdhc_fdt_set_clock()
372 WR4(sc, SDHCI_CLOCK_CONTROL, val32); in fsl_sdhc_fdt_set_clock()
492 WR4(sc, SDHCI_FSL_PROT_CTRL, val32); in sdhci_fsl_fdt_write_1()
500 WR4(sc, off & ~3, val32); in sdhci_fsl_fdt_write_1()
529 WR4(sc, SDHCI_TRANSFER_MODE, sc->cmd_and_mode); in sdhci_fsl_fdt_write_2()
543 WR4(sc, off & ~3, val32); in sdhci_fsl_fdt_write_2()
572 WR4(sc, off, val); in sdhci_fsl_fdt_write_4()
723 WR4(sc, SDHCI_FSL_PROT_CTRL, val); in sdhci_fsl_fdt_switch_vccq()
747 WR4(sc, SDHCI_FSL_PROT_CTRL, val_old); in sdhci_fsl_fdt_switch_vccq()
962 WR4(sc, SDHCI_FSL_PROT_CTRL, val | buf_order); in sdhci_fsl_fdt_attach()
970 WR4(sc, SDHCI_CLOCK_CONTROL, val & ~SDHCI_FSL_CLK_SDCLKEN); in sdhci_fsl_fdt_attach()
972 WR4(sc, SDHCI_FSL_ESDHC_CTRL, val | SDHCI_FSL_ESDHC_CTRL_CLK_DIV2); in sdhci_fsl_fdt_attach()
989 WR4(sc, SDHCI_FSL_WTMK_LVL, SDHCI_FSL_WTMK_WR_512B | in sdhci_fsl_fdt_attach()
1107 WR4(sc, SDHCI_FSL_TBCTL, val); in sdhci_fsl_fdt_reset()
1117 WR4(sc, SDHCI_FSL_DLLCFG1, val); in sdhci_fsl_fdt_reset()
1138 WR4(sc, SDHCI_FSL_TBCTL, reg); in sdhci_fsl_switch_tuning_block()
1162 WR4(sc, SDHCI_FSL_TBPTR, reg); in sdhci_fsl_sw_tuning()
1170 WR4(sc, SDHCI_FSL_AUTOCERR, reg); in sdhci_fsl_sw_tuning()
1173 WR4(sc, SDHCI_FSL_AUTOCERR, reg); in sdhci_fsl_sw_tuning()
1178 WR4(sc, SDHCI_FSL_TBCTL, reg); in sdhci_fsl_sw_tuning()
1231 WR4(sc, SDHCI_FSL_ESDHC_CTRL, reg); in sdhci_fsl_fdt_tune()
1250 WR4(sc, SDHCI_FSL_TBCTL, reg); in sdhci_fsl_fdt_tune()
1299 WR4(sc, SDHCI_FSL_SDTIMINGCTL, reg); in sdhci_fsl_fdt_tune()
1348 WR4(sc, SDHCI_FSL_SDTIMINGCTL, reg); in sdhci_fsl_disable_hs400_mode()
1352 WR4(sc, SDHCI_FSL_SDCLKCTL, reg); in sdhci_fsl_disable_hs400_mode()
1363 WR4(sc, SDHCI_FSL_TBCTL, reg); in sdhci_fsl_disable_hs400_mode()
1377 WR4(sc, SDHCI_FSL_DLLCFG0, reg); in sdhci_fsl_disable_hs400_mode()
1381 WR4(sc, SDHCI_FSL_TBCTL, reg); in sdhci_fsl_disable_hs400_mode()
1404 WR4(sc, SDHCI_FSL_TBCTL, reg); in sdhci_fsl_enable_hs400_mode()
1407 WR4(sc, SDHCI_FSL_SDCLKCTL, reg); in sdhci_fsl_enable_hs400_mode()
1420 WR4(sc, SDHCI_FSL_DLLCFG0, reg); in sdhci_fsl_enable_hs400_mode()
1428 WR4(sc, SDHCI_FSL_DLLCFG0, reg); in sdhci_fsl_enable_hs400_mode()
1438 WR4(sc, SDHCI_FSL_TBCTL, reg); in sdhci_fsl_enable_hs400_mode()
1450 WR4(sc, SDHCI_FSL_ESDHC_CTRL, reg); in sdhci_fsl_enable_hs400_mode()
1513 WR4(sc, SDHCI_FSL_AUTOCERR, reg); in sdhci_fsl_fdt_set_uhs_timing()