e146a7ab | 04-Sep-2024 |
Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> |
drm/amd/display: Add kdoc entry for 'program_isharp_1dlut' in 'dpp401_dscl_program_isharp'
Added a descriptor for the 'program_isharp_1dlut' parameter, which is a flag used to determine whether to p
drm/amd/display: Add kdoc entry for 'program_isharp_1dlut' in 'dpp401_dscl_program_isharp'
Added a descriptor for the 'program_isharp_1dlut' parameter, which is a flag used to determine whether to program the isharp 1D LUT.
Fixes the below with gcc W=1: drivers/gpu/drm/amd/amdgpu/../display/dc/dpp/dcn401/dcn401_dpp_dscl.c:963: warning: Function parameter or struct member 'program_isharp_1dlut' not described in 'dpp401_dscl_program_isharp'
Cc: Tom Chung <chiahsuan.chung@amd.com> Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Cc: Roman Li <roman.li@amd.com> Cc: Alex Hung <alex.hung@amd.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Cc: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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4c4e9cb5 | 28-Aug-2024 |
Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> |
drm/amd/display: Add missing kdoc entry for 'bs_coeffs_updated' in dpp401_dscl_program_isharp
This commit addresses a missing kdoc for the 'bs_coeffs_updated' parameter in the 'dpp401_dscl_program_i
drm/amd/display: Add missing kdoc entry for 'bs_coeffs_updated' in dpp401_dscl_program_isharp
This commit addresses a missing kdoc for the 'bs_coeffs_updated' parameter in the 'dpp401_dscl_program_isharp' function. The 'bs_coeffs_updated' is a flag indicating whether the Blur and Scale Coefficients have been updated.
The 'dpp401_dscl_program_isharp' function is responsible for programming the isharp, which includes setting the isharp filter, noise gain, and blur and scale coefficients. If the 'bs_coeffs_updated' flag is set to true, the function updates the blur and scale coefficients.
Fixes the below with gcc W=1: drivers/gpu/drm/amd/amdgpu/../display/dc/dpp/dcn401/dcn401_dpp_dscl.c:961: warning: Function parameter or struct member 'bs_coeffs_updated' not described in 'dpp401_dscl_program_isharp'
Cc: Tom Chung <chiahsuan.chung@amd.com> Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Cc: Roman Li <roman.li@amd.com> Cc: Alex Hung <alex.hung@amd.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Cc: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Suggested-by: Tom Chung <chiahsuan.chung@amd.com> Reviewed-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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efaf1575 | 21-Aug-2024 |
Relja Vojvodic <Relja.Vojvodic@amd.com> |
drm/amd/display: Add sharpness control interface
- Add interface for controlling shapness level input into DCN. - Update SPL to support custom sharpness values. - Add support for different sharpness
drm/amd/display: Add sharpness control interface
- Add interface for controlling shapness level input into DCN. - Update SPL to support custom sharpness values. - Add support for different sharpness values depending on YUV/RGB content.
Reviewed-by: Samson Tam <samson.tam@amd.com> Signed-off-by: Relja Vojvodic <Relja.Vojvodic@amd.com> Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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6efc0ab3 | 16-Aug-2024 |
Samson Tam <Samson.Tam@amd.com> |
drm/amd/display: add back quality EASF and ISHARP and dc dependency changes
[Why] Addressed previous issues with quality changes and new issues due to rolling back quality changes.
[How] This reve
drm/amd/display: add back quality EASF and ISHARP and dc dependency changes
[Why] Addressed previous issues with quality changes and new issues due to rolling back quality changes.
[How] This reverts commit f9e6759888866748f31b6b6c2142a481d587f51f, fixes merge conflicts, and fixed some formatting errors. Store current sharpness level for each pregen table to minimize calculating sharpness table every time. Disable dynamic ODM when sharpness is enabled.
Reviewed-by: Jun Lei <jun.lei@amd.com> Signed-off-by: Samson Tam <Samson.Tam@amd.com> Signed-off-by: Zaeem Mohamed <zaeem.mohamed@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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272e6aab | 16-Aug-2024 |
Nevenko Stupar <Nevenko.Stupar@amd.com> |
drm/amd/display: Hardware cursor changes color when switched to software cursor
[Why & How] DCN4 Cursor has separate degamma block and should always do Cursor degamma for Cursor color modes.
Review
drm/amd/display: Hardware cursor changes color when switched to software cursor
[Why & How] DCN4 Cursor has separate degamma block and should always do Cursor degamma for Cursor color modes.
Reviewed-by: Chris Park <chris.park@amd.com> Signed-off-by: Nevenko Stupar <Nevenko.Stupar@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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267c5876 | 02-Aug-2024 |
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> |
drm/amd/display: Remove unnecessary call to REG_SEQ_SUBMIT|WAIT_DONE
[why & how] Remove unnecessary call to REG_SEQ_SUBMIT and REG_SEQ_WAIT_DONE, since those macros are not necessary anymore at the
drm/amd/display: Remove unnecessary call to REG_SEQ_SUBMIT|WAIT_DONE
[why & how] Remove unnecessary call to REG_SEQ_SUBMIT and REG_SEQ_WAIT_DONE, since those macros are not necessary anymore at the dpp1 set degamma. Those are part of an old implementation.
Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Tom Chung <chiahsuan.chung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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4a4c815b | 30-Jul-2024 |
Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> |
drm/amd/display: Align 'dpp401_dscl_program_isharp' with actual function parameters
This commit corrects the function comment for 'dpp401_dscl_program_isharp' in 'dcn401_dpp_dscl.c'. The comment pre
drm/amd/display: Align 'dpp401_dscl_program_isharp' with actual function parameters
This commit corrects the function comment for 'dpp401_dscl_program_isharp' in 'dcn401_dpp_dscl.c'. The comment previously included a description for a non-existent parameter 'bs_coeffs_updated'. This parameter description has been removed to reflect the function's actual parameters.
Fixes the below with gcc W=1: drivers/gpu/drm/amd/amdgpu/../display/dc/dpp/dcn401/dcn401_dpp_dscl.c:981: warning: Excess function parameter 'bs_coeffs_updated' description in 'dpp401_dscl_program_isharp'
Cc: Tom Chung <chiahsuan.chung@amd.com> Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Cc: Roman Li <roman.li@amd.com> Cc: Alex Hung <alex.hung@amd.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Cc: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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f9e67598 | 14-Jul-2024 |
Samson Tam <Samson.Tam@amd.com> |
drm/amd/display: roll back quality EASF and ISHARP and dc dependency changes
[Why] Seeing several regressions related to quality EASF and ISHARP changes and removing dc dependency changes.
[How] Ro
drm/amd/display: roll back quality EASF and ISHARP and dc dependency changes
[Why] Seeing several regressions related to quality EASF and ISHARP changes and removing dc dependency changes.
[How] Roll back SPL changes
Signed-off-by: Samson Tam <Samson.Tam@amd.com> Reviewed-by: Martin Leung <martin.leung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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0352e39e | 22-Jul-2024 |
Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> |
drm/amd/display: Add kdoc entry for 'bs_coeffs_updated' in dpp401_dscl_program_isharp
Fixes the below with gcc W=1: drivers/gpu/drm/amd/amdgpu/../display/dc/dpp/dcn401/dcn401_dpp_dscl.c:961: warning
drm/amd/display: Add kdoc entry for 'bs_coeffs_updated' in dpp401_dscl_program_isharp
Fixes the below with gcc W=1: drivers/gpu/drm/amd/amdgpu/../display/dc/dpp/dcn401/dcn401_dpp_dscl.c:961: warning: Function parameter or struct member 'bs_coeffs_updated' not described in 'dpp401_dscl_program_isharp'
Fixes: 94beb4ac1b3b ("drm/amd/display: ensure EASF and ISHARP coefficients are programmed together") Cc: Tom Chung <chiahsuan.chung@amd.com> Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Cc: Roman Li <roman.li@amd.com> Cc: Alex Hung <alex.hung@amd.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Cc: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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94beb4ac | 10-Jul-2024 |
Samson Tam <samson.tam@amd.com> |
drm/amd/display: ensure EASF and ISHARP coefficients are programmed together
[Why] EASF coefficients are programmed to RAM and then RAM selector is toggled. ISHARP coefficients are programmed after
drm/amd/display: ensure EASF and ISHARP coefficients are programmed together
[Why] EASF coefficients are programmed to RAM and then RAM selector is toggled. ISHARP coefficients are programmed after so they will not be in the same RAM block
[How] Move ISHARP programming before EASF programming Add flag if ISHARP coefficients are updated. If so, then force EASF coefficients programming
Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Signed-off-by: Samson Tam <samson.tam@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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acce1eb8 | 04-Jul-2024 |
Daniel Sa <daniel.sa@amd.com> |
drm/amd/display: Set Cursor Matrix to bypass instead of Input Plane
why: When the cursor disappears/reappears on fullscreen video, there is a short transitional period where the cursor's color matri
drm/amd/display: Set Cursor Matrix to bypass instead of Input Plane
why: When the cursor disappears/reappears on fullscreen video, there is a short transitional period where the cursor's color matrix is using the same format as the video plane. This sets the cursor to the wrong color momentarily before the UI plane appears, correcting the color.
how: Instead of defaulting to using the color space from the input plane, default to bypass mode.
Reviewed-by: Nevenko Stupar <nevenko.stupar@amd.com> Signed-off-by: Jerry Zuo <jerry.zuo@amd.com> Signed-off-by: Daniel Sa <daniel.sa@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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c83ecc0b | 27-Jun-2024 |
Relja Vojvodic <relja.vojvodic@amd.com> |
drm/amd/display: Implement bias and scale pre scl
why: New scaler needs the input to be full range color space. This will also fix issues that come up due to not having a predefined limited color sp
drm/amd/display: Implement bias and scale pre scl
why: New scaler needs the input to be full range color space. This will also fix issues that come up due to not having a predefined limited color space matrix for certain color spaces
how: Use bias and scale HW to expand the range of limited color spaces to full before the scaler
Reviewed-by: Krunoslav Kovac <krunoslav.kovac@amd.com> Signed-off-by: Jerry Zuo <jerry.zuo@amd.com> Signed-off-by: Relja Vojvodic <relja.vojvodic@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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|
5f30ee49 | 20-Jun-2024 |
Samson Tam <samson.tam@amd.com> |
drm/amd/display: quality improvements for EASF and ISHARP
[Why] Update coefficients and LUT tables for scaler and sharpener to improve quality and support different use cases (SDR/HDR)
[How] Move
drm/amd/display: quality improvements for EASF and ISHARP
[Why] Update coefficients and LUT tables for scaler and sharpener to improve quality and support different use cases (SDR/HDR)
[How] Move scaler coefficients to new file dc_spl_scl_easf_filters.c Remove older coefficients file dc_sp_scl_filters_old.c Update default taps for EASF support Update LLS policy for DON'T CARE case Update cositing offset from 0.5 to 0.25 Add support to adjust sharpness based on level, use case, and scaling ratio ( using discrete levels ) Apply sharpness to all RGB surfaces and both NV12 and P010 video ( in fullscreen only ). Upscale and 1:1 ratios only Enable scaler when sharpening 1:1 ratios Add support for coefficients that are in S1.10 format (convert to S1.12 format)
Reviewed-by: Jun Lei <jun.lei@amd.com> Signed-off-by: Jerry Zuo <jerry.zuo@amd.com> Signed-off-by: Samson Tam <samson.tam@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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|
ee8287e0 | 10-Jun-2024 |
Nevenko Stupar <nevenko.stupar@amd.com> |
drm/amd/display: Fix cursor issues with ODMs and HW rotations
[WHY & HOW] Current code for cursor positions does not work properly with different ODM options and HW rotations like ODM 2to1, 3to1 and
drm/amd/display: Fix cursor issues with ODMs and HW rotations
[WHY & HOW] Current code for cursor positions does not work properly with different ODM options and HW rotations like ODM 2to1, 3to1 and 4to1, and has different issues depending on angle of HW rotations.
[HOW] Fixed these issues so to work properly when ODM is used with HW rotations.
Reviewed-by: Sridevi Arvindekar <sridevi.arvindekar@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Nevenko Stupar <nevenko.stupar@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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|
223ac8b6 | 31-May-2024 |
Ivan Lipski <ivlipski@amd.com> |
drm/amd/display: Remove redundant if conditions
[WHY] Coverity analysis flagged the two if conditions in dcn30_dpp.c and dcn401_dpp.c as DEADCODE since they are never true, since the variable 'progr
drm/amd/display: Remove redundant if conditions
[WHY] Coverity analysis flagged the two if conditions in dcn30_dpp.c and dcn401_dpp.c as DEADCODE since they are never true, since the variable 'program_prealpha_dealpha' is initialized at 0 and never chagnes.
[HOW] Removed the variable 'program_prealpha_dealpha' and the if conditions.
Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com> Signed-off-by: Ivan Lipski <ivlipski@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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|
470679ef | 21-May-2024 |
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> |
drm/amd/display: Guard reading 3DLUT registers for dcn32/dcn35
[Why] 3DLUT is not part of the DPP on DCN32/DCN35 ASIC and these registers now exist in MCM state.
[How] Add guards when reading DPP s
drm/amd/display: Guard reading 3DLUT registers for dcn32/dcn35
[Why] 3DLUT is not part of the DPP on DCN32/DCN35 ASIC and these registers now exist in MCM state.
[How] Add guards when reading DPP state based on whether the register has a valid offset.
Reviewed-by: Sung joon Kim <sungjoon.kim@amd.com> Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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5d74be8c | 15-May-2024 |
Samson Tam <samson.tam@amd.com> |
drm/amd/display: fix YUV video color corruption in DCN401
[Why] Missing check causes sequence error which results in chroma filter coefficients not being updated in certain modes when we display Y
drm/amd/display: fix YUV video color corruption in DCN401
[Why] Missing check causes sequence error which results in chroma filter coefficients not being updated in certain modes when we display YUV video in fullscreen. This results in color corruption in video
[How] Add back chroma_coef_mode check in dscl_set_scl_filter so that filter coefficients are calculated and updated when we have YUV surface
Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com> Signed-off-by: Samson Tam <samson.tam@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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ddef2cfb | 14-May-2024 |
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> |
drm/amd/display: Remove unused code
This commit removes some unused code with the required adjustments.
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Harry Wentland <harry.we
drm/amd/display: Remove unused code
This commit removes some unused code with the required adjustments.
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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2998bccf | 26-Apr-2024 |
Samson Tam <Samson.Tam@amd.com> |
drm/amd/display: Enable ISHARP support for DCN401
[Why] Enable sharpener support for DCN401
[How] - Removed memcmp check that was preventing ISHARP from being enabled. - Add missing ISHARP register
drm/amd/display: Enable ISHARP support for DCN401
[Why] Enable sharpener support for DCN401
[How] - Removed memcmp check that was preventing ISHARP from being enabled. - Add missing ISHARP register defines, masks, and writes. - Add programming of Blur and Scale coefficients. - Program FMT_MODE and NLDELTA registers based on LLS_PREF and pixel - format - Only enable ISHARP for YUV420 - Add disabling of ISHARP - Add debug flags and registry keys for debugging ISHARP. - Set default to medium level
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Samson Tam <Samson.Tam@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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c2edec16 | 27-Apr-2024 |
Sridevi <sarvinde@amd.com> |
drm/amd/display: Fix incorrect cursor position for dcn401
[Why] Incorrect cursor position calculation in some scenarios. Also for mirror and rotation cases.
[How] Fix for incorrect cursor position
drm/amd/display: Fix incorrect cursor position for dcn401
[Why] Incorrect cursor position calculation in some scenarios. Also for mirror and rotation cases.
[How] Fix for incorrect cursor position. Added new test scenarios for diags cursor test. Updated CRC for few of the diags cursor test scenarios.
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Sridevi <sarvinde@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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7a1dd866 | 24-Apr-2024 |
Samson Tam <Samson.Tam@amd.com> |
drm/amd/display: enable EASF support for DCN40
[Why] Enable adaptive scaler support for DCN401
[How] - Enable build flag for SPL - Set prefer_easf flag to true - Apply light linear scaling policy b
drm/amd/display: enable EASF support for DCN40
[Why] Enable adaptive scaler support for DCN401
[How] - Enable build flag for SPL - Set prefer_easf flag to true - Apply light linear scaling policy based on transfer function and pixel format. Choose between linear or non-linear scaling - Set matrix_mode based on pixel format - Disable ring estimator - Add missing EASF register defines, masks, and writes - Disable EASF if scale ratio or number of taps is unsupported and when bypassing the scaler - Add debug flags and registry keys for debugging SPL and EASF - Add support for Visual Confirm with EASF
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Samson Tam <Samson.Tam@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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6690d949 | 26-Apr-2024 |
Samson Tam <samson.tam@amd.com> |
drm/amd/display: Add COEF filter types for DCN401
Add VERTICAL_BLUR_SCALE & HORIZONTAL_BLUR_SCALE types.
Reviewed-by: Jun Lei <jun.lei@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by
drm/amd/display: Add COEF filter types for DCN401
Add VERTICAL_BLUR_SCALE & HORIZONTAL_BLUR_SCALE types.
Reviewed-by: Jun Lei <jun.lei@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Samson Tam <samson.tam@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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01d6606b | 28-Apr-2024 |
Dan Carpenter <dan.carpenter@linaro.org> |
drm/amd/display: re-indent dpp401_dscl_program_isharp()
Smatch complains because some lines are indented more than they should be. I went a bit crazy re-indenting this. ;)
The comments were not u
drm/amd/display: re-indent dpp401_dscl_program_isharp()
Smatch complains because some lines are indented more than they should be. I went a bit crazy re-indenting this. ;)
The comments were not useful except as a marker of things which are left to implement so I deleted most of them except for the TODO.
I introduced a "data" pointer so that I could replace "scl_data->dscl_prog_data." with just "data->" and shorten the lines a bit. It's more readable without the line breaks.
I also tried to align it so you can see what is changing on each line.
Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org> Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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9e9ad056 | 23-Apr-2024 |
Wayne Lin <Wayne.Lin@amd.com> |
drm/amd/display: Remove unnecessary files
[Why & How] We accidentally upstream unnecessary files. Remove them.
Reviewed-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Wayne Lin <Wayne.Lin@a
drm/amd/display: Remove unnecessary files
[Why & How] We accidentally upstream unnecessary files. Remove them.
Reviewed-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Wayne Lin <Wayne.Lin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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dff0360a | 17-Apr-2024 |
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> |
drm/amd/display: Improve registers write
Add REG_SEQ_SUBMIT and REG_SEQ_WAIT_DONE to optimize the burst write for the regama lut.
Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Rodrigo Siqu
drm/amd/display: Improve registers write
Add REG_SEQ_SUBMIT and REG_SEQ_WAIT_DONE to optimize the burst write for the regama lut.
Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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