1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*- 2 */ 3 /* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30 #include <linux/acpi.h> 31 #include <linux/device.h> 32 #include <linux/module.h> 33 #include <linux/oom.h> 34 #include <linux/pci.h> 35 #include <linux/pm.h> 36 #include <linux/pm_runtime.h> 37 #include <linux/slab.h> 38 #include <linux/string_helpers.h> 39 #include <linux/vga_switcheroo.h> 40 #include <linux/vt.h> 41 42 #include <drm/drm_aperture.h> 43 #include <drm/drm_atomic_helper.h> 44 #include <drm/drm_ioctl.h> 45 #include <drm/drm_managed.h> 46 #include <drm/drm_probe_helper.h> 47 48 #include "display/intel_acpi.h" 49 #include "display/intel_bw.h" 50 #include "display/intel_cdclk.h" 51 #include "display/intel_display_driver.h" 52 #include "display/intel_display_types.h" 53 #include "display/intel_dmc.h" 54 #include "display/intel_dp.h" 55 #include "display/intel_dpt.h" 56 #include "display/intel_encoder.h" 57 #include "display/intel_fbdev.h" 58 #include "display/intel_hotplug.h" 59 #include "display/intel_overlay.h" 60 #include "display/intel_pch_refclk.h" 61 #include "display/intel_pipe_crc.h" 62 #include "display/intel_pps.h" 63 #include "display/intel_sprite.h" 64 #include "display/intel_vga.h" 65 #include "display/skl_watermark.h" 66 67 #include "gem/i915_gem_context.h" 68 #include "gem/i915_gem_create.h" 69 #include "gem/i915_gem_dmabuf.h" 70 #include "gem/i915_gem_ioctls.h" 71 #include "gem/i915_gem_mman.h" 72 #include "gem/i915_gem_pm.h" 73 #include "gt/intel_gt.h" 74 #include "gt/intel_gt_pm.h" 75 #include "gt/intel_gt_print.h" 76 #include "gt/intel_rc6.h" 77 78 #include "pxp/intel_pxp.h" 79 #include "pxp/intel_pxp_debugfs.h" 80 #include "pxp/intel_pxp_pm.h" 81 82 #include "soc/intel_dram.h" 83 #include "soc/intel_gmch.h" 84 85 #include "i915_debugfs.h" 86 #include "i915_driver.h" 87 #include "i915_drm_client.h" 88 #include "i915_drv.h" 89 #include "i915_file_private.h" 90 #include "i915_getparam.h" 91 #include "i915_hwmon.h" 92 #include "i915_ioc32.h" 93 #include "i915_ioctl.h" 94 #include "i915_irq.h" 95 #include "i915_memcpy.h" 96 #include "i915_perf.h" 97 #include "i915_query.h" 98 #include "i915_suspend.h" 99 #include "i915_switcheroo.h" 100 #include "i915_sysfs.h" 101 #include "i915_utils.h" 102 #include "i915_vgpu.h" 103 #include "intel_clock_gating.h" 104 #include "intel_gvt.h" 105 #include "intel_memory_region.h" 106 #include "intel_pci_config.h" 107 #include "intel_pcode.h" 108 #include "intel_region_ttm.h" 109 #include "vlv_suspend.h" 110 111 static const struct drm_driver i915_drm_driver; 112 113 static int i915_workqueues_init(struct drm_i915_private *dev_priv) 114 { 115 /* 116 * The i915 workqueue is primarily used for batched retirement of 117 * requests (and thus managing bo) once the task has been completed 118 * by the GPU. i915_retire_requests() is called directly when we 119 * need high-priority retirement, such as waiting for an explicit 120 * bo. 121 * 122 * It is also used for periodic low-priority events, such as 123 * idle-timers and recording error state. 124 * 125 * All tasks on the workqueue are expected to acquire the dev mutex 126 * so there is no point in running more than one instance of the 127 * workqueue at any time. Use an ordered one. 128 */ 129 dev_priv->wq = alloc_ordered_workqueue("i915", 0); 130 if (dev_priv->wq == NULL) 131 goto out_err; 132 133 dev_priv->display.hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0); 134 if (dev_priv->display.hotplug.dp_wq == NULL) 135 goto out_free_wq; 136 137 /* 138 * The unordered i915 workqueue should be used for all work 139 * scheduling that do not require running in order, which used 140 * to be scheduled on the system_wq before moving to a driver 141 * instance due deprecation of flush_scheduled_work(). 142 */ 143 dev_priv->unordered_wq = alloc_workqueue("i915-unordered", 0, 0); 144 if (dev_priv->unordered_wq == NULL) 145 goto out_free_dp_wq; 146 147 return 0; 148 149 out_free_dp_wq: 150 destroy_workqueue(dev_priv->display.hotplug.dp_wq); 151 out_free_wq: 152 destroy_workqueue(dev_priv->wq); 153 out_err: 154 drm_err(&dev_priv->drm, "Failed to allocate workqueues.\n"); 155 156 return -ENOMEM; 157 } 158 159 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv) 160 { 161 destroy_workqueue(dev_priv->unordered_wq); 162 destroy_workqueue(dev_priv->display.hotplug.dp_wq); 163 destroy_workqueue(dev_priv->wq); 164 } 165 166 /* 167 * We don't keep the workarounds for pre-production hardware, so we expect our 168 * driver to fail on these machines in one way or another. A little warning on 169 * dmesg may help both the user and the bug triagers. 170 * 171 * Our policy for removing pre-production workarounds is to keep the 172 * current gen workarounds as a guide to the bring-up of the next gen 173 * (workarounds have a habit of persisting!). Anything older than that 174 * should be removed along with the complications they introduce. 175 */ 176 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv) 177 { 178 bool pre = false; 179 180 pre |= IS_HASWELL_EARLY_SDV(dev_priv); 181 pre |= IS_SKYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x6; 182 pre |= IS_BROXTON(dev_priv) && INTEL_REVID(dev_priv) < 0xA; 183 pre |= IS_KABYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1; 184 pre |= IS_GEMINILAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x3; 185 pre |= IS_ICELAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x7; 186 pre |= IS_TIGERLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1; 187 pre |= IS_DG1(dev_priv) && INTEL_REVID(dev_priv) < 0x1; 188 pre |= IS_DG2_G10(dev_priv) && INTEL_REVID(dev_priv) < 0x8; 189 pre |= IS_DG2_G11(dev_priv) && INTEL_REVID(dev_priv) < 0x5; 190 pre |= IS_DG2_G12(dev_priv) && INTEL_REVID(dev_priv) < 0x1; 191 192 if (pre) { 193 drm_err(&dev_priv->drm, "This is a pre-production stepping. " 194 "It may not be fully functional.\n"); 195 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK); 196 } 197 } 198 199 static void sanitize_gpu(struct drm_i915_private *i915) 200 { 201 if (!INTEL_INFO(i915)->gpu_reset_clobbers_display) { 202 struct intel_gt *gt; 203 unsigned int i; 204 205 for_each_gt(gt, i915, i) 206 intel_gt_reset_all_engines(gt); 207 } 208 } 209 210 /** 211 * i915_driver_early_probe - setup state not requiring device access 212 * @dev_priv: device private 213 * 214 * Initialize everything that is a "SW-only" state, that is state not 215 * requiring accessing the device or exposing the driver via kernel internal 216 * or userspace interfaces. Example steps belonging here: lock initialization, 217 * system memory allocation, setting up device specific attributes and 218 * function hooks not requiring accessing the device. 219 */ 220 static int i915_driver_early_probe(struct drm_i915_private *dev_priv) 221 { 222 int ret = 0; 223 224 if (i915_inject_probe_failure(dev_priv)) 225 return -ENODEV; 226 227 intel_device_info_runtime_init_early(dev_priv); 228 229 intel_step_init(dev_priv); 230 231 intel_uncore_mmio_debug_init_early(dev_priv); 232 233 spin_lock_init(&dev_priv->irq_lock); 234 spin_lock_init(&dev_priv->gpu_error.lock); 235 236 mutex_init(&dev_priv->sb_lock); 237 cpu_latency_qos_add_request(&dev_priv->sb_qos, PM_QOS_DEFAULT_VALUE); 238 239 i915_memcpy_init_early(dev_priv); 240 intel_runtime_pm_init_early(&dev_priv->runtime_pm); 241 242 ret = i915_workqueues_init(dev_priv); 243 if (ret < 0) 244 return ret; 245 246 ret = vlv_suspend_init(dev_priv); 247 if (ret < 0) 248 goto err_workqueues; 249 250 ret = intel_region_ttm_device_init(dev_priv); 251 if (ret) 252 goto err_ttm; 253 254 ret = intel_root_gt_init_early(dev_priv); 255 if (ret < 0) 256 goto err_rootgt; 257 258 i915_gem_init_early(dev_priv); 259 260 /* This must be called before any calls to HAS_PCH_* */ 261 intel_detect_pch(dev_priv); 262 263 intel_irq_init(dev_priv); 264 intel_display_driver_early_probe(dev_priv); 265 intel_clock_gating_hooks_init(dev_priv); 266 267 intel_detect_preproduction_hw(dev_priv); 268 269 return 0; 270 271 err_rootgt: 272 intel_region_ttm_device_fini(dev_priv); 273 err_ttm: 274 vlv_suspend_cleanup(dev_priv); 275 err_workqueues: 276 i915_workqueues_cleanup(dev_priv); 277 return ret; 278 } 279 280 /** 281 * i915_driver_late_release - cleanup the setup done in 282 * i915_driver_early_probe() 283 * @dev_priv: device private 284 */ 285 static void i915_driver_late_release(struct drm_i915_private *dev_priv) 286 { 287 intel_irq_fini(dev_priv); 288 intel_power_domains_cleanup(dev_priv); 289 i915_gem_cleanup_early(dev_priv); 290 intel_gt_driver_late_release_all(dev_priv); 291 intel_region_ttm_device_fini(dev_priv); 292 vlv_suspend_cleanup(dev_priv); 293 i915_workqueues_cleanup(dev_priv); 294 295 cpu_latency_qos_remove_request(&dev_priv->sb_qos); 296 mutex_destroy(&dev_priv->sb_lock); 297 298 i915_params_free(&dev_priv->params); 299 } 300 301 /** 302 * i915_driver_mmio_probe - setup device MMIO 303 * @dev_priv: device private 304 * 305 * Setup minimal device state necessary for MMIO accesses later in the 306 * initialization sequence. The setup here should avoid any other device-wide 307 * side effects or exposing the driver via kernel internal or user space 308 * interfaces. 309 */ 310 static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv) 311 { 312 struct intel_gt *gt; 313 int ret, i; 314 315 if (i915_inject_probe_failure(dev_priv)) 316 return -ENODEV; 317 318 ret = intel_gmch_bridge_setup(dev_priv); 319 if (ret < 0) 320 return ret; 321 322 for_each_gt(gt, dev_priv, i) { 323 ret = intel_uncore_init_mmio(gt->uncore); 324 if (ret) 325 return ret; 326 327 ret = drmm_add_action_or_reset(&dev_priv->drm, 328 intel_uncore_fini_mmio, 329 gt->uncore); 330 if (ret) 331 return ret; 332 } 333 334 /* Try to make sure MCHBAR is enabled before poking at it */ 335 intel_gmch_bar_setup(dev_priv); 336 intel_device_info_runtime_init(dev_priv); 337 intel_display_device_info_runtime_init(dev_priv); 338 339 for_each_gt(gt, dev_priv, i) { 340 ret = intel_gt_init_mmio(gt); 341 if (ret) 342 goto err_uncore; 343 } 344 345 /* As early as possible, scrub existing GPU state before clobbering */ 346 sanitize_gpu(dev_priv); 347 348 return 0; 349 350 err_uncore: 351 intel_gmch_bar_teardown(dev_priv); 352 353 return ret; 354 } 355 356 /** 357 * i915_driver_mmio_release - cleanup the setup done in i915_driver_mmio_probe() 358 * @dev_priv: device private 359 */ 360 static void i915_driver_mmio_release(struct drm_i915_private *dev_priv) 361 { 362 intel_gmch_bar_teardown(dev_priv); 363 } 364 365 /** 366 * i915_set_dma_info - set all relevant PCI dma info as configured for the 367 * platform 368 * @i915: valid i915 instance 369 * 370 * Set the dma max segment size, device and coherent masks. The dma mask set 371 * needs to occur before i915_ggtt_probe_hw. 372 * 373 * A couple of platforms have special needs. Address them as well. 374 * 375 */ 376 static int i915_set_dma_info(struct drm_i915_private *i915) 377 { 378 unsigned int mask_size = INTEL_INFO(i915)->dma_mask_size; 379 int ret; 380 381 GEM_BUG_ON(!mask_size); 382 383 /* 384 * We don't have a max segment size, so set it to the max so sg's 385 * debugging layer doesn't complain 386 */ 387 dma_set_max_seg_size(i915->drm.dev, UINT_MAX); 388 389 ret = dma_set_mask(i915->drm.dev, DMA_BIT_MASK(mask_size)); 390 if (ret) 391 goto mask_err; 392 393 /* overlay on gen2 is broken and can't address above 1G */ 394 if (GRAPHICS_VER(i915) == 2) 395 mask_size = 30; 396 397 /* 398 * 965GM sometimes incorrectly writes to hardware status page (HWS) 399 * using 32bit addressing, overwriting memory if HWS is located 400 * above 4GB. 401 * 402 * The documentation also mentions an issue with undefined 403 * behaviour if any general state is accessed within a page above 4GB, 404 * which also needs to be handled carefully. 405 */ 406 if (IS_I965G(i915) || IS_I965GM(i915)) 407 mask_size = 32; 408 409 ret = dma_set_coherent_mask(i915->drm.dev, DMA_BIT_MASK(mask_size)); 410 if (ret) 411 goto mask_err; 412 413 return 0; 414 415 mask_err: 416 drm_err(&i915->drm, "Can't set DMA mask/consistent mask (%d)\n", ret); 417 return ret; 418 } 419 420 static int i915_pcode_init(struct drm_i915_private *i915) 421 { 422 struct intel_gt *gt; 423 int id, ret; 424 425 for_each_gt(gt, i915, id) { 426 ret = intel_pcode_init(gt->uncore); 427 if (ret) { 428 gt_err(gt, "intel_pcode_init failed %d\n", ret); 429 return ret; 430 } 431 } 432 433 return 0; 434 } 435 436 /** 437 * i915_driver_hw_probe - setup state requiring device access 438 * @dev_priv: device private 439 * 440 * Setup state that requires accessing the device, but doesn't require 441 * exposing the driver via kernel internal or userspace interfaces. 442 */ 443 static int i915_driver_hw_probe(struct drm_i915_private *dev_priv) 444 { 445 struct intel_display *display = &dev_priv->display; 446 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 447 int ret; 448 449 if (i915_inject_probe_failure(dev_priv)) 450 return -ENODEV; 451 452 if (HAS_PPGTT(dev_priv)) { 453 if (intel_vgpu_active(dev_priv) && 454 !intel_vgpu_has_full_ppgtt(dev_priv)) { 455 drm_err(&dev_priv->drm, 456 "incompatible vGPU found, support for isolated ppGTT required\n"); 457 return -ENXIO; 458 } 459 } 460 461 if (HAS_EXECLISTS(dev_priv)) { 462 /* 463 * Older GVT emulation depends upon intercepting CSB mmio, 464 * which we no longer use, preferring to use the HWSP cache 465 * instead. 466 */ 467 if (intel_vgpu_active(dev_priv) && 468 !intel_vgpu_has_hwsp_emulation(dev_priv)) { 469 drm_err(&dev_priv->drm, 470 "old vGPU host found, support for HWSP emulation required\n"); 471 return -ENXIO; 472 } 473 } 474 475 /* needs to be done before ggtt probe */ 476 intel_dram_edram_detect(dev_priv); 477 478 ret = i915_set_dma_info(dev_priv); 479 if (ret) 480 return ret; 481 482 ret = i915_perf_init(dev_priv); 483 if (ret) 484 return ret; 485 486 ret = i915_ggtt_probe_hw(dev_priv); 487 if (ret) 488 goto err_perf; 489 490 ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, dev_priv->drm.driver); 491 if (ret) 492 goto err_ggtt; 493 494 ret = i915_ggtt_init_hw(dev_priv); 495 if (ret) 496 goto err_ggtt; 497 498 /* 499 * Make sure we probe lmem before we probe stolen-lmem. The BAR size 500 * might be different due to bar resizing. 501 */ 502 ret = intel_gt_tiles_init(dev_priv); 503 if (ret) 504 goto err_ggtt; 505 506 ret = intel_memory_regions_hw_probe(dev_priv); 507 if (ret) 508 goto err_ggtt; 509 510 ret = i915_ggtt_enable_hw(dev_priv); 511 if (ret) { 512 drm_err(&dev_priv->drm, "failed to enable GGTT\n"); 513 goto err_mem_regions; 514 } 515 516 pci_set_master(pdev); 517 518 /* On the 945G/GM, the chipset reports the MSI capability on the 519 * integrated graphics even though the support isn't actually there 520 * according to the published specs. It doesn't appear to function 521 * correctly in testing on 945G. 522 * This may be a side effect of MSI having been made available for PEG 523 * and the registers being closely associated. 524 * 525 * According to chipset errata, on the 965GM, MSI interrupts may 526 * be lost or delayed, and was defeatured. MSI interrupts seem to 527 * get lost on g4x as well, and interrupt delivery seems to stay 528 * properly dead afterwards. So we'll just disable them for all 529 * pre-gen5 chipsets. 530 * 531 * dp aux and gmbus irq on gen4 seems to be able to generate legacy 532 * interrupts even when in MSI mode. This results in spurious 533 * interrupt warnings if the legacy irq no. is shared with another 534 * device. The kernel then disables that interrupt source and so 535 * prevents the other device from working properly. 536 */ 537 if (GRAPHICS_VER(dev_priv) >= 5) { 538 if (pci_enable_msi(pdev) < 0) 539 drm_dbg(&dev_priv->drm, "can't enable MSI"); 540 } 541 542 ret = intel_gvt_init(dev_priv); 543 if (ret) 544 goto err_msi; 545 546 intel_opregion_setup(display); 547 548 ret = i915_pcode_init(dev_priv); 549 if (ret) 550 goto err_opregion; 551 552 /* 553 * Fill the dram structure to get the system dram info. This will be 554 * used for memory latency calculation. 555 */ 556 intel_dram_detect(dev_priv); 557 558 intel_bw_init_hw(dev_priv); 559 560 return 0; 561 562 err_opregion: 563 intel_opregion_cleanup(display); 564 err_msi: 565 if (pdev->msi_enabled) 566 pci_disable_msi(pdev); 567 err_mem_regions: 568 intel_memory_regions_driver_release(dev_priv); 569 err_ggtt: 570 i915_ggtt_driver_release(dev_priv); 571 i915_gem_drain_freed_objects(dev_priv); 572 i915_ggtt_driver_late_release(dev_priv); 573 err_perf: 574 i915_perf_fini(dev_priv); 575 return ret; 576 } 577 578 /** 579 * i915_driver_hw_remove - cleanup the setup done in i915_driver_hw_probe() 580 * @dev_priv: device private 581 */ 582 static void i915_driver_hw_remove(struct drm_i915_private *dev_priv) 583 { 584 struct intel_display *display = &dev_priv->display; 585 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 586 587 i915_perf_fini(dev_priv); 588 589 intel_opregion_cleanup(display); 590 591 if (pdev->msi_enabled) 592 pci_disable_msi(pdev); 593 } 594 595 /** 596 * i915_driver_register - register the driver with the rest of the system 597 * @dev_priv: device private 598 * 599 * Perform any steps necessary to make the driver available via kernel 600 * internal or userspace interfaces. 601 */ 602 static void i915_driver_register(struct drm_i915_private *dev_priv) 603 { 604 struct intel_gt *gt; 605 unsigned int i; 606 607 i915_gem_driver_register(dev_priv); 608 i915_pmu_register(dev_priv); 609 610 intel_vgpu_register(dev_priv); 611 612 /* Reveal our presence to userspace */ 613 if (drm_dev_register(&dev_priv->drm, 0)) { 614 drm_err(&dev_priv->drm, 615 "Failed to register driver for userspace access!\n"); 616 return; 617 } 618 619 i915_debugfs_register(dev_priv); 620 i915_setup_sysfs(dev_priv); 621 622 /* Depends on sysfs having been initialized */ 623 i915_perf_register(dev_priv); 624 625 for_each_gt(gt, dev_priv, i) 626 intel_gt_driver_register(gt); 627 628 intel_pxp_debugfs_register(dev_priv->pxp); 629 630 i915_hwmon_register(dev_priv); 631 632 intel_display_driver_register(dev_priv); 633 634 intel_power_domains_enable(dev_priv); 635 intel_runtime_pm_enable(&dev_priv->runtime_pm); 636 637 intel_register_dsm_handler(); 638 639 if (i915_switcheroo_register(dev_priv)) 640 drm_err(&dev_priv->drm, "Failed to register vga switcheroo!\n"); 641 } 642 643 /** 644 * i915_driver_unregister - cleanup the registration done in i915_driver_regiser() 645 * @dev_priv: device private 646 */ 647 static void i915_driver_unregister(struct drm_i915_private *dev_priv) 648 { 649 struct intel_gt *gt; 650 unsigned int i; 651 652 i915_switcheroo_unregister(dev_priv); 653 654 intel_unregister_dsm_handler(); 655 656 intel_runtime_pm_disable(&dev_priv->runtime_pm); 657 intel_power_domains_disable(dev_priv); 658 659 intel_display_driver_unregister(dev_priv); 660 661 intel_pxp_fini(dev_priv); 662 663 for_each_gt(gt, dev_priv, i) 664 intel_gt_driver_unregister(gt); 665 666 i915_hwmon_unregister(dev_priv); 667 668 i915_perf_unregister(dev_priv); 669 i915_pmu_unregister(dev_priv); 670 671 i915_teardown_sysfs(dev_priv); 672 drm_dev_unplug(&dev_priv->drm); 673 674 i915_gem_driver_unregister(dev_priv); 675 } 676 677 void 678 i915_print_iommu_status(struct drm_i915_private *i915, struct drm_printer *p) 679 { 680 drm_printf(p, "iommu: %s\n", 681 str_enabled_disabled(i915_vtd_active(i915))); 682 } 683 684 static void i915_welcome_messages(struct drm_i915_private *dev_priv) 685 { 686 if (drm_debug_enabled(DRM_UT_DRIVER)) { 687 struct drm_printer p = drm_dbg_printer(&dev_priv->drm, DRM_UT_DRIVER, 688 "device info:"); 689 struct intel_gt *gt; 690 unsigned int i; 691 692 drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n", 693 INTEL_DEVID(dev_priv), 694 INTEL_REVID(dev_priv), 695 intel_platform_name(INTEL_INFO(dev_priv)->platform), 696 intel_subplatform(RUNTIME_INFO(dev_priv), 697 INTEL_INFO(dev_priv)->platform), 698 GRAPHICS_VER(dev_priv)); 699 700 intel_device_info_print(INTEL_INFO(dev_priv), 701 RUNTIME_INFO(dev_priv), &p); 702 i915_print_iommu_status(dev_priv, &p); 703 for_each_gt(gt, dev_priv, i) 704 intel_gt_info_print(>->info, &p); 705 } 706 707 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG)) 708 drm_info(&dev_priv->drm, "DRM_I915_DEBUG enabled\n"); 709 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) 710 drm_info(&dev_priv->drm, "DRM_I915_DEBUG_GEM enabled\n"); 711 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)) 712 drm_info(&dev_priv->drm, 713 "DRM_I915_DEBUG_RUNTIME_PM enabled\n"); 714 } 715 716 static struct drm_i915_private * 717 i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent) 718 { 719 const struct intel_device_info *match_info = 720 (struct intel_device_info *)ent->driver_data; 721 struct drm_i915_private *i915; 722 723 i915 = devm_drm_dev_alloc(&pdev->dev, &i915_drm_driver, 724 struct drm_i915_private, drm); 725 if (IS_ERR(i915)) 726 return i915; 727 728 pci_set_drvdata(pdev, i915); 729 730 /* Device parameters start as a copy of module parameters. */ 731 i915_params_copy(&i915->params, &i915_modparams); 732 733 /* Set up device info and initial runtime info. */ 734 intel_device_info_driver_create(i915, pdev->device, match_info); 735 736 intel_display_device_probe(i915); 737 738 return i915; 739 } 740 741 /** 742 * i915_driver_probe - setup chip and create an initial config 743 * @pdev: PCI device 744 * @ent: matching PCI ID entry 745 * 746 * The driver probe routine has to do several things: 747 * - drive output discovery via intel_display_driver_probe() 748 * - initialize the memory manager 749 * - allocate initial config memory 750 * - setup the DRM framebuffer with the allocated memory 751 */ 752 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 753 { 754 struct drm_i915_private *i915; 755 int ret; 756 757 ret = pci_enable_device(pdev); 758 if (ret) { 759 pr_err("Failed to enable graphics device: %pe\n", ERR_PTR(ret)); 760 return ret; 761 } 762 763 i915 = i915_driver_create(pdev, ent); 764 if (IS_ERR(i915)) { 765 pci_disable_device(pdev); 766 return PTR_ERR(i915); 767 } 768 769 ret = i915_driver_early_probe(i915); 770 if (ret < 0) 771 goto out_pci_disable; 772 773 disable_rpm_wakeref_asserts(&i915->runtime_pm); 774 775 intel_vgpu_detect(i915); 776 777 ret = intel_gt_probe_all(i915); 778 if (ret < 0) 779 goto out_runtime_pm_put; 780 781 ret = i915_driver_mmio_probe(i915); 782 if (ret < 0) 783 goto out_runtime_pm_put; 784 785 ret = i915_driver_hw_probe(i915); 786 if (ret < 0) 787 goto out_cleanup_mmio; 788 789 ret = intel_display_driver_probe_noirq(i915); 790 if (ret < 0) 791 goto out_cleanup_hw; 792 793 ret = intel_irq_install(i915); 794 if (ret) 795 goto out_cleanup_modeset; 796 797 ret = intel_display_driver_probe_nogem(i915); 798 if (ret) 799 goto out_cleanup_irq; 800 801 ret = i915_gem_init(i915); 802 if (ret) 803 goto out_cleanup_modeset2; 804 805 ret = intel_pxp_init(i915); 806 if (ret && ret != -ENODEV) 807 drm_dbg(&i915->drm, "pxp init failed with %d\n", ret); 808 809 ret = intel_display_driver_probe(i915); 810 if (ret) 811 goto out_cleanup_gem; 812 813 i915_driver_register(i915); 814 815 enable_rpm_wakeref_asserts(&i915->runtime_pm); 816 817 i915_welcome_messages(i915); 818 819 i915->do_release = true; 820 821 return 0; 822 823 out_cleanup_gem: 824 i915_gem_suspend(i915); 825 i915_gem_driver_remove(i915); 826 i915_gem_driver_release(i915); 827 out_cleanup_modeset2: 828 /* FIXME clean up the error path */ 829 intel_display_driver_remove(i915); 830 intel_irq_uninstall(i915); 831 intel_display_driver_remove_noirq(i915); 832 goto out_cleanup_modeset; 833 out_cleanup_irq: 834 intel_irq_uninstall(i915); 835 out_cleanup_modeset: 836 intel_display_driver_remove_nogem(i915); 837 out_cleanup_hw: 838 i915_driver_hw_remove(i915); 839 intel_memory_regions_driver_release(i915); 840 i915_ggtt_driver_release(i915); 841 i915_gem_drain_freed_objects(i915); 842 i915_ggtt_driver_late_release(i915); 843 out_cleanup_mmio: 844 i915_driver_mmio_release(i915); 845 out_runtime_pm_put: 846 enable_rpm_wakeref_asserts(&i915->runtime_pm); 847 i915_driver_late_release(i915); 848 out_pci_disable: 849 pci_disable_device(pdev); 850 i915_probe_error(i915, "Device initialization failed (%d)\n", ret); 851 return ret; 852 } 853 854 void i915_driver_remove(struct drm_i915_private *i915) 855 { 856 intel_wakeref_t wakeref; 857 858 wakeref = intel_runtime_pm_get(&i915->runtime_pm); 859 860 i915_driver_unregister(i915); 861 862 /* Flush any external code that still may be under the RCU lock */ 863 synchronize_rcu(); 864 865 i915_gem_suspend(i915); 866 867 intel_gvt_driver_remove(i915); 868 869 intel_display_driver_remove(i915); 870 871 intel_irq_uninstall(i915); 872 873 intel_display_driver_remove_noirq(i915); 874 875 i915_reset_error_state(i915); 876 i915_gem_driver_remove(i915); 877 878 intel_display_driver_remove_nogem(i915); 879 880 i915_driver_hw_remove(i915); 881 882 intel_runtime_pm_put(&i915->runtime_pm, wakeref); 883 } 884 885 static void i915_driver_release(struct drm_device *dev) 886 { 887 struct drm_i915_private *dev_priv = to_i915(dev); 888 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 889 intel_wakeref_t wakeref; 890 891 if (!dev_priv->do_release) 892 return; 893 894 wakeref = intel_runtime_pm_get(rpm); 895 896 i915_gem_driver_release(dev_priv); 897 898 intel_memory_regions_driver_release(dev_priv); 899 i915_ggtt_driver_release(dev_priv); 900 i915_gem_drain_freed_objects(dev_priv); 901 i915_ggtt_driver_late_release(dev_priv); 902 903 i915_driver_mmio_release(dev_priv); 904 905 intel_runtime_pm_put(rpm, wakeref); 906 907 intel_runtime_pm_driver_release(rpm); 908 909 i915_driver_late_release(dev_priv); 910 911 intel_display_device_remove(dev_priv); 912 } 913 914 static int i915_driver_open(struct drm_device *dev, struct drm_file *file) 915 { 916 struct drm_i915_private *i915 = to_i915(dev); 917 int ret; 918 919 ret = i915_gem_open(i915, file); 920 if (ret) 921 return ret; 922 923 return 0; 924 } 925 926 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file) 927 { 928 struct drm_i915_file_private *file_priv = file->driver_priv; 929 930 i915_gem_context_close(file); 931 i915_drm_client_put(file_priv->client); 932 933 kfree_rcu(file_priv, rcu); 934 935 /* Catch up with all the deferred frees from "this" client */ 936 i915_gem_flush_free_objects(to_i915(dev)); 937 } 938 939 void i915_driver_shutdown(struct drm_i915_private *i915) 940 { 941 disable_rpm_wakeref_asserts(&i915->runtime_pm); 942 intel_runtime_pm_disable(&i915->runtime_pm); 943 intel_power_domains_disable(i915); 944 945 intel_fbdev_set_suspend(&i915->drm, FBINFO_STATE_SUSPENDED, true); 946 if (HAS_DISPLAY(i915)) { 947 drm_kms_helper_poll_disable(&i915->drm); 948 intel_display_driver_disable_user_access(i915); 949 950 drm_atomic_helper_shutdown(&i915->drm); 951 } 952 953 intel_dp_mst_suspend(i915); 954 955 intel_runtime_pm_disable_interrupts(i915); 956 intel_hpd_cancel_work(i915); 957 958 if (HAS_DISPLAY(i915)) 959 intel_display_driver_suspend_access(i915); 960 961 intel_encoder_suspend_all(&i915->display); 962 intel_encoder_shutdown_all(&i915->display); 963 964 intel_dmc_suspend(i915); 965 966 i915_gem_suspend(i915); 967 968 /* 969 * The only requirement is to reboot with display DC states disabled, 970 * for now leaving all display power wells in the INIT power domain 971 * enabled. 972 * 973 * TODO: 974 * - unify the pci_driver::shutdown sequence here with the 975 * pci_driver.driver.pm.poweroff,poweroff_late sequence. 976 * - unify the driver remove and system/runtime suspend sequences with 977 * the above unified shutdown/poweroff sequence. 978 */ 979 intel_power_domains_driver_remove(i915); 980 enable_rpm_wakeref_asserts(&i915->runtime_pm); 981 982 intel_runtime_pm_driver_last_release(&i915->runtime_pm); 983 } 984 985 static bool suspend_to_idle(struct drm_i915_private *dev_priv) 986 { 987 #if IS_ENABLED(CONFIG_ACPI_SLEEP) 988 if (acpi_target_system_state() < ACPI_STATE_S3) 989 return true; 990 #endif 991 return false; 992 } 993 994 static void i915_drm_complete(struct drm_device *dev) 995 { 996 struct drm_i915_private *i915 = to_i915(dev); 997 998 intel_pxp_resume_complete(i915->pxp); 999 } 1000 1001 static int i915_drm_prepare(struct drm_device *dev) 1002 { 1003 struct drm_i915_private *i915 = to_i915(dev); 1004 1005 intel_pxp_suspend_prepare(i915->pxp); 1006 1007 /* 1008 * NB intel_display_driver_suspend() may issue new requests after we've 1009 * ostensibly marked the GPU as ready-to-sleep here. We need to 1010 * split out that work and pull it forward so that after point, 1011 * the GPU is not woken again. 1012 */ 1013 return i915_gem_backup_suspend(i915); 1014 } 1015 1016 static int i915_drm_suspend(struct drm_device *dev) 1017 { 1018 struct drm_i915_private *dev_priv = to_i915(dev); 1019 struct intel_display *display = &dev_priv->display; 1020 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 1021 pci_power_t opregion_target_state; 1022 1023 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1024 1025 /* We do a lot of poking in a lot of registers, make sure they work 1026 * properly. */ 1027 intel_power_domains_disable(dev_priv); 1028 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true); 1029 if (HAS_DISPLAY(dev_priv)) { 1030 drm_kms_helper_poll_disable(dev); 1031 intel_display_driver_disable_user_access(dev_priv); 1032 } 1033 1034 pci_save_state(pdev); 1035 1036 intel_display_driver_suspend(dev_priv); 1037 1038 intel_dp_mst_suspend(dev_priv); 1039 1040 intel_runtime_pm_disable_interrupts(dev_priv); 1041 intel_hpd_cancel_work(dev_priv); 1042 1043 if (HAS_DISPLAY(dev_priv)) 1044 intel_display_driver_suspend_access(dev_priv); 1045 1046 intel_encoder_suspend_all(&dev_priv->display); 1047 1048 /* Must be called before GGTT is suspended. */ 1049 intel_dpt_suspend(dev_priv); 1050 i915_ggtt_suspend(to_gt(dev_priv)->ggtt); 1051 1052 i915_save_display(dev_priv); 1053 1054 opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold; 1055 intel_opregion_suspend(display, opregion_target_state); 1056 1057 dev_priv->suspend_count++; 1058 1059 intel_dmc_suspend(dev_priv); 1060 1061 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1062 1063 i915_gem_drain_freed_objects(dev_priv); 1064 1065 return 0; 1066 } 1067 1068 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation) 1069 { 1070 struct drm_i915_private *dev_priv = to_i915(dev); 1071 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 1072 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 1073 struct intel_gt *gt; 1074 int ret, i; 1075 bool s2idle = !hibernation && suspend_to_idle(dev_priv); 1076 1077 disable_rpm_wakeref_asserts(rpm); 1078 1079 intel_pxp_suspend(dev_priv->pxp); 1080 1081 i915_gem_suspend_late(dev_priv); 1082 1083 for_each_gt(gt, dev_priv, i) 1084 intel_uncore_suspend(gt->uncore); 1085 1086 intel_power_domains_suspend(dev_priv, s2idle); 1087 1088 intel_display_power_suspend_late(dev_priv); 1089 1090 ret = vlv_suspend_complete(dev_priv); 1091 if (ret) { 1092 drm_err(&dev_priv->drm, "Suspend complete failed: %d\n", ret); 1093 intel_power_domains_resume(dev_priv); 1094 1095 goto out; 1096 } 1097 1098 pci_disable_device(pdev); 1099 /* 1100 * During hibernation on some platforms the BIOS may try to access 1101 * the device even though it's already in D3 and hang the machine. So 1102 * leave the device in D0 on those platforms and hope the BIOS will 1103 * power down the device properly. The issue was seen on multiple old 1104 * GENs with different BIOS vendors, so having an explicit blacklist 1105 * is inpractical; apply the workaround on everything pre GEN6. The 1106 * platforms where the issue was seen: 1107 * Lenovo Thinkpad X301, X61s, X60, T60, X41 1108 * Fujitsu FSC S7110 1109 * Acer Aspire 1830T 1110 */ 1111 if (!(hibernation && GRAPHICS_VER(dev_priv) < 6)) 1112 pci_set_power_state(pdev, PCI_D3hot); 1113 1114 out: 1115 enable_rpm_wakeref_asserts(rpm); 1116 if (!dev_priv->uncore.user_forcewake_count) 1117 intel_runtime_pm_driver_release(rpm); 1118 1119 return ret; 1120 } 1121 1122 int i915_driver_suspend_switcheroo(struct drm_i915_private *i915, 1123 pm_message_t state) 1124 { 1125 int error; 1126 1127 if (drm_WARN_ON_ONCE(&i915->drm, state.event != PM_EVENT_SUSPEND && 1128 state.event != PM_EVENT_FREEZE)) 1129 return -EINVAL; 1130 1131 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1132 return 0; 1133 1134 error = i915_drm_suspend(&i915->drm); 1135 if (error) 1136 return error; 1137 1138 return i915_drm_suspend_late(&i915->drm, false); 1139 } 1140 1141 static int i915_drm_resume(struct drm_device *dev) 1142 { 1143 struct drm_i915_private *dev_priv = to_i915(dev); 1144 struct intel_display *display = &dev_priv->display; 1145 struct intel_gt *gt; 1146 int ret, i; 1147 1148 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1149 1150 ret = i915_pcode_init(dev_priv); 1151 if (ret) 1152 return ret; 1153 1154 sanitize_gpu(dev_priv); 1155 1156 ret = i915_ggtt_enable_hw(dev_priv); 1157 if (ret) 1158 drm_err(&dev_priv->drm, "failed to re-enable GGTT\n"); 1159 1160 i915_ggtt_resume(to_gt(dev_priv)->ggtt); 1161 1162 for_each_gt(gt, dev_priv, i) 1163 if (GRAPHICS_VER(gt->i915) >= 8) 1164 setup_private_pat(gt); 1165 1166 /* Must be called after GGTT is resumed. */ 1167 intel_dpt_resume(dev_priv); 1168 1169 intel_dmc_resume(dev_priv); 1170 1171 i915_restore_display(dev_priv); 1172 intel_pps_unlock_regs_wa(dev_priv); 1173 1174 intel_init_pch_refclk(dev_priv); 1175 1176 /* 1177 * Interrupts have to be enabled before any batches are run. If not the 1178 * GPU will hang. i915_gem_init_hw() will initiate batches to 1179 * update/restore the context. 1180 * 1181 * drm_mode_config_reset() needs AUX interrupts. 1182 * 1183 * Modeset enabling in intel_display_driver_init_hw() also needs working 1184 * interrupts. 1185 */ 1186 intel_runtime_pm_enable_interrupts(dev_priv); 1187 1188 if (HAS_DISPLAY(dev_priv)) 1189 drm_mode_config_reset(dev); 1190 1191 i915_gem_resume(dev_priv); 1192 1193 intel_display_driver_init_hw(dev_priv); 1194 1195 intel_clock_gating_init(dev_priv); 1196 1197 if (HAS_DISPLAY(dev_priv)) 1198 intel_display_driver_resume_access(dev_priv); 1199 1200 intel_hpd_init(dev_priv); 1201 1202 /* MST sideband requires HPD interrupts enabled */ 1203 intel_dp_mst_resume(dev_priv); 1204 intel_display_driver_resume(dev_priv); 1205 1206 if (HAS_DISPLAY(dev_priv)) { 1207 intel_display_driver_enable_user_access(dev_priv); 1208 drm_kms_helper_poll_enable(dev); 1209 } 1210 intel_hpd_poll_disable(dev_priv); 1211 1212 intel_opregion_resume(display); 1213 1214 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false); 1215 1216 intel_power_domains_enable(dev_priv); 1217 1218 intel_gvt_resume(dev_priv); 1219 1220 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1221 1222 return 0; 1223 } 1224 1225 static int i915_drm_resume_early(struct drm_device *dev) 1226 { 1227 struct drm_i915_private *dev_priv = to_i915(dev); 1228 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 1229 struct intel_gt *gt; 1230 int ret, i; 1231 1232 /* 1233 * We have a resume ordering issue with the snd-hda driver also 1234 * requiring our device to be power up. Due to the lack of a 1235 * parent/child relationship we currently solve this with an early 1236 * resume hook. 1237 * 1238 * FIXME: This should be solved with a special hdmi sink device or 1239 * similar so that power domains can be employed. 1240 */ 1241 1242 /* 1243 * Note that we need to set the power state explicitly, since we 1244 * powered off the device during freeze and the PCI core won't power 1245 * it back up for us during thaw. Powering off the device during 1246 * freeze is not a hard requirement though, and during the 1247 * suspend/resume phases the PCI core makes sure we get here with the 1248 * device powered on. So in case we change our freeze logic and keep 1249 * the device powered we can also remove the following set power state 1250 * call. 1251 */ 1252 ret = pci_set_power_state(pdev, PCI_D0); 1253 if (ret) { 1254 drm_err(&dev_priv->drm, 1255 "failed to set PCI D0 power state (%d)\n", ret); 1256 return ret; 1257 } 1258 1259 /* 1260 * Note that pci_enable_device() first enables any parent bridge 1261 * device and only then sets the power state for this device. The 1262 * bridge enabling is a nop though, since bridge devices are resumed 1263 * first. The order of enabling power and enabling the device is 1264 * imposed by the PCI core as described above, so here we preserve the 1265 * same order for the freeze/thaw phases. 1266 * 1267 * TODO: eventually we should remove pci_disable_device() / 1268 * pci_enable_enable_device() from suspend/resume. Due to how they 1269 * depend on the device enable refcount we can't anyway depend on them 1270 * disabling/enabling the device. 1271 */ 1272 if (pci_enable_device(pdev)) 1273 return -EIO; 1274 1275 pci_set_master(pdev); 1276 1277 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1278 1279 ret = vlv_resume_prepare(dev_priv, false); 1280 if (ret) 1281 drm_err(&dev_priv->drm, 1282 "Resume prepare failed: %d, continuing anyway\n", ret); 1283 1284 for_each_gt(gt, dev_priv, i) 1285 intel_gt_resume_early(gt); 1286 1287 intel_display_power_resume_early(dev_priv); 1288 1289 intel_power_domains_resume(dev_priv); 1290 1291 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1292 1293 return ret; 1294 } 1295 1296 int i915_driver_resume_switcheroo(struct drm_i915_private *i915) 1297 { 1298 int ret; 1299 1300 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1301 return 0; 1302 1303 ret = i915_drm_resume_early(&i915->drm); 1304 if (ret) 1305 return ret; 1306 1307 return i915_drm_resume(&i915->drm); 1308 } 1309 1310 static int i915_pm_prepare(struct device *kdev) 1311 { 1312 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1313 1314 if (!i915) { 1315 dev_err(kdev, "DRM not initialized, aborting suspend.\n"); 1316 return -ENODEV; 1317 } 1318 1319 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1320 return 0; 1321 1322 return i915_drm_prepare(&i915->drm); 1323 } 1324 1325 static int i915_pm_suspend(struct device *kdev) 1326 { 1327 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1328 1329 if (!i915) { 1330 dev_err(kdev, "DRM not initialized, aborting suspend.\n"); 1331 return -ENODEV; 1332 } 1333 1334 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1335 return 0; 1336 1337 return i915_drm_suspend(&i915->drm); 1338 } 1339 1340 static int i915_pm_suspend_late(struct device *kdev) 1341 { 1342 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1343 1344 /* 1345 * We have a suspend ordering issue with the snd-hda driver also 1346 * requiring our device to be power up. Due to the lack of a 1347 * parent/child relationship we currently solve this with an late 1348 * suspend hook. 1349 * 1350 * FIXME: This should be solved with a special hdmi sink device or 1351 * similar so that power domains can be employed. 1352 */ 1353 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1354 return 0; 1355 1356 return i915_drm_suspend_late(&i915->drm, false); 1357 } 1358 1359 static int i915_pm_poweroff_late(struct device *kdev) 1360 { 1361 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1362 1363 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1364 return 0; 1365 1366 return i915_drm_suspend_late(&i915->drm, true); 1367 } 1368 1369 static int i915_pm_resume_early(struct device *kdev) 1370 { 1371 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1372 1373 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1374 return 0; 1375 1376 return i915_drm_resume_early(&i915->drm); 1377 } 1378 1379 static int i915_pm_resume(struct device *kdev) 1380 { 1381 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1382 1383 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1384 return 0; 1385 1386 return i915_drm_resume(&i915->drm); 1387 } 1388 1389 static void i915_pm_complete(struct device *kdev) 1390 { 1391 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1392 1393 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1394 return; 1395 1396 i915_drm_complete(&i915->drm); 1397 } 1398 1399 /* freeze: before creating the hibernation_image */ 1400 static int i915_pm_freeze(struct device *kdev) 1401 { 1402 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1403 int ret; 1404 1405 if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) { 1406 ret = i915_drm_suspend(&i915->drm); 1407 if (ret) 1408 return ret; 1409 } 1410 1411 ret = i915_gem_freeze(i915); 1412 if (ret) 1413 return ret; 1414 1415 return 0; 1416 } 1417 1418 static int i915_pm_freeze_late(struct device *kdev) 1419 { 1420 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1421 int ret; 1422 1423 if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) { 1424 ret = i915_drm_suspend_late(&i915->drm, true); 1425 if (ret) 1426 return ret; 1427 } 1428 1429 ret = i915_gem_freeze_late(i915); 1430 if (ret) 1431 return ret; 1432 1433 return 0; 1434 } 1435 1436 /* thaw: called after creating the hibernation image, but before turning off. */ 1437 static int i915_pm_thaw_early(struct device *kdev) 1438 { 1439 return i915_pm_resume_early(kdev); 1440 } 1441 1442 static int i915_pm_thaw(struct device *kdev) 1443 { 1444 return i915_pm_resume(kdev); 1445 } 1446 1447 /* restore: called after loading the hibernation image. */ 1448 static int i915_pm_restore_early(struct device *kdev) 1449 { 1450 return i915_pm_resume_early(kdev); 1451 } 1452 1453 static int i915_pm_restore(struct device *kdev) 1454 { 1455 return i915_pm_resume(kdev); 1456 } 1457 1458 static int intel_runtime_suspend(struct device *kdev) 1459 { 1460 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 1461 struct intel_display *display = &dev_priv->display; 1462 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 1463 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 1464 struct pci_dev *root_pdev; 1465 struct intel_gt *gt; 1466 int ret, i; 1467 1468 if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv))) 1469 return -ENODEV; 1470 1471 drm_dbg(&dev_priv->drm, "Suspending device\n"); 1472 1473 disable_rpm_wakeref_asserts(rpm); 1474 1475 /* 1476 * We are safe here against re-faults, since the fault handler takes 1477 * an RPM reference. 1478 */ 1479 i915_gem_runtime_suspend(dev_priv); 1480 1481 intel_pxp_runtime_suspend(dev_priv->pxp); 1482 1483 for_each_gt(gt, dev_priv, i) 1484 intel_gt_runtime_suspend(gt); 1485 1486 intel_runtime_pm_disable_interrupts(dev_priv); 1487 1488 for_each_gt(gt, dev_priv, i) 1489 intel_uncore_suspend(gt->uncore); 1490 1491 intel_display_power_suspend(dev_priv); 1492 1493 ret = vlv_suspend_complete(dev_priv); 1494 if (ret) { 1495 drm_err(&dev_priv->drm, 1496 "Runtime suspend failed, disabling it (%d)\n", ret); 1497 intel_uncore_runtime_resume(&dev_priv->uncore); 1498 1499 intel_runtime_pm_enable_interrupts(dev_priv); 1500 1501 for_each_gt(gt, dev_priv, i) 1502 intel_gt_runtime_resume(gt); 1503 1504 enable_rpm_wakeref_asserts(rpm); 1505 1506 return ret; 1507 } 1508 1509 enable_rpm_wakeref_asserts(rpm); 1510 intel_runtime_pm_driver_release(rpm); 1511 1512 if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore)) 1513 drm_err(&dev_priv->drm, 1514 "Unclaimed access detected prior to suspending\n"); 1515 1516 /* 1517 * FIXME: Temporary hammer to avoid freezing the machine on our DGFX 1518 * This should be totally removed when we handle the pci states properly 1519 * on runtime PM. 1520 */ 1521 root_pdev = pcie_find_root_port(pdev); 1522 if (root_pdev) 1523 pci_d3cold_disable(root_pdev); 1524 1525 /* 1526 * FIXME: We really should find a document that references the arguments 1527 * used below! 1528 */ 1529 if (IS_BROADWELL(dev_priv)) { 1530 /* 1531 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop 1532 * being detected, and the call we do at intel_runtime_resume() 1533 * won't be able to restore them. Since PCI_D3hot matches the 1534 * actual specification and appears to be working, use it. 1535 */ 1536 intel_opregion_notify_adapter(display, PCI_D3hot); 1537 } else { 1538 /* 1539 * current versions of firmware which depend on this opregion 1540 * notification have repurposed the D1 definition to mean 1541 * "runtime suspended" vs. what you would normally expect (D3) 1542 * to distinguish it from notifications that might be sent via 1543 * the suspend path. 1544 */ 1545 intel_opregion_notify_adapter(display, PCI_D1); 1546 } 1547 1548 assert_forcewakes_inactive(&dev_priv->uncore); 1549 1550 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) 1551 intel_hpd_poll_enable(dev_priv); 1552 1553 drm_dbg(&dev_priv->drm, "Device suspended\n"); 1554 return 0; 1555 } 1556 1557 static int intel_runtime_resume(struct device *kdev) 1558 { 1559 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 1560 struct intel_display *display = &dev_priv->display; 1561 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 1562 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 1563 struct pci_dev *root_pdev; 1564 struct intel_gt *gt; 1565 int ret, i; 1566 1567 if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv))) 1568 return -ENODEV; 1569 1570 drm_dbg(&dev_priv->drm, "Resuming device\n"); 1571 1572 drm_WARN_ON_ONCE(&dev_priv->drm, atomic_read(&rpm->wakeref_count)); 1573 disable_rpm_wakeref_asserts(rpm); 1574 1575 intel_opregion_notify_adapter(display, PCI_D0); 1576 1577 root_pdev = pcie_find_root_port(pdev); 1578 if (root_pdev) 1579 pci_d3cold_enable(root_pdev); 1580 1581 if (intel_uncore_unclaimed_mmio(&dev_priv->uncore)) 1582 drm_dbg(&dev_priv->drm, 1583 "Unclaimed access during suspend, bios?\n"); 1584 1585 intel_display_power_resume(dev_priv); 1586 1587 ret = vlv_resume_prepare(dev_priv, true); 1588 1589 for_each_gt(gt, dev_priv, i) 1590 intel_uncore_runtime_resume(gt->uncore); 1591 1592 intel_runtime_pm_enable_interrupts(dev_priv); 1593 1594 /* 1595 * No point of rolling back things in case of an error, as the best 1596 * we can do is to hope that things will still work (and disable RPM). 1597 */ 1598 for_each_gt(gt, dev_priv, i) 1599 intel_gt_runtime_resume(gt); 1600 1601 intel_pxp_runtime_resume(dev_priv->pxp); 1602 1603 /* 1604 * On VLV/CHV display interrupts are part of the display 1605 * power well, so hpd is reinitialized from there. For 1606 * everyone else do it here. 1607 */ 1608 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { 1609 intel_hpd_init(dev_priv); 1610 intel_hpd_poll_disable(dev_priv); 1611 } 1612 1613 skl_watermark_ipc_update(dev_priv); 1614 1615 enable_rpm_wakeref_asserts(rpm); 1616 1617 if (ret) 1618 drm_err(&dev_priv->drm, 1619 "Runtime resume failed, disabling it (%d)\n", ret); 1620 else 1621 drm_dbg(&dev_priv->drm, "Device resumed\n"); 1622 1623 return ret; 1624 } 1625 1626 const struct dev_pm_ops i915_pm_ops = { 1627 /* 1628 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND, 1629 * PMSG_RESUME] 1630 */ 1631 .prepare = i915_pm_prepare, 1632 .suspend = i915_pm_suspend, 1633 .suspend_late = i915_pm_suspend_late, 1634 .resume_early = i915_pm_resume_early, 1635 .resume = i915_pm_resume, 1636 .complete = i915_pm_complete, 1637 1638 /* 1639 * S4 event handlers 1640 * @freeze, @freeze_late : called (1) before creating the 1641 * hibernation image [PMSG_FREEZE] and 1642 * (2) after rebooting, before restoring 1643 * the image [PMSG_QUIESCE] 1644 * @thaw, @thaw_early : called (1) after creating the hibernation 1645 * image, before writing it [PMSG_THAW] 1646 * and (2) after failing to create or 1647 * restore the image [PMSG_RECOVER] 1648 * @poweroff, @poweroff_late: called after writing the hibernation 1649 * image, before rebooting [PMSG_HIBERNATE] 1650 * @restore, @restore_early : called after rebooting and restoring the 1651 * hibernation image [PMSG_RESTORE] 1652 */ 1653 .freeze = i915_pm_freeze, 1654 .freeze_late = i915_pm_freeze_late, 1655 .thaw_early = i915_pm_thaw_early, 1656 .thaw = i915_pm_thaw, 1657 .poweroff = i915_pm_suspend, 1658 .poweroff_late = i915_pm_poweroff_late, 1659 .restore_early = i915_pm_restore_early, 1660 .restore = i915_pm_restore, 1661 1662 /* S0ix (via runtime suspend) event handlers */ 1663 .runtime_suspend = intel_runtime_suspend, 1664 .runtime_resume = intel_runtime_resume, 1665 }; 1666 1667 static const struct file_operations i915_driver_fops = { 1668 .owner = THIS_MODULE, 1669 .open = drm_open, 1670 .release = drm_release_noglobal, 1671 .unlocked_ioctl = drm_ioctl, 1672 .mmap = i915_gem_mmap, 1673 .poll = drm_poll, 1674 .read = drm_read, 1675 .compat_ioctl = i915_ioc32_compat_ioctl, 1676 .llseek = noop_llseek, 1677 #ifdef CONFIG_PROC_FS 1678 .show_fdinfo = drm_show_fdinfo, 1679 #endif 1680 }; 1681 1682 static int 1683 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data, 1684 struct drm_file *file) 1685 { 1686 return -ENODEV; 1687 } 1688 1689 static const struct drm_ioctl_desc i915_ioctls[] = { 1690 DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1691 DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH), 1692 DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH), 1693 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH), 1694 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH), 1695 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH), 1696 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_RENDER_ALLOW), 1697 DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1698 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH), 1699 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH), 1700 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1701 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH), 1702 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1703 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1704 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH), 1705 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH), 1706 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1707 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1708 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, drm_invalid_op, DRM_AUTH), 1709 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_RENDER_ALLOW), 1710 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), 1711 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), 1712 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_RENDER_ALLOW), 1713 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW), 1714 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW), 1715 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW), 1716 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1717 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1718 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW), 1719 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE_EXT, i915_gem_create_ext_ioctl, DRM_RENDER_ALLOW), 1720 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW), 1721 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW), 1722 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW), 1723 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_OFFSET, i915_gem_mmap_offset_ioctl, DRM_RENDER_ALLOW), 1724 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW), 1725 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW), 1726 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW), 1727 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW), 1728 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW), 1729 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0), 1730 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW), 1731 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER), 1732 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER), 1733 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER), 1734 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER), 1735 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_RENDER_ALLOW), 1736 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE_EXT, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW), 1737 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW), 1738 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW), 1739 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW), 1740 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW), 1741 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW), 1742 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW), 1743 DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW), 1744 DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_RENDER_ALLOW), 1745 DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_RENDER_ALLOW), 1746 DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_RENDER_ALLOW), 1747 DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE, i915_gem_vm_create_ioctl, DRM_RENDER_ALLOW), 1748 DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY, i915_gem_vm_destroy_ioctl, DRM_RENDER_ALLOW), 1749 }; 1750 1751 /* 1752 * Interface history: 1753 * 1754 * 1.1: Original. 1755 * 1.2: Add Power Management 1756 * 1.3: Add vblank support 1757 * 1.4: Fix cmdbuffer path, add heap destroy 1758 * 1.5: Add vblank pipe configuration 1759 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank 1760 * - Support vertical blank on secondary display pipe 1761 */ 1762 #define DRIVER_MAJOR 1 1763 #define DRIVER_MINOR 6 1764 #define DRIVER_PATCHLEVEL 0 1765 1766 static const struct drm_driver i915_drm_driver = { 1767 /* Don't use MTRRs here; the Xserver or userspace app should 1768 * deal with them for Intel hardware. 1769 */ 1770 .driver_features = 1771 DRIVER_GEM | 1772 DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ | 1773 DRIVER_SYNCOBJ_TIMELINE, 1774 .release = i915_driver_release, 1775 .open = i915_driver_open, 1776 .postclose = i915_driver_postclose, 1777 .show_fdinfo = PTR_IF(IS_ENABLED(CONFIG_PROC_FS), i915_drm_client_fdinfo), 1778 1779 .gem_prime_import = i915_gem_prime_import, 1780 1781 .dumb_create = i915_gem_dumb_create, 1782 .dumb_map_offset = i915_gem_dumb_mmap_offset, 1783 1784 .ioctls = i915_ioctls, 1785 .num_ioctls = ARRAY_SIZE(i915_ioctls), 1786 .fops = &i915_driver_fops, 1787 .name = DRIVER_NAME, 1788 .desc = DRIVER_DESC, 1789 .date = DRIVER_DATE, 1790 .major = DRIVER_MAJOR, 1791 .minor = DRIVER_MINOR, 1792 .patchlevel = DRIVER_PATCHLEVEL, 1793 }; 1794