1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Support routines for initializing a PCI subsystem 4 * 5 * Extruded from code written by 6 * Dave Rusling (david.rusling@reo.mts.dec.com) 7 * David Mosberger (davidm@cs.arizona.edu) 8 * David Miller (davem@redhat.com) 9 * 10 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru> 11 * PCI-PCI bridges cleanup, sorted resource allocation. 12 * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru> 13 * Converted to allocation in 3 passes, which gives 14 * tighter packing. Prefetchable range support. 15 */ 16 17 #include <linux/bitops.h> 18 #include <linux/init.h> 19 #include <linux/kernel.h> 20 #include <linux/module.h> 21 #include <linux/pci.h> 22 #include <linux/errno.h> 23 #include <linux/ioport.h> 24 #include <linux/cache.h> 25 #include <linux/limits.h> 26 #include <linux/sizes.h> 27 #include <linux/slab.h> 28 #include <linux/acpi.h> 29 #include "pci.h" 30 31 unsigned int pci_flags; 32 EXPORT_SYMBOL_GPL(pci_flags); 33 34 struct pci_dev_resource { 35 struct list_head list; 36 struct resource *res; 37 struct pci_dev *dev; 38 resource_size_t start; 39 resource_size_t end; 40 resource_size_t add_size; 41 resource_size_t min_align; 42 unsigned long flags; 43 }; 44 45 static void free_list(struct list_head *head) 46 { 47 struct pci_dev_resource *dev_res, *tmp; 48 49 list_for_each_entry_safe(dev_res, tmp, head, list) { 50 list_del(&dev_res->list); 51 kfree(dev_res); 52 } 53 } 54 55 /** 56 * add_to_list() - Add a new resource tracker to the list 57 * @head: Head of the list 58 * @dev: Device to which the resource belongs 59 * @res: Resource to be tracked 60 * @add_size: Additional size to be optionally added to the resource 61 * @min_align: Minimum memory window alignment 62 */ 63 static int add_to_list(struct list_head *head, struct pci_dev *dev, 64 struct resource *res, resource_size_t add_size, 65 resource_size_t min_align) 66 { 67 struct pci_dev_resource *tmp; 68 69 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL); 70 if (!tmp) 71 return -ENOMEM; 72 73 tmp->res = res; 74 tmp->dev = dev; 75 tmp->start = res->start; 76 tmp->end = res->end; 77 tmp->flags = res->flags; 78 tmp->add_size = add_size; 79 tmp->min_align = min_align; 80 81 list_add(&tmp->list, head); 82 83 return 0; 84 } 85 86 static void remove_from_list(struct list_head *head, struct resource *res) 87 { 88 struct pci_dev_resource *dev_res, *tmp; 89 90 list_for_each_entry_safe(dev_res, tmp, head, list) { 91 if (dev_res->res == res) { 92 list_del(&dev_res->list); 93 kfree(dev_res); 94 break; 95 } 96 } 97 } 98 99 static struct pci_dev_resource *res_to_dev_res(struct list_head *head, 100 struct resource *res) 101 { 102 struct pci_dev_resource *dev_res; 103 104 list_for_each_entry(dev_res, head, list) { 105 if (dev_res->res == res) 106 return dev_res; 107 } 108 109 return NULL; 110 } 111 112 static resource_size_t get_res_add_size(struct list_head *head, 113 struct resource *res) 114 { 115 struct pci_dev_resource *dev_res; 116 117 dev_res = res_to_dev_res(head, res); 118 return dev_res ? dev_res->add_size : 0; 119 } 120 121 static resource_size_t get_res_add_align(struct list_head *head, 122 struct resource *res) 123 { 124 struct pci_dev_resource *dev_res; 125 126 dev_res = res_to_dev_res(head, res); 127 return dev_res ? dev_res->min_align : 0; 128 } 129 130 /* Sort resources by alignment */ 131 static void pdev_sort_resources(struct pci_dev *dev, struct list_head *head) 132 { 133 struct resource *r; 134 int i; 135 136 pci_dev_for_each_resource(dev, r, i) { 137 struct pci_dev_resource *dev_res, *tmp; 138 resource_size_t r_align; 139 struct list_head *n; 140 141 if (r->flags & IORESOURCE_PCI_FIXED) 142 continue; 143 144 if (!(r->flags) || r->parent) 145 continue; 146 147 r_align = pci_resource_alignment(dev, r); 148 if (!r_align) { 149 pci_warn(dev, "BAR %d: %pR has bogus alignment\n", 150 i, r); 151 continue; 152 } 153 154 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL); 155 if (!tmp) 156 panic("%s: kzalloc() failed!\n", __func__); 157 tmp->res = r; 158 tmp->dev = dev; 159 160 /* Fallback is smallest one or list is empty */ 161 n = head; 162 list_for_each_entry(dev_res, head, list) { 163 resource_size_t align; 164 165 align = pci_resource_alignment(dev_res->dev, 166 dev_res->res); 167 168 if (r_align > align) { 169 n = &dev_res->list; 170 break; 171 } 172 } 173 /* Insert it just before n */ 174 list_add_tail(&tmp->list, n); 175 } 176 } 177 178 static void __dev_sort_resources(struct pci_dev *dev, struct list_head *head) 179 { 180 u16 class = dev->class >> 8; 181 182 /* Don't touch classless devices or host bridges or IOAPICs */ 183 if (class == PCI_CLASS_NOT_DEFINED || class == PCI_CLASS_BRIDGE_HOST) 184 return; 185 186 /* Don't touch IOAPIC devices already enabled by firmware */ 187 if (class == PCI_CLASS_SYSTEM_PIC) { 188 u16 command; 189 pci_read_config_word(dev, PCI_COMMAND, &command); 190 if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) 191 return; 192 } 193 194 pdev_sort_resources(dev, head); 195 } 196 197 static inline void reset_resource(struct resource *res) 198 { 199 res->start = 0; 200 res->end = 0; 201 res->flags = 0; 202 } 203 204 /** 205 * reassign_resources_sorted() - Satisfy any additional resource requests 206 * 207 * @realloc_head: Head of the list tracking requests requiring 208 * additional resources 209 * @head: Head of the list tracking requests with allocated 210 * resources 211 * 212 * Walk through each element of the realloc_head and try to procure additional 213 * resources for the element, provided the element is in the head list. 214 */ 215 static void reassign_resources_sorted(struct list_head *realloc_head, 216 struct list_head *head) 217 { 218 struct resource *res; 219 const char *res_name; 220 struct pci_dev_resource *add_res, *tmp; 221 struct pci_dev_resource *dev_res; 222 resource_size_t add_size, align; 223 int idx; 224 225 list_for_each_entry_safe(add_res, tmp, realloc_head, list) { 226 bool found_match = false; 227 228 res = add_res->res; 229 230 /* Skip resource that has been reset */ 231 if (!res->flags) 232 goto out; 233 234 /* Skip this resource if not found in head list */ 235 list_for_each_entry(dev_res, head, list) { 236 if (dev_res->res == res) { 237 found_match = true; 238 break; 239 } 240 } 241 if (!found_match) /* Just skip */ 242 continue; 243 244 idx = res - &add_res->dev->resource[0]; 245 res_name = pci_resource_name(add_res->dev, idx); 246 add_size = add_res->add_size; 247 align = add_res->min_align; 248 if (!resource_size(res)) { 249 res->start = align; 250 res->end = res->start + add_size - 1; 251 if (pci_assign_resource(add_res->dev, idx)) 252 reset_resource(res); 253 } else { 254 res->flags |= add_res->flags & 255 (IORESOURCE_STARTALIGN|IORESOURCE_SIZEALIGN); 256 if (pci_reassign_resource(add_res->dev, idx, 257 add_size, align)) 258 pci_info(add_res->dev, "%s %pR: failed to add %llx\n", 259 res_name, res, 260 (unsigned long long) add_size); 261 } 262 out: 263 list_del(&add_res->list); 264 kfree(add_res); 265 } 266 } 267 268 /** 269 * assign_requested_resources_sorted() - Satisfy resource requests 270 * 271 * @head: Head of the list tracking requests for resources 272 * @fail_head: Head of the list tracking requests that could not be 273 * allocated 274 * 275 * Satisfy resource requests of each element in the list. Add requests that 276 * could not be satisfied to the failed_list. 277 */ 278 static void assign_requested_resources_sorted(struct list_head *head, 279 struct list_head *fail_head) 280 { 281 struct resource *res; 282 struct pci_dev_resource *dev_res; 283 int idx; 284 285 list_for_each_entry(dev_res, head, list) { 286 res = dev_res->res; 287 idx = res - &dev_res->dev->resource[0]; 288 if (resource_size(res) && 289 pci_assign_resource(dev_res->dev, idx)) { 290 if (fail_head) { 291 /* 292 * If the failed resource is a ROM BAR and 293 * it will be enabled later, don't add it 294 * to the list. 295 */ 296 if (!((idx == PCI_ROM_RESOURCE) && 297 (!(res->flags & IORESOURCE_ROM_ENABLE)))) 298 add_to_list(fail_head, 299 dev_res->dev, res, 300 0 /* don't care */, 301 0 /* don't care */); 302 } 303 reset_resource(res); 304 } 305 } 306 } 307 308 static unsigned long pci_fail_res_type_mask(struct list_head *fail_head) 309 { 310 struct pci_dev_resource *fail_res; 311 unsigned long mask = 0; 312 313 /* Check failed type */ 314 list_for_each_entry(fail_res, fail_head, list) 315 mask |= fail_res->flags; 316 317 /* 318 * One pref failed resource will set IORESOURCE_MEM, as we can 319 * allocate pref in non-pref range. Will release all assigned 320 * non-pref sibling resources according to that bit. 321 */ 322 return mask & (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH); 323 } 324 325 static bool pci_need_to_release(unsigned long mask, struct resource *res) 326 { 327 if (res->flags & IORESOURCE_IO) 328 return !!(mask & IORESOURCE_IO); 329 330 /* Check pref at first */ 331 if (res->flags & IORESOURCE_PREFETCH) { 332 if (mask & IORESOURCE_PREFETCH) 333 return true; 334 /* Count pref if its parent is non-pref */ 335 else if ((mask & IORESOURCE_MEM) && 336 !(res->parent->flags & IORESOURCE_PREFETCH)) 337 return true; 338 else 339 return false; 340 } 341 342 if (res->flags & IORESOURCE_MEM) 343 return !!(mask & IORESOURCE_MEM); 344 345 return false; /* Should not get here */ 346 } 347 348 static void __assign_resources_sorted(struct list_head *head, 349 struct list_head *realloc_head, 350 struct list_head *fail_head) 351 { 352 /* 353 * Should not assign requested resources at first. They could be 354 * adjacent, so later reassign can not reallocate them one by one in 355 * parent resource window. 356 * 357 * Try to assign requested + add_size at beginning. If could do that, 358 * could get out early. If could not do that, we still try to assign 359 * requested at first, then try to reassign add_size for some resources. 360 * 361 * Separate three resource type checking if we need to release 362 * assigned resource after requested + add_size try. 363 * 364 * 1. If IO port assignment fails, will release assigned IO 365 * port. 366 * 2. If pref MMIO assignment fails, release assigned pref 367 * MMIO. If assigned pref MMIO's parent is non-pref MMIO 368 * and non-pref MMIO assignment fails, will release that 369 * assigned pref MMIO. 370 * 3. If non-pref MMIO assignment fails or pref MMIO 371 * assignment fails, will release assigned non-pref MMIO. 372 */ 373 LIST_HEAD(save_head); 374 LIST_HEAD(local_fail_head); 375 struct pci_dev_resource *save_res; 376 struct pci_dev_resource *dev_res, *tmp_res, *dev_res2; 377 unsigned long fail_type; 378 resource_size_t add_align, align; 379 380 /* Check if optional add_size is there */ 381 if (!realloc_head || list_empty(realloc_head)) 382 goto requested_and_reassign; 383 384 /* Save original start, end, flags etc at first */ 385 list_for_each_entry(dev_res, head, list) { 386 if (add_to_list(&save_head, dev_res->dev, dev_res->res, 0, 0)) { 387 free_list(&save_head); 388 goto requested_and_reassign; 389 } 390 } 391 392 /* Update res in head list with add_size in realloc_head list */ 393 list_for_each_entry_safe(dev_res, tmp_res, head, list) { 394 dev_res->res->end += get_res_add_size(realloc_head, 395 dev_res->res); 396 397 /* 398 * There are two kinds of additional resources in the list: 399 * 1. bridge resource -- IORESOURCE_STARTALIGN 400 * 2. SR-IOV resource -- IORESOURCE_SIZEALIGN 401 * Here just fix the additional alignment for bridge 402 */ 403 if (!(dev_res->res->flags & IORESOURCE_STARTALIGN)) 404 continue; 405 406 add_align = get_res_add_align(realloc_head, dev_res->res); 407 408 /* 409 * The "head" list is sorted by alignment so resources with 410 * bigger alignment will be assigned first. After we 411 * change the alignment of a dev_res in "head" list, we 412 * need to reorder the list by alignment to make it 413 * consistent. 414 */ 415 if (add_align > dev_res->res->start) { 416 resource_size_t r_size = resource_size(dev_res->res); 417 418 dev_res->res->start = add_align; 419 dev_res->res->end = add_align + r_size - 1; 420 421 list_for_each_entry(dev_res2, head, list) { 422 align = pci_resource_alignment(dev_res2->dev, 423 dev_res2->res); 424 if (add_align > align) { 425 list_move_tail(&dev_res->list, 426 &dev_res2->list); 427 break; 428 } 429 } 430 } 431 432 } 433 434 /* Try updated head list with add_size added */ 435 assign_requested_resources_sorted(head, &local_fail_head); 436 437 /* All assigned with add_size? */ 438 if (list_empty(&local_fail_head)) { 439 /* Remove head list from realloc_head list */ 440 list_for_each_entry(dev_res, head, list) 441 remove_from_list(realloc_head, dev_res->res); 442 free_list(&save_head); 443 free_list(head); 444 return; 445 } 446 447 /* Check failed type */ 448 fail_type = pci_fail_res_type_mask(&local_fail_head); 449 /* Remove not need to be released assigned res from head list etc */ 450 list_for_each_entry_safe(dev_res, tmp_res, head, list) 451 if (dev_res->res->parent && 452 !pci_need_to_release(fail_type, dev_res->res)) { 453 /* Remove it from realloc_head list */ 454 remove_from_list(realloc_head, dev_res->res); 455 remove_from_list(&save_head, dev_res->res); 456 list_del(&dev_res->list); 457 kfree(dev_res); 458 } 459 460 free_list(&local_fail_head); 461 /* Release assigned resource */ 462 list_for_each_entry(dev_res, head, list) 463 if (dev_res->res->parent) 464 release_resource(dev_res->res); 465 /* Restore start/end/flags from saved list */ 466 list_for_each_entry(save_res, &save_head, list) { 467 struct resource *res = save_res->res; 468 469 res->start = save_res->start; 470 res->end = save_res->end; 471 res->flags = save_res->flags; 472 } 473 free_list(&save_head); 474 475 requested_and_reassign: 476 /* Satisfy the must-have resource requests */ 477 assign_requested_resources_sorted(head, fail_head); 478 479 /* Try to satisfy any additional optional resource requests */ 480 if (realloc_head) 481 reassign_resources_sorted(realloc_head, head); 482 free_list(head); 483 } 484 485 static void pdev_assign_resources_sorted(struct pci_dev *dev, 486 struct list_head *add_head, 487 struct list_head *fail_head) 488 { 489 LIST_HEAD(head); 490 491 __dev_sort_resources(dev, &head); 492 __assign_resources_sorted(&head, add_head, fail_head); 493 494 } 495 496 static void pbus_assign_resources_sorted(const struct pci_bus *bus, 497 struct list_head *realloc_head, 498 struct list_head *fail_head) 499 { 500 struct pci_dev *dev; 501 LIST_HEAD(head); 502 503 list_for_each_entry(dev, &bus->devices, bus_list) 504 __dev_sort_resources(dev, &head); 505 506 __assign_resources_sorted(&head, realloc_head, fail_head); 507 } 508 509 void pci_setup_cardbus(struct pci_bus *bus) 510 { 511 struct pci_dev *bridge = bus->self; 512 struct resource *res; 513 struct pci_bus_region region; 514 515 pci_info(bridge, "CardBus bridge to %pR\n", 516 &bus->busn_res); 517 518 res = bus->resource[0]; 519 pcibios_resource_to_bus(bridge->bus, ®ion, res); 520 if (res->flags & IORESOURCE_IO) { 521 /* 522 * The IO resource is allocated a range twice as large as it 523 * would normally need. This allows us to set both IO regs. 524 */ 525 pci_info(bridge, " bridge window %pR\n", res); 526 pci_write_config_dword(bridge, PCI_CB_IO_BASE_0, 527 region.start); 528 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0, 529 region.end); 530 } 531 532 res = bus->resource[1]; 533 pcibios_resource_to_bus(bridge->bus, ®ion, res); 534 if (res->flags & IORESOURCE_IO) { 535 pci_info(bridge, " bridge window %pR\n", res); 536 pci_write_config_dword(bridge, PCI_CB_IO_BASE_1, 537 region.start); 538 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1, 539 region.end); 540 } 541 542 res = bus->resource[2]; 543 pcibios_resource_to_bus(bridge->bus, ®ion, res); 544 if (res->flags & IORESOURCE_MEM) { 545 pci_info(bridge, " bridge window %pR\n", res); 546 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0, 547 region.start); 548 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0, 549 region.end); 550 } 551 552 res = bus->resource[3]; 553 pcibios_resource_to_bus(bridge->bus, ®ion, res); 554 if (res->flags & IORESOURCE_MEM) { 555 pci_info(bridge, " bridge window %pR\n", res); 556 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1, 557 region.start); 558 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1, 559 region.end); 560 } 561 } 562 EXPORT_SYMBOL(pci_setup_cardbus); 563 564 /* 565 * Initialize bridges with base/limit values we have collected. PCI-to-PCI 566 * Bridge Architecture Specification rev. 1.1 (1998) requires that if there 567 * are no I/O ports or memory behind the bridge, the corresponding range 568 * must be turned off by writing base value greater than limit to the 569 * bridge's base/limit registers. 570 * 571 * Note: care must be taken when updating I/O base/limit registers of 572 * bridges which support 32-bit I/O. This update requires two config space 573 * writes, so it's quite possible that an I/O window of the bridge will 574 * have some undesirable address (e.g. 0) after the first write. Ditto 575 * 64-bit prefetchable MMIO. 576 */ 577 static void pci_setup_bridge_io(struct pci_dev *bridge) 578 { 579 struct resource *res; 580 const char *res_name; 581 struct pci_bus_region region; 582 unsigned long io_mask; 583 u8 io_base_lo, io_limit_lo; 584 u16 l; 585 u32 io_upper16; 586 587 io_mask = PCI_IO_RANGE_MASK; 588 if (bridge->io_window_1k) 589 io_mask = PCI_IO_1K_RANGE_MASK; 590 591 /* Set up the top and bottom of the PCI I/O segment for this bus */ 592 res = &bridge->resource[PCI_BRIDGE_IO_WINDOW]; 593 res_name = pci_resource_name(bridge, PCI_BRIDGE_IO_WINDOW); 594 pcibios_resource_to_bus(bridge->bus, ®ion, res); 595 if (res->flags & IORESOURCE_IO) { 596 pci_read_config_word(bridge, PCI_IO_BASE, &l); 597 io_base_lo = (region.start >> 8) & io_mask; 598 io_limit_lo = (region.end >> 8) & io_mask; 599 l = ((u16) io_limit_lo << 8) | io_base_lo; 600 /* Set up upper 16 bits of I/O base/limit */ 601 io_upper16 = (region.end & 0xffff0000) | (region.start >> 16); 602 pci_info(bridge, " %s %pR\n", res_name, res); 603 } else { 604 /* Clear upper 16 bits of I/O base/limit */ 605 io_upper16 = 0; 606 l = 0x00f0; 607 } 608 /* Temporarily disable the I/O range before updating PCI_IO_BASE */ 609 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff); 610 /* Update lower 16 bits of I/O base/limit */ 611 pci_write_config_word(bridge, PCI_IO_BASE, l); 612 /* Update upper 16 bits of I/O base/limit */ 613 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16); 614 } 615 616 static void pci_setup_bridge_mmio(struct pci_dev *bridge) 617 { 618 struct resource *res; 619 const char *res_name; 620 struct pci_bus_region region; 621 u32 l; 622 623 /* Set up the top and bottom of the PCI Memory segment for this bus */ 624 res = &bridge->resource[PCI_BRIDGE_MEM_WINDOW]; 625 res_name = pci_resource_name(bridge, PCI_BRIDGE_MEM_WINDOW); 626 pcibios_resource_to_bus(bridge->bus, ®ion, res); 627 if (res->flags & IORESOURCE_MEM) { 628 l = (region.start >> 16) & 0xfff0; 629 l |= region.end & 0xfff00000; 630 pci_info(bridge, " %s %pR\n", res_name, res); 631 } else { 632 l = 0x0000fff0; 633 } 634 pci_write_config_dword(bridge, PCI_MEMORY_BASE, l); 635 } 636 637 static void pci_setup_bridge_mmio_pref(struct pci_dev *bridge) 638 { 639 struct resource *res; 640 const char *res_name; 641 struct pci_bus_region region; 642 u32 l, bu, lu; 643 644 /* 645 * Clear out the upper 32 bits of PREF limit. If 646 * PCI_PREF_BASE_UPPER32 was non-zero, this temporarily disables 647 * PREF range, which is ok. 648 */ 649 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0); 650 651 /* Set up PREF base/limit */ 652 bu = lu = 0; 653 res = &bridge->resource[PCI_BRIDGE_PREF_MEM_WINDOW]; 654 res_name = pci_resource_name(bridge, PCI_BRIDGE_PREF_MEM_WINDOW); 655 pcibios_resource_to_bus(bridge->bus, ®ion, res); 656 if (res->flags & IORESOURCE_PREFETCH) { 657 l = (region.start >> 16) & 0xfff0; 658 l |= region.end & 0xfff00000; 659 if (res->flags & IORESOURCE_MEM_64) { 660 bu = upper_32_bits(region.start); 661 lu = upper_32_bits(region.end); 662 } 663 pci_info(bridge, " %s %pR\n", res_name, res); 664 } else { 665 l = 0x0000fff0; 666 } 667 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l); 668 669 /* Set the upper 32 bits of PREF base & limit */ 670 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu); 671 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu); 672 } 673 674 static void __pci_setup_bridge(struct pci_bus *bus, unsigned long type) 675 { 676 struct pci_dev *bridge = bus->self; 677 678 pci_info(bridge, "PCI bridge to %pR\n", 679 &bus->busn_res); 680 681 if (type & IORESOURCE_IO) 682 pci_setup_bridge_io(bridge); 683 684 if (type & IORESOURCE_MEM) 685 pci_setup_bridge_mmio(bridge); 686 687 if (type & IORESOURCE_PREFETCH) 688 pci_setup_bridge_mmio_pref(bridge); 689 690 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl); 691 } 692 693 void __weak pcibios_setup_bridge(struct pci_bus *bus, unsigned long type) 694 { 695 } 696 697 void pci_setup_bridge(struct pci_bus *bus) 698 { 699 unsigned long type = IORESOURCE_IO | IORESOURCE_MEM | 700 IORESOURCE_PREFETCH; 701 702 pcibios_setup_bridge(bus, type); 703 __pci_setup_bridge(bus, type); 704 } 705 706 707 int pci_claim_bridge_resource(struct pci_dev *bridge, int i) 708 { 709 if (i < PCI_BRIDGE_RESOURCES || i > PCI_BRIDGE_RESOURCE_END) 710 return 0; 711 712 if (pci_claim_resource(bridge, i) == 0) 713 return 0; /* Claimed the window */ 714 715 if ((bridge->class >> 8) != PCI_CLASS_BRIDGE_PCI) 716 return 0; 717 718 if (!pci_bus_clip_resource(bridge, i)) 719 return -EINVAL; /* Clipping didn't change anything */ 720 721 switch (i) { 722 case PCI_BRIDGE_IO_WINDOW: 723 pci_setup_bridge_io(bridge); 724 break; 725 case PCI_BRIDGE_MEM_WINDOW: 726 pci_setup_bridge_mmio(bridge); 727 break; 728 case PCI_BRIDGE_PREF_MEM_WINDOW: 729 pci_setup_bridge_mmio_pref(bridge); 730 break; 731 default: 732 return -EINVAL; 733 } 734 735 if (pci_claim_resource(bridge, i) == 0) 736 return 0; /* Claimed a smaller window */ 737 738 return -EINVAL; 739 } 740 741 /* 742 * Check whether the bridge supports optional I/O and prefetchable memory 743 * ranges. If not, the respective base/limit registers must be read-only 744 * and read as 0. 745 */ 746 static void pci_bridge_check_ranges(struct pci_bus *bus) 747 { 748 struct pci_dev *bridge = bus->self; 749 struct resource *b_res; 750 751 b_res = &bridge->resource[PCI_BRIDGE_MEM_WINDOW]; 752 b_res->flags |= IORESOURCE_MEM; 753 754 if (bridge->io_window) { 755 b_res = &bridge->resource[PCI_BRIDGE_IO_WINDOW]; 756 b_res->flags |= IORESOURCE_IO; 757 } 758 759 if (bridge->pref_window) { 760 b_res = &bridge->resource[PCI_BRIDGE_PREF_MEM_WINDOW]; 761 b_res->flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH; 762 if (bridge->pref_64_window) { 763 b_res->flags |= IORESOURCE_MEM_64 | 764 PCI_PREF_RANGE_TYPE_64; 765 } 766 } 767 } 768 769 /* 770 * Helper function for sizing routines. Assigned resources have non-NULL 771 * parent resource. 772 * 773 * Return first unassigned resource of the correct type. If there is none, 774 * return first assigned resource of the correct type. If none of the 775 * above, return NULL. 776 * 777 * Returning an assigned resource of the correct type allows the caller to 778 * distinguish between already assigned and no resource of the correct type. 779 */ 780 static struct resource *find_bus_resource_of_type(struct pci_bus *bus, 781 unsigned long type_mask, 782 unsigned long type) 783 { 784 struct resource *r, *r_assigned = NULL; 785 786 pci_bus_for_each_resource(bus, r) { 787 if (r == &ioport_resource || r == &iomem_resource) 788 continue; 789 if (r && (r->flags & type_mask) == type && !r->parent) 790 return r; 791 if (r && (r->flags & type_mask) == type && !r_assigned) 792 r_assigned = r; 793 } 794 return r_assigned; 795 } 796 797 static resource_size_t calculate_iosize(resource_size_t size, 798 resource_size_t min_size, 799 resource_size_t size1, 800 resource_size_t add_size, 801 resource_size_t children_add_size, 802 resource_size_t old_size, 803 resource_size_t align) 804 { 805 if (size < min_size) 806 size = min_size; 807 if (old_size == 1) 808 old_size = 0; 809 /* 810 * To be fixed in 2.5: we should have sort of HAVE_ISA flag in the 811 * struct pci_bus. 812 */ 813 #if defined(CONFIG_ISA) || defined(CONFIG_EISA) 814 size = (size & 0xff) + ((size & ~0xffUL) << 2); 815 #endif 816 size = size + size1; 817 if (size < old_size) 818 size = old_size; 819 820 size = ALIGN(max(size, add_size) + children_add_size, align); 821 return size; 822 } 823 824 static resource_size_t calculate_memsize(resource_size_t size, 825 resource_size_t min_size, 826 resource_size_t add_size, 827 resource_size_t children_add_size, 828 resource_size_t old_size, 829 resource_size_t align) 830 { 831 if (size < min_size) 832 size = min_size; 833 if (old_size == 1) 834 old_size = 0; 835 836 size = max(size, add_size) + children_add_size; 837 return ALIGN(max(size, old_size), align); 838 } 839 840 resource_size_t __weak pcibios_window_alignment(struct pci_bus *bus, 841 unsigned long type) 842 { 843 return 1; 844 } 845 846 #define PCI_P2P_DEFAULT_MEM_ALIGN 0x100000 /* 1MiB */ 847 #define PCI_P2P_DEFAULT_IO_ALIGN 0x1000 /* 4KiB */ 848 #define PCI_P2P_DEFAULT_IO_ALIGN_1K 0x400 /* 1KiB */ 849 850 static resource_size_t window_alignment(struct pci_bus *bus, unsigned long type) 851 { 852 resource_size_t align = 1, arch_align; 853 854 if (type & IORESOURCE_MEM) 855 align = PCI_P2P_DEFAULT_MEM_ALIGN; 856 else if (type & IORESOURCE_IO) { 857 /* 858 * Per spec, I/O windows are 4K-aligned, but some bridges have 859 * an extension to support 1K alignment. 860 */ 861 if (bus->self && bus->self->io_window_1k) 862 align = PCI_P2P_DEFAULT_IO_ALIGN_1K; 863 else 864 align = PCI_P2P_DEFAULT_IO_ALIGN; 865 } 866 867 arch_align = pcibios_window_alignment(bus, type); 868 return max(align, arch_align); 869 } 870 871 /** 872 * pbus_size_io() - Size the I/O window of a given bus 873 * 874 * @bus: The bus 875 * @min_size: The minimum I/O window that must be allocated 876 * @add_size: Additional optional I/O window 877 * @realloc_head: Track the additional I/O window on this list 878 * 879 * Sizing the I/O windows of the PCI-PCI bridge is trivial, since these 880 * windows have 1K or 4K granularity and the I/O ranges of non-bridge PCI 881 * devices are limited to 256 bytes. We must be careful with the ISA 882 * aliasing though. 883 */ 884 static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size, 885 resource_size_t add_size, 886 struct list_head *realloc_head) 887 { 888 struct pci_dev *dev; 889 struct resource *b_res = find_bus_resource_of_type(bus, IORESOURCE_IO, 890 IORESOURCE_IO); 891 resource_size_t size = 0, size0 = 0, size1 = 0; 892 resource_size_t children_add_size = 0; 893 resource_size_t min_align, align; 894 895 if (!b_res) 896 return; 897 898 /* If resource is already assigned, nothing more to do */ 899 if (b_res->parent) 900 return; 901 902 min_align = window_alignment(bus, IORESOURCE_IO); 903 list_for_each_entry(dev, &bus->devices, bus_list) { 904 struct resource *r; 905 906 pci_dev_for_each_resource(dev, r) { 907 unsigned long r_size; 908 909 if (r->parent || !(r->flags & IORESOURCE_IO)) 910 continue; 911 r_size = resource_size(r); 912 913 if (r_size < 0x400) 914 /* Might be re-aligned for ISA */ 915 size += r_size; 916 else 917 size1 += r_size; 918 919 align = pci_resource_alignment(dev, r); 920 if (align > min_align) 921 min_align = align; 922 923 if (realloc_head) 924 children_add_size += get_res_add_size(realloc_head, r); 925 } 926 } 927 928 size0 = calculate_iosize(size, min_size, size1, 0, 0, 929 resource_size(b_res), min_align); 930 size1 = (!realloc_head || (realloc_head && !add_size && !children_add_size)) ? size0 : 931 calculate_iosize(size, min_size, size1, add_size, children_add_size, 932 resource_size(b_res), min_align); 933 if (!size0 && !size1) { 934 if (bus->self && (b_res->start || b_res->end)) 935 pci_info(bus->self, "disabling bridge window %pR to %pR (unused)\n", 936 b_res, &bus->busn_res); 937 b_res->flags = 0; 938 return; 939 } 940 941 b_res->start = min_align; 942 b_res->end = b_res->start + size0 - 1; 943 b_res->flags |= IORESOURCE_STARTALIGN; 944 if (bus->self && size1 > size0 && realloc_head) { 945 add_to_list(realloc_head, bus->self, b_res, size1-size0, 946 min_align); 947 pci_info(bus->self, "bridge window %pR to %pR add_size %llx\n", 948 b_res, &bus->busn_res, 949 (unsigned long long) size1 - size0); 950 } 951 } 952 953 static inline resource_size_t calculate_mem_align(resource_size_t *aligns, 954 int max_order) 955 { 956 resource_size_t align = 0; 957 resource_size_t min_align = 0; 958 int order; 959 960 for (order = 0; order <= max_order; order++) { 961 resource_size_t align1 = 1; 962 963 align1 <<= order + __ffs(SZ_1M); 964 965 if (!align) 966 min_align = align1; 967 else if (ALIGN(align + min_align, min_align) < align1) 968 min_align = align1 >> 1; 969 align += aligns[order]; 970 } 971 972 return min_align; 973 } 974 975 /** 976 * pbus_upstream_space_available - Check no upstream resource limits allocation 977 * @bus: The bus 978 * @mask: Mask the resource flag, then compare it with type 979 * @type: The type of resource from bridge 980 * @size: The size required from the bridge window 981 * @align: Required alignment for the resource 982 * 983 * Checks that @size can fit inside the upstream bridge resources that are 984 * already assigned. 985 * 986 * Return: %true if enough space is available on all assigned upstream 987 * resources. 988 */ 989 static bool pbus_upstream_space_available(struct pci_bus *bus, unsigned long mask, 990 unsigned long type, resource_size_t size, 991 resource_size_t align) 992 { 993 struct resource_constraint constraint = { 994 .max = RESOURCE_SIZE_MAX, 995 .align = align, 996 }; 997 struct pci_bus *downstream = bus; 998 struct resource *r; 999 1000 while ((bus = bus->parent)) { 1001 if (pci_is_root_bus(bus)) 1002 break; 1003 1004 pci_bus_for_each_resource(bus, r) { 1005 if (!r || !r->parent || (r->flags & mask) != type) 1006 continue; 1007 1008 if (resource_size(r) >= size) { 1009 struct resource gap = {}; 1010 1011 if (find_resource_space(r, &gap, size, &constraint) == 0) { 1012 gap.flags = type; 1013 pci_dbg(bus->self, 1014 "Assigned bridge window %pR to %pR free space at %pR\n", 1015 r, &bus->busn_res, &gap); 1016 return true; 1017 } 1018 } 1019 1020 if (bus->self) { 1021 pci_info(bus->self, 1022 "Assigned bridge window %pR to %pR cannot fit 0x%llx required for %s bridging to %pR\n", 1023 r, &bus->busn_res, 1024 (unsigned long long)size, 1025 pci_name(downstream->self), 1026 &downstream->busn_res); 1027 } 1028 1029 return false; 1030 } 1031 } 1032 1033 return true; 1034 } 1035 1036 /** 1037 * pbus_size_mem() - Size the memory window of a given bus 1038 * 1039 * @bus: The bus 1040 * @mask: Mask the resource flag, then compare it with type 1041 * @type: The type of free resource from bridge 1042 * @type2: Second match type 1043 * @type3: Third match type 1044 * @min_size: The minimum memory window that must be allocated 1045 * @add_size: Additional optional memory window 1046 * @realloc_head: Track the additional memory window on this list 1047 * 1048 * Calculate the size of the bus and minimal alignment which guarantees 1049 * that all child resources fit in this size. 1050 * 1051 * Return -ENOSPC if there's no available bus resource of the desired 1052 * type. Otherwise, set the bus resource start/end to indicate the 1053 * required size, add things to realloc_head (if supplied), and return 0. 1054 */ 1055 static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, 1056 unsigned long type, unsigned long type2, 1057 unsigned long type3, resource_size_t min_size, 1058 resource_size_t add_size, 1059 struct list_head *realloc_head) 1060 { 1061 struct pci_dev *dev; 1062 resource_size_t min_align, win_align, align, size, size0, size1; 1063 resource_size_t aligns[24]; /* Alignments from 1MB to 8TB */ 1064 int order, max_order; 1065 struct resource *b_res = find_bus_resource_of_type(bus, 1066 mask | IORESOURCE_PREFETCH, type); 1067 resource_size_t children_add_size = 0; 1068 resource_size_t children_add_align = 0; 1069 resource_size_t add_align = 0; 1070 1071 if (!b_res) 1072 return -ENOSPC; 1073 1074 /* If resource is already assigned, nothing more to do */ 1075 if (b_res->parent) 1076 return 0; 1077 1078 memset(aligns, 0, sizeof(aligns)); 1079 max_order = 0; 1080 size = 0; 1081 1082 list_for_each_entry(dev, &bus->devices, bus_list) { 1083 struct resource *r; 1084 int i; 1085 1086 pci_dev_for_each_resource(dev, r, i) { 1087 const char *r_name = pci_resource_name(dev, i); 1088 resource_size_t r_size; 1089 1090 if (r->parent || (r->flags & IORESOURCE_PCI_FIXED) || 1091 ((r->flags & mask) != type && 1092 (r->flags & mask) != type2 && 1093 (r->flags & mask) != type3)) 1094 continue; 1095 r_size = resource_size(r); 1096 #ifdef CONFIG_PCI_IOV 1097 /* Put SRIOV requested res to the optional list */ 1098 if (realloc_head && i >= PCI_IOV_RESOURCES && 1099 i <= PCI_IOV_RESOURCE_END) { 1100 add_align = max(pci_resource_alignment(dev, r), add_align); 1101 r->end = r->start - 1; 1102 add_to_list(realloc_head, dev, r, r_size, 0 /* Don't care */); 1103 children_add_size += r_size; 1104 continue; 1105 } 1106 #endif 1107 /* 1108 * aligns[0] is for 1MB (since bridge memory 1109 * windows are always at least 1MB aligned), so 1110 * keep "order" from being negative for smaller 1111 * resources. 1112 */ 1113 align = pci_resource_alignment(dev, r); 1114 order = __ffs(align) - __ffs(SZ_1M); 1115 if (order < 0) 1116 order = 0; 1117 if (order >= ARRAY_SIZE(aligns)) { 1118 pci_warn(dev, "%s %pR: disabling; bad alignment %#llx\n", 1119 r_name, r, (unsigned long long) align); 1120 r->flags = 0; 1121 continue; 1122 } 1123 size += max(r_size, align); 1124 /* 1125 * Exclude ranges with size > align from calculation of 1126 * the alignment. 1127 */ 1128 if (r_size <= align) 1129 aligns[order] += align; 1130 if (order > max_order) 1131 max_order = order; 1132 1133 if (realloc_head) { 1134 children_add_size += get_res_add_size(realloc_head, r); 1135 children_add_align = get_res_add_align(realloc_head, r); 1136 add_align = max(add_align, children_add_align); 1137 } 1138 } 1139 } 1140 1141 win_align = window_alignment(bus, b_res->flags); 1142 min_align = calculate_mem_align(aligns, max_order); 1143 min_align = max(min_align, win_align); 1144 size0 = calculate_memsize(size, min_size, 0, 0, resource_size(b_res), min_align); 1145 add_align = max(min_align, add_align); 1146 1147 if (bus->self && size0 && 1148 !pbus_upstream_space_available(bus, mask | IORESOURCE_PREFETCH, type, 1149 size0, add_align)) { 1150 min_align = 1ULL << (max_order + __ffs(SZ_1M)); 1151 min_align = max(min_align, win_align); 1152 size0 = calculate_memsize(size, min_size, 0, 0, resource_size(b_res), win_align); 1153 add_align = win_align; 1154 pci_info(bus->self, "bridge window %pR to %pR requires relaxed alignment rules\n", 1155 b_res, &bus->busn_res); 1156 } 1157 1158 size1 = (!realloc_head || (realloc_head && !add_size && !children_add_size)) ? size0 : 1159 calculate_memsize(size, min_size, add_size, children_add_size, 1160 resource_size(b_res), add_align); 1161 if (!size0 && !size1) { 1162 if (bus->self && (b_res->start || b_res->end)) 1163 pci_info(bus->self, "disabling bridge window %pR to %pR (unused)\n", 1164 b_res, &bus->busn_res); 1165 b_res->flags = 0; 1166 return 0; 1167 } 1168 b_res->start = min_align; 1169 b_res->end = size0 + min_align - 1; 1170 b_res->flags |= IORESOURCE_STARTALIGN; 1171 if (bus->self && size1 > size0 && realloc_head) { 1172 add_to_list(realloc_head, bus->self, b_res, size1-size0, add_align); 1173 pci_info(bus->self, "bridge window %pR to %pR add_size %llx add_align %llx\n", 1174 b_res, &bus->busn_res, 1175 (unsigned long long) (size1 - size0), 1176 (unsigned long long) add_align); 1177 } 1178 return 0; 1179 } 1180 1181 unsigned long pci_cardbus_resource_alignment(struct resource *res) 1182 { 1183 if (res->flags & IORESOURCE_IO) 1184 return pci_cardbus_io_size; 1185 if (res->flags & IORESOURCE_MEM) 1186 return pci_cardbus_mem_size; 1187 return 0; 1188 } 1189 1190 static void pci_bus_size_cardbus(struct pci_bus *bus, 1191 struct list_head *realloc_head) 1192 { 1193 struct pci_dev *bridge = bus->self; 1194 struct resource *b_res; 1195 resource_size_t b_res_3_size = pci_cardbus_mem_size * 2; 1196 u16 ctrl; 1197 1198 b_res = &bridge->resource[PCI_CB_BRIDGE_IO_0_WINDOW]; 1199 if (b_res->parent) 1200 goto handle_b_res_1; 1201 /* 1202 * Reserve some resources for CardBus. We reserve a fixed amount 1203 * of bus space for CardBus bridges. 1204 */ 1205 b_res->start = pci_cardbus_io_size; 1206 b_res->end = b_res->start + pci_cardbus_io_size - 1; 1207 b_res->flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN; 1208 if (realloc_head) { 1209 b_res->end -= pci_cardbus_io_size; 1210 add_to_list(realloc_head, bridge, b_res, pci_cardbus_io_size, 1211 pci_cardbus_io_size); 1212 } 1213 1214 handle_b_res_1: 1215 b_res = &bridge->resource[PCI_CB_BRIDGE_IO_1_WINDOW]; 1216 if (b_res->parent) 1217 goto handle_b_res_2; 1218 b_res->start = pci_cardbus_io_size; 1219 b_res->end = b_res->start + pci_cardbus_io_size - 1; 1220 b_res->flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN; 1221 if (realloc_head) { 1222 b_res->end -= pci_cardbus_io_size; 1223 add_to_list(realloc_head, bridge, b_res, pci_cardbus_io_size, 1224 pci_cardbus_io_size); 1225 } 1226 1227 handle_b_res_2: 1228 /* MEM1 must not be pref MMIO */ 1229 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); 1230 if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM1) { 1231 ctrl &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1; 1232 pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl); 1233 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); 1234 } 1235 1236 /* Check whether prefetchable memory is supported by this bridge. */ 1237 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); 1238 if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) { 1239 ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0; 1240 pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl); 1241 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); 1242 } 1243 1244 b_res = &bridge->resource[PCI_CB_BRIDGE_MEM_0_WINDOW]; 1245 if (b_res->parent) 1246 goto handle_b_res_3; 1247 /* 1248 * If we have prefetchable memory support, allocate two regions. 1249 * Otherwise, allocate one region of twice the size. 1250 */ 1251 if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) { 1252 b_res->start = pci_cardbus_mem_size; 1253 b_res->end = b_res->start + pci_cardbus_mem_size - 1; 1254 b_res->flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH | 1255 IORESOURCE_STARTALIGN; 1256 if (realloc_head) { 1257 b_res->end -= pci_cardbus_mem_size; 1258 add_to_list(realloc_head, bridge, b_res, 1259 pci_cardbus_mem_size, pci_cardbus_mem_size); 1260 } 1261 1262 /* Reduce that to half */ 1263 b_res_3_size = pci_cardbus_mem_size; 1264 } 1265 1266 handle_b_res_3: 1267 b_res = &bridge->resource[PCI_CB_BRIDGE_MEM_1_WINDOW]; 1268 if (b_res->parent) 1269 goto handle_done; 1270 b_res->start = pci_cardbus_mem_size; 1271 b_res->end = b_res->start + b_res_3_size - 1; 1272 b_res->flags |= IORESOURCE_MEM | IORESOURCE_STARTALIGN; 1273 if (realloc_head) { 1274 b_res->end -= b_res_3_size; 1275 add_to_list(realloc_head, bridge, b_res, b_res_3_size, 1276 pci_cardbus_mem_size); 1277 } 1278 1279 handle_done: 1280 ; 1281 } 1282 1283 void __pci_bus_size_bridges(struct pci_bus *bus, struct list_head *realloc_head) 1284 { 1285 struct pci_dev *dev; 1286 unsigned long mask, prefmask, type2 = 0, type3 = 0; 1287 resource_size_t additional_io_size = 0, additional_mmio_size = 0, 1288 additional_mmio_pref_size = 0; 1289 struct resource *pref; 1290 struct pci_host_bridge *host; 1291 int hdr_type, ret; 1292 1293 list_for_each_entry(dev, &bus->devices, bus_list) { 1294 struct pci_bus *b = dev->subordinate; 1295 if (!b) 1296 continue; 1297 1298 switch (dev->hdr_type) { 1299 case PCI_HEADER_TYPE_CARDBUS: 1300 pci_bus_size_cardbus(b, realloc_head); 1301 break; 1302 1303 case PCI_HEADER_TYPE_BRIDGE: 1304 default: 1305 __pci_bus_size_bridges(b, realloc_head); 1306 break; 1307 } 1308 } 1309 1310 /* The root bus? */ 1311 if (pci_is_root_bus(bus)) { 1312 host = to_pci_host_bridge(bus->bridge); 1313 if (!host->size_windows) 1314 return; 1315 pci_bus_for_each_resource(bus, pref) 1316 if (pref && (pref->flags & IORESOURCE_PREFETCH)) 1317 break; 1318 hdr_type = -1; /* Intentionally invalid - not a PCI device. */ 1319 } else { 1320 pref = &bus->self->resource[PCI_BRIDGE_PREF_MEM_WINDOW]; 1321 hdr_type = bus->self->hdr_type; 1322 } 1323 1324 switch (hdr_type) { 1325 case PCI_HEADER_TYPE_CARDBUS: 1326 /* Don't size CardBuses yet */ 1327 break; 1328 1329 case PCI_HEADER_TYPE_BRIDGE: 1330 pci_bridge_check_ranges(bus); 1331 if (bus->self->is_hotplug_bridge) { 1332 additional_io_size = pci_hotplug_io_size; 1333 additional_mmio_size = pci_hotplug_mmio_size; 1334 additional_mmio_pref_size = pci_hotplug_mmio_pref_size; 1335 } 1336 fallthrough; 1337 default: 1338 pbus_size_io(bus, realloc_head ? 0 : additional_io_size, 1339 additional_io_size, realloc_head); 1340 1341 /* 1342 * If there's a 64-bit prefetchable MMIO window, compute 1343 * the size required to put all 64-bit prefetchable 1344 * resources in it. 1345 */ 1346 mask = IORESOURCE_MEM; 1347 prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH; 1348 if (pref && (pref->flags & IORESOURCE_MEM_64)) { 1349 prefmask |= IORESOURCE_MEM_64; 1350 ret = pbus_size_mem(bus, prefmask, prefmask, 1351 prefmask, prefmask, 1352 realloc_head ? 0 : additional_mmio_pref_size, 1353 additional_mmio_pref_size, realloc_head); 1354 1355 /* 1356 * If successful, all non-prefetchable resources 1357 * and any 32-bit prefetchable resources will go in 1358 * the non-prefetchable window. 1359 */ 1360 if (ret == 0) { 1361 mask = prefmask; 1362 type2 = prefmask & ~IORESOURCE_MEM_64; 1363 type3 = prefmask & ~IORESOURCE_PREFETCH; 1364 } 1365 } 1366 1367 /* 1368 * If there is no 64-bit prefetchable window, compute the 1369 * size required to put all prefetchable resources in the 1370 * 32-bit prefetchable window (if there is one). 1371 */ 1372 if (!type2) { 1373 prefmask &= ~IORESOURCE_MEM_64; 1374 ret = pbus_size_mem(bus, prefmask, prefmask, 1375 prefmask, prefmask, 1376 realloc_head ? 0 : additional_mmio_pref_size, 1377 additional_mmio_pref_size, realloc_head); 1378 1379 /* 1380 * If successful, only non-prefetchable resources 1381 * will go in the non-prefetchable window. 1382 */ 1383 if (ret == 0) 1384 mask = prefmask; 1385 else 1386 additional_mmio_size += additional_mmio_pref_size; 1387 1388 type2 = type3 = IORESOURCE_MEM; 1389 } 1390 1391 /* 1392 * Compute the size required to put everything else in the 1393 * non-prefetchable window. This includes: 1394 * 1395 * - all non-prefetchable resources 1396 * - 32-bit prefetchable resources if there's a 64-bit 1397 * prefetchable window or no prefetchable window at all 1398 * - 64-bit prefetchable resources if there's no prefetchable 1399 * window at all 1400 * 1401 * Note that the strategy in __pci_assign_resource() must match 1402 * that used here. Specifically, we cannot put a 32-bit 1403 * prefetchable resource in a 64-bit prefetchable window. 1404 */ 1405 pbus_size_mem(bus, mask, IORESOURCE_MEM, type2, type3, 1406 realloc_head ? 0 : additional_mmio_size, 1407 additional_mmio_size, realloc_head); 1408 break; 1409 } 1410 } 1411 1412 void pci_bus_size_bridges(struct pci_bus *bus) 1413 { 1414 __pci_bus_size_bridges(bus, NULL); 1415 } 1416 EXPORT_SYMBOL(pci_bus_size_bridges); 1417 1418 static void assign_fixed_resource_on_bus(struct pci_bus *b, struct resource *r) 1419 { 1420 struct resource *parent_r; 1421 unsigned long mask = IORESOURCE_IO | IORESOURCE_MEM | 1422 IORESOURCE_PREFETCH; 1423 1424 pci_bus_for_each_resource(b, parent_r) { 1425 if (!parent_r) 1426 continue; 1427 1428 if ((r->flags & mask) == (parent_r->flags & mask) && 1429 resource_contains(parent_r, r)) 1430 request_resource(parent_r, r); 1431 } 1432 } 1433 1434 /* 1435 * Try to assign any resources marked as IORESOURCE_PCI_FIXED, as they are 1436 * skipped by pbus_assign_resources_sorted(). 1437 */ 1438 static void pdev_assign_fixed_resources(struct pci_dev *dev) 1439 { 1440 struct resource *r; 1441 1442 pci_dev_for_each_resource(dev, r) { 1443 struct pci_bus *b; 1444 1445 if (r->parent || !(r->flags & IORESOURCE_PCI_FIXED) || 1446 !(r->flags & (IORESOURCE_IO | IORESOURCE_MEM))) 1447 continue; 1448 1449 b = dev->bus; 1450 while (b && !r->parent) { 1451 assign_fixed_resource_on_bus(b, r); 1452 b = b->parent; 1453 } 1454 } 1455 } 1456 1457 void __pci_bus_assign_resources(const struct pci_bus *bus, 1458 struct list_head *realloc_head, 1459 struct list_head *fail_head) 1460 { 1461 struct pci_bus *b; 1462 struct pci_dev *dev; 1463 1464 pbus_assign_resources_sorted(bus, realloc_head, fail_head); 1465 1466 list_for_each_entry(dev, &bus->devices, bus_list) { 1467 pdev_assign_fixed_resources(dev); 1468 1469 b = dev->subordinate; 1470 if (!b) 1471 continue; 1472 1473 __pci_bus_assign_resources(b, realloc_head, fail_head); 1474 1475 switch (dev->hdr_type) { 1476 case PCI_HEADER_TYPE_BRIDGE: 1477 if (!pci_is_enabled(dev)) 1478 pci_setup_bridge(b); 1479 break; 1480 1481 case PCI_HEADER_TYPE_CARDBUS: 1482 pci_setup_cardbus(b); 1483 break; 1484 1485 default: 1486 pci_info(dev, "not setting up bridge for bus %04x:%02x\n", 1487 pci_domain_nr(b), b->number); 1488 break; 1489 } 1490 } 1491 } 1492 1493 void pci_bus_assign_resources(const struct pci_bus *bus) 1494 { 1495 __pci_bus_assign_resources(bus, NULL, NULL); 1496 } 1497 EXPORT_SYMBOL(pci_bus_assign_resources); 1498 1499 static void pci_claim_device_resources(struct pci_dev *dev) 1500 { 1501 int i; 1502 1503 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) { 1504 struct resource *r = &dev->resource[i]; 1505 1506 if (!r->flags || r->parent) 1507 continue; 1508 1509 pci_claim_resource(dev, i); 1510 } 1511 } 1512 1513 static void pci_claim_bridge_resources(struct pci_dev *dev) 1514 { 1515 int i; 1516 1517 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) { 1518 struct resource *r = &dev->resource[i]; 1519 1520 if (!r->flags || r->parent) 1521 continue; 1522 1523 pci_claim_bridge_resource(dev, i); 1524 } 1525 } 1526 1527 static void pci_bus_allocate_dev_resources(struct pci_bus *b) 1528 { 1529 struct pci_dev *dev; 1530 struct pci_bus *child; 1531 1532 list_for_each_entry(dev, &b->devices, bus_list) { 1533 pci_claim_device_resources(dev); 1534 1535 child = dev->subordinate; 1536 if (child) 1537 pci_bus_allocate_dev_resources(child); 1538 } 1539 } 1540 1541 static void pci_bus_allocate_resources(struct pci_bus *b) 1542 { 1543 struct pci_bus *child; 1544 1545 /* 1546 * Carry out a depth-first search on the PCI bus tree to allocate 1547 * bridge apertures. Read the programmed bridge bases and 1548 * recursively claim the respective bridge resources. 1549 */ 1550 if (b->self) { 1551 pci_read_bridge_bases(b); 1552 pci_claim_bridge_resources(b->self); 1553 } 1554 1555 list_for_each_entry(child, &b->children, node) 1556 pci_bus_allocate_resources(child); 1557 } 1558 1559 void pci_bus_claim_resources(struct pci_bus *b) 1560 { 1561 pci_bus_allocate_resources(b); 1562 pci_bus_allocate_dev_resources(b); 1563 } 1564 EXPORT_SYMBOL(pci_bus_claim_resources); 1565 1566 static void __pci_bridge_assign_resources(const struct pci_dev *bridge, 1567 struct list_head *add_head, 1568 struct list_head *fail_head) 1569 { 1570 struct pci_bus *b; 1571 1572 pdev_assign_resources_sorted((struct pci_dev *)bridge, 1573 add_head, fail_head); 1574 1575 b = bridge->subordinate; 1576 if (!b) 1577 return; 1578 1579 __pci_bus_assign_resources(b, add_head, fail_head); 1580 1581 switch (bridge->class >> 8) { 1582 case PCI_CLASS_BRIDGE_PCI: 1583 pci_setup_bridge(b); 1584 break; 1585 1586 case PCI_CLASS_BRIDGE_CARDBUS: 1587 pci_setup_cardbus(b); 1588 break; 1589 1590 default: 1591 pci_info(bridge, "not setting up bridge for bus %04x:%02x\n", 1592 pci_domain_nr(b), b->number); 1593 break; 1594 } 1595 } 1596 1597 #define PCI_RES_TYPE_MASK \ 1598 (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH |\ 1599 IORESOURCE_MEM_64) 1600 1601 static void pci_bridge_release_resources(struct pci_bus *bus, 1602 unsigned long type) 1603 { 1604 struct pci_dev *dev = bus->self; 1605 struct resource *r; 1606 unsigned int old_flags; 1607 struct resource *b_res; 1608 int idx = 1; 1609 1610 b_res = &dev->resource[PCI_BRIDGE_RESOURCES]; 1611 1612 /* 1613 * 1. If IO port assignment fails, release bridge IO port. 1614 * 2. If non pref MMIO assignment fails, release bridge nonpref MMIO. 1615 * 3. If 64bit pref MMIO assignment fails, and bridge pref is 64bit, 1616 * release bridge pref MMIO. 1617 * 4. If pref MMIO assignment fails, and bridge pref is 32bit, 1618 * release bridge pref MMIO. 1619 * 5. If pref MMIO assignment fails, and bridge pref is not 1620 * assigned, release bridge nonpref MMIO. 1621 */ 1622 if (type & IORESOURCE_IO) 1623 idx = 0; 1624 else if (!(type & IORESOURCE_PREFETCH)) 1625 idx = 1; 1626 else if ((type & IORESOURCE_MEM_64) && 1627 (b_res[2].flags & IORESOURCE_MEM_64)) 1628 idx = 2; 1629 else if (!(b_res[2].flags & IORESOURCE_MEM_64) && 1630 (b_res[2].flags & IORESOURCE_PREFETCH)) 1631 idx = 2; 1632 else 1633 idx = 1; 1634 1635 r = &b_res[idx]; 1636 1637 if (!r->parent) 1638 return; 1639 1640 /* If there are children, release them all */ 1641 release_child_resources(r); 1642 if (!release_resource(r)) { 1643 type = old_flags = r->flags & PCI_RES_TYPE_MASK; 1644 pci_info(dev, "resource %d %pR released\n", 1645 PCI_BRIDGE_RESOURCES + idx, r); 1646 /* Keep the old size */ 1647 r->end = resource_size(r) - 1; 1648 r->start = 0; 1649 r->flags = 0; 1650 1651 /* Avoiding touch the one without PREF */ 1652 if (type & IORESOURCE_PREFETCH) 1653 type = IORESOURCE_PREFETCH; 1654 __pci_setup_bridge(bus, type); 1655 /* For next child res under same bridge */ 1656 r->flags = old_flags; 1657 } 1658 } 1659 1660 enum release_type { 1661 leaf_only, 1662 whole_subtree, 1663 }; 1664 1665 /* 1666 * Try to release PCI bridge resources from leaf bridge, so we can allocate 1667 * a larger window later. 1668 */ 1669 static void pci_bus_release_bridge_resources(struct pci_bus *bus, 1670 unsigned long type, 1671 enum release_type rel_type) 1672 { 1673 struct pci_dev *dev; 1674 bool is_leaf_bridge = true; 1675 1676 list_for_each_entry(dev, &bus->devices, bus_list) { 1677 struct pci_bus *b = dev->subordinate; 1678 if (!b) 1679 continue; 1680 1681 is_leaf_bridge = false; 1682 1683 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI) 1684 continue; 1685 1686 if (rel_type == whole_subtree) 1687 pci_bus_release_bridge_resources(b, type, 1688 whole_subtree); 1689 } 1690 1691 if (pci_is_root_bus(bus)) 1692 return; 1693 1694 if ((bus->self->class >> 8) != PCI_CLASS_BRIDGE_PCI) 1695 return; 1696 1697 if ((rel_type == whole_subtree) || is_leaf_bridge) 1698 pci_bridge_release_resources(bus, type); 1699 } 1700 1701 static void pci_bus_dump_res(struct pci_bus *bus) 1702 { 1703 struct resource *res; 1704 int i; 1705 1706 pci_bus_for_each_resource(bus, res, i) { 1707 if (!res || !res->end || !res->flags) 1708 continue; 1709 1710 dev_info(&bus->dev, "resource %d %pR\n", i, res); 1711 } 1712 } 1713 1714 static void pci_bus_dump_resources(struct pci_bus *bus) 1715 { 1716 struct pci_bus *b; 1717 struct pci_dev *dev; 1718 1719 1720 pci_bus_dump_res(bus); 1721 1722 list_for_each_entry(dev, &bus->devices, bus_list) { 1723 b = dev->subordinate; 1724 if (!b) 1725 continue; 1726 1727 pci_bus_dump_resources(b); 1728 } 1729 } 1730 1731 static int pci_bus_get_depth(struct pci_bus *bus) 1732 { 1733 int depth = 0; 1734 struct pci_bus *child_bus; 1735 1736 list_for_each_entry(child_bus, &bus->children, node) { 1737 int ret; 1738 1739 ret = pci_bus_get_depth(child_bus); 1740 if (ret + 1 > depth) 1741 depth = ret + 1; 1742 } 1743 1744 return depth; 1745 } 1746 1747 /* 1748 * -1: undefined, will auto detect later 1749 * 0: disabled by user 1750 * 1: disabled by auto detect 1751 * 2: enabled by user 1752 * 3: enabled by auto detect 1753 */ 1754 enum enable_type { 1755 undefined = -1, 1756 user_disabled, 1757 auto_disabled, 1758 user_enabled, 1759 auto_enabled, 1760 }; 1761 1762 static enum enable_type pci_realloc_enable = undefined; 1763 void __init pci_realloc_get_opt(char *str) 1764 { 1765 if (!strncmp(str, "off", 3)) 1766 pci_realloc_enable = user_disabled; 1767 else if (!strncmp(str, "on", 2)) 1768 pci_realloc_enable = user_enabled; 1769 } 1770 static bool pci_realloc_enabled(enum enable_type enable) 1771 { 1772 return enable >= user_enabled; 1773 } 1774 1775 #if defined(CONFIG_PCI_IOV) && defined(CONFIG_PCI_REALLOC_ENABLE_AUTO) 1776 static int iov_resources_unassigned(struct pci_dev *dev, void *data) 1777 { 1778 int i; 1779 bool *unassigned = data; 1780 1781 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { 1782 struct resource *r = &dev->resource[i + PCI_IOV_RESOURCES]; 1783 struct pci_bus_region region; 1784 1785 /* Not assigned or rejected by kernel? */ 1786 if (!r->flags) 1787 continue; 1788 1789 pcibios_resource_to_bus(dev->bus, ®ion, r); 1790 if (!region.start) { 1791 *unassigned = true; 1792 return 1; /* Return early from pci_walk_bus() */ 1793 } 1794 } 1795 1796 return 0; 1797 } 1798 1799 static enum enable_type pci_realloc_detect(struct pci_bus *bus, 1800 enum enable_type enable_local) 1801 { 1802 bool unassigned = false; 1803 struct pci_host_bridge *host; 1804 1805 if (enable_local != undefined) 1806 return enable_local; 1807 1808 host = pci_find_host_bridge(bus); 1809 if (host->preserve_config) 1810 return auto_disabled; 1811 1812 pci_walk_bus(bus, iov_resources_unassigned, &unassigned); 1813 if (unassigned) 1814 return auto_enabled; 1815 1816 return enable_local; 1817 } 1818 #else 1819 static enum enable_type pci_realloc_detect(struct pci_bus *bus, 1820 enum enable_type enable_local) 1821 { 1822 return enable_local; 1823 } 1824 #endif 1825 1826 static void adjust_bridge_window(struct pci_dev *bridge, struct resource *res, 1827 struct list_head *add_list, 1828 resource_size_t new_size) 1829 { 1830 resource_size_t add_size, size = resource_size(res); 1831 1832 if (res->parent) 1833 return; 1834 1835 if (!new_size) 1836 return; 1837 1838 if (new_size > size) { 1839 add_size = new_size - size; 1840 pci_dbg(bridge, "bridge window %pR extended by %pa\n", res, 1841 &add_size); 1842 } else if (new_size < size) { 1843 add_size = size - new_size; 1844 pci_dbg(bridge, "bridge window %pR shrunken by %pa\n", res, 1845 &add_size); 1846 } else { 1847 return; 1848 } 1849 1850 res->end = res->start + new_size - 1; 1851 1852 /* If the resource is part of the add_list, remove it now */ 1853 if (add_list) 1854 remove_from_list(add_list, res); 1855 } 1856 1857 static void remove_dev_resource(struct resource *avail, struct pci_dev *dev, 1858 struct resource *res) 1859 { 1860 resource_size_t size, align, tmp; 1861 1862 size = resource_size(res); 1863 if (!size) 1864 return; 1865 1866 align = pci_resource_alignment(dev, res); 1867 align = align ? ALIGN(avail->start, align) - avail->start : 0; 1868 tmp = align + size; 1869 avail->start = min(avail->start + tmp, avail->end + 1); 1870 } 1871 1872 static void remove_dev_resources(struct pci_dev *dev, struct resource *io, 1873 struct resource *mmio, 1874 struct resource *mmio_pref) 1875 { 1876 struct resource *res; 1877 1878 pci_dev_for_each_resource(dev, res) { 1879 if (resource_type(res) == IORESOURCE_IO) { 1880 remove_dev_resource(io, dev, res); 1881 } else if (resource_type(res) == IORESOURCE_MEM) { 1882 1883 /* 1884 * Make sure prefetchable memory is reduced from 1885 * the correct resource. Specifically we put 32-bit 1886 * prefetchable memory in non-prefetchable window 1887 * if there is an 64-bit prefetchable window. 1888 * 1889 * See comments in __pci_bus_size_bridges() for 1890 * more information. 1891 */ 1892 if ((res->flags & IORESOURCE_PREFETCH) && 1893 ((res->flags & IORESOURCE_MEM_64) == 1894 (mmio_pref->flags & IORESOURCE_MEM_64))) 1895 remove_dev_resource(mmio_pref, dev, res); 1896 else 1897 remove_dev_resource(mmio, dev, res); 1898 } 1899 } 1900 } 1901 1902 /* 1903 * io, mmio and mmio_pref contain the total amount of bridge window space 1904 * available. This includes the minimal space needed to cover all the 1905 * existing devices on the bus and the possible extra space that can be 1906 * shared with the bridges. 1907 */ 1908 static void pci_bus_distribute_available_resources(struct pci_bus *bus, 1909 struct list_head *add_list, 1910 struct resource io, 1911 struct resource mmio, 1912 struct resource mmio_pref) 1913 { 1914 unsigned int normal_bridges = 0, hotplug_bridges = 0; 1915 struct resource *io_res, *mmio_res, *mmio_pref_res; 1916 struct pci_dev *dev, *bridge = bus->self; 1917 resource_size_t io_per_b, mmio_per_b, mmio_pref_per_b, align; 1918 1919 io_res = &bridge->resource[PCI_BRIDGE_IO_WINDOW]; 1920 mmio_res = &bridge->resource[PCI_BRIDGE_MEM_WINDOW]; 1921 mmio_pref_res = &bridge->resource[PCI_BRIDGE_PREF_MEM_WINDOW]; 1922 1923 /* 1924 * The alignment of this bridge is yet to be considered, hence it must 1925 * be done now before extending its bridge window. 1926 */ 1927 align = pci_resource_alignment(bridge, io_res); 1928 if (!io_res->parent && align) 1929 io.start = min(ALIGN(io.start, align), io.end + 1); 1930 1931 align = pci_resource_alignment(bridge, mmio_res); 1932 if (!mmio_res->parent && align) 1933 mmio.start = min(ALIGN(mmio.start, align), mmio.end + 1); 1934 1935 align = pci_resource_alignment(bridge, mmio_pref_res); 1936 if (!mmio_pref_res->parent && align) 1937 mmio_pref.start = min(ALIGN(mmio_pref.start, align), 1938 mmio_pref.end + 1); 1939 1940 /* 1941 * Now that we have adjusted for alignment, update the bridge window 1942 * resources to fill as much remaining resource space as possible. 1943 */ 1944 adjust_bridge_window(bridge, io_res, add_list, resource_size(&io)); 1945 adjust_bridge_window(bridge, mmio_res, add_list, resource_size(&mmio)); 1946 adjust_bridge_window(bridge, mmio_pref_res, add_list, 1947 resource_size(&mmio_pref)); 1948 1949 /* 1950 * Calculate how many hotplug bridges and normal bridges there 1951 * are on this bus. We will distribute the additional available 1952 * resources between hotplug bridges. 1953 */ 1954 for_each_pci_bridge(dev, bus) { 1955 if (dev->is_hotplug_bridge) 1956 hotplug_bridges++; 1957 else 1958 normal_bridges++; 1959 } 1960 1961 if (!(hotplug_bridges + normal_bridges)) 1962 return; 1963 1964 /* 1965 * Calculate the amount of space we can forward from "bus" to any 1966 * downstream buses, i.e., the space left over after assigning the 1967 * BARs and windows on "bus". 1968 */ 1969 list_for_each_entry(dev, &bus->devices, bus_list) { 1970 if (!dev->is_virtfn) 1971 remove_dev_resources(dev, &io, &mmio, &mmio_pref); 1972 } 1973 1974 /* 1975 * If there is at least one hotplug bridge on this bus it gets all 1976 * the extra resource space that was left after the reductions 1977 * above. 1978 * 1979 * If there are no hotplug bridges the extra resource space is 1980 * split between non-hotplug bridges. This is to allow possible 1981 * hotplug bridges below them to get the extra space as well. 1982 */ 1983 if (hotplug_bridges) { 1984 io_per_b = div64_ul(resource_size(&io), hotplug_bridges); 1985 mmio_per_b = div64_ul(resource_size(&mmio), hotplug_bridges); 1986 mmio_pref_per_b = div64_ul(resource_size(&mmio_pref), 1987 hotplug_bridges); 1988 } else { 1989 io_per_b = div64_ul(resource_size(&io), normal_bridges); 1990 mmio_per_b = div64_ul(resource_size(&mmio), normal_bridges); 1991 mmio_pref_per_b = div64_ul(resource_size(&mmio_pref), 1992 normal_bridges); 1993 } 1994 1995 for_each_pci_bridge(dev, bus) { 1996 struct resource *res; 1997 struct pci_bus *b; 1998 1999 b = dev->subordinate; 2000 if (!b) 2001 continue; 2002 if (hotplug_bridges && !dev->is_hotplug_bridge) 2003 continue; 2004 2005 res = &dev->resource[PCI_BRIDGE_IO_WINDOW]; 2006 2007 /* 2008 * Make sure the split resource space is properly aligned 2009 * for bridge windows (align it down to avoid going above 2010 * what is available). 2011 */ 2012 align = pci_resource_alignment(dev, res); 2013 io.end = align ? io.start + ALIGN_DOWN(io_per_b, align) - 1 2014 : io.start + io_per_b - 1; 2015 2016 /* 2017 * The x_per_b holds the extra resource space that can be 2018 * added for each bridge but there is the minimal already 2019 * reserved as well so adjust x.start down accordingly to 2020 * cover the whole space. 2021 */ 2022 io.start -= resource_size(res); 2023 2024 res = &dev->resource[PCI_BRIDGE_MEM_WINDOW]; 2025 align = pci_resource_alignment(dev, res); 2026 mmio.end = align ? mmio.start + ALIGN_DOWN(mmio_per_b, align) - 1 2027 : mmio.start + mmio_per_b - 1; 2028 mmio.start -= resource_size(res); 2029 2030 res = &dev->resource[PCI_BRIDGE_PREF_MEM_WINDOW]; 2031 align = pci_resource_alignment(dev, res); 2032 mmio_pref.end = align ? mmio_pref.start + 2033 ALIGN_DOWN(mmio_pref_per_b, align) - 1 2034 : mmio_pref.start + mmio_pref_per_b - 1; 2035 mmio_pref.start -= resource_size(res); 2036 2037 pci_bus_distribute_available_resources(b, add_list, io, mmio, 2038 mmio_pref); 2039 2040 io.start += io.end + 1; 2041 mmio.start += mmio.end + 1; 2042 mmio_pref.start += mmio_pref.end + 1; 2043 } 2044 } 2045 2046 static void pci_bridge_distribute_available_resources(struct pci_dev *bridge, 2047 struct list_head *add_list) 2048 { 2049 struct resource available_io, available_mmio, available_mmio_pref; 2050 2051 if (!bridge->is_hotplug_bridge) 2052 return; 2053 2054 pci_dbg(bridge, "distributing available resources\n"); 2055 2056 /* Take the initial extra resources from the hotplug port */ 2057 available_io = bridge->resource[PCI_BRIDGE_IO_WINDOW]; 2058 available_mmio = bridge->resource[PCI_BRIDGE_MEM_WINDOW]; 2059 available_mmio_pref = bridge->resource[PCI_BRIDGE_PREF_MEM_WINDOW]; 2060 2061 pci_bus_distribute_available_resources(bridge->subordinate, 2062 add_list, available_io, 2063 available_mmio, 2064 available_mmio_pref); 2065 } 2066 2067 static bool pci_bridge_resources_not_assigned(struct pci_dev *dev) 2068 { 2069 const struct resource *r; 2070 2071 /* 2072 * If the child device's resources are not yet assigned it means we 2073 * are configuring them (not the boot firmware), so we should be 2074 * able to extend the upstream bridge resources in the same way we 2075 * do with the normal hotplug case. 2076 */ 2077 r = &dev->resource[PCI_BRIDGE_IO_WINDOW]; 2078 if (r->flags && !(r->flags & IORESOURCE_STARTALIGN)) 2079 return false; 2080 r = &dev->resource[PCI_BRIDGE_MEM_WINDOW]; 2081 if (r->flags && !(r->flags & IORESOURCE_STARTALIGN)) 2082 return false; 2083 r = &dev->resource[PCI_BRIDGE_PREF_MEM_WINDOW]; 2084 if (r->flags && !(r->flags & IORESOURCE_STARTALIGN)) 2085 return false; 2086 2087 return true; 2088 } 2089 2090 static void 2091 pci_root_bus_distribute_available_resources(struct pci_bus *bus, 2092 struct list_head *add_list) 2093 { 2094 struct pci_dev *dev, *bridge = bus->self; 2095 2096 for_each_pci_bridge(dev, bus) { 2097 struct pci_bus *b; 2098 2099 b = dev->subordinate; 2100 if (!b) 2101 continue; 2102 2103 /* 2104 * Need to check "bridge" here too because it is NULL 2105 * in case of root bus. 2106 */ 2107 if (bridge && pci_bridge_resources_not_assigned(dev)) 2108 pci_bridge_distribute_available_resources(bridge, 2109 add_list); 2110 else 2111 pci_root_bus_distribute_available_resources(b, add_list); 2112 } 2113 } 2114 2115 /* 2116 * First try will not touch PCI bridge res. 2117 * Second and later try will clear small leaf bridge res. 2118 * Will stop till to the max depth if can not find good one. 2119 */ 2120 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus) 2121 { 2122 LIST_HEAD(realloc_head); 2123 /* List of resources that want additional resources */ 2124 struct list_head *add_list = NULL; 2125 int tried_times = 0; 2126 enum release_type rel_type = leaf_only; 2127 LIST_HEAD(fail_head); 2128 struct pci_dev_resource *fail_res; 2129 int pci_try_num = 1; 2130 enum enable_type enable_local; 2131 2132 /* Don't realloc if asked to do so */ 2133 enable_local = pci_realloc_detect(bus, pci_realloc_enable); 2134 if (pci_realloc_enabled(enable_local)) { 2135 int max_depth = pci_bus_get_depth(bus); 2136 2137 pci_try_num = max_depth + 1; 2138 dev_info(&bus->dev, "max bus depth: %d pci_try_num: %d\n", 2139 max_depth, pci_try_num); 2140 } 2141 2142 again: 2143 /* 2144 * Last try will use add_list, otherwise will try good to have as must 2145 * have, so can realloc parent bridge resource 2146 */ 2147 if (tried_times + 1 == pci_try_num) 2148 add_list = &realloc_head; 2149 /* 2150 * Depth first, calculate sizes and alignments of all subordinate buses. 2151 */ 2152 __pci_bus_size_bridges(bus, add_list); 2153 2154 pci_root_bus_distribute_available_resources(bus, add_list); 2155 2156 /* Depth last, allocate resources and update the hardware. */ 2157 __pci_bus_assign_resources(bus, add_list, &fail_head); 2158 if (add_list) 2159 BUG_ON(!list_empty(add_list)); 2160 tried_times++; 2161 2162 /* Any device complain? */ 2163 if (list_empty(&fail_head)) 2164 goto dump; 2165 2166 if (tried_times >= pci_try_num) { 2167 if (enable_local == undefined) 2168 dev_info(&bus->dev, "Some PCI device resources are unassigned, try booting with pci=realloc\n"); 2169 else if (enable_local == auto_enabled) 2170 dev_info(&bus->dev, "Automatically enabled pci realloc, if you have problem, try booting with pci=realloc=off\n"); 2171 2172 free_list(&fail_head); 2173 goto dump; 2174 } 2175 2176 dev_info(&bus->dev, "No. %d try to assign unassigned res\n", 2177 tried_times + 1); 2178 2179 /* Third times and later will not check if it is leaf */ 2180 if ((tried_times + 1) > 2) 2181 rel_type = whole_subtree; 2182 2183 /* 2184 * Try to release leaf bridge's resources that doesn't fit resource of 2185 * child device under that bridge. 2186 */ 2187 list_for_each_entry(fail_res, &fail_head, list) 2188 pci_bus_release_bridge_resources(fail_res->dev->bus, 2189 fail_res->flags & PCI_RES_TYPE_MASK, 2190 rel_type); 2191 2192 /* Restore size and flags */ 2193 list_for_each_entry(fail_res, &fail_head, list) { 2194 struct resource *res = fail_res->res; 2195 int idx; 2196 2197 res->start = fail_res->start; 2198 res->end = fail_res->end; 2199 res->flags = fail_res->flags; 2200 2201 if (pci_is_bridge(fail_res->dev)) { 2202 idx = res - &fail_res->dev->resource[0]; 2203 if (idx >= PCI_BRIDGE_RESOURCES && 2204 idx <= PCI_BRIDGE_RESOURCE_END) 2205 res->flags = 0; 2206 } 2207 } 2208 free_list(&fail_head); 2209 2210 goto again; 2211 2212 dump: 2213 /* Dump the resource on buses */ 2214 pci_bus_dump_resources(bus); 2215 } 2216 2217 void pci_assign_unassigned_resources(void) 2218 { 2219 struct pci_bus *root_bus; 2220 2221 list_for_each_entry(root_bus, &pci_root_buses, node) { 2222 pci_assign_unassigned_root_bus_resources(root_bus); 2223 2224 /* Make sure the root bridge has a companion ACPI device */ 2225 if (ACPI_HANDLE(root_bus->bridge)) 2226 acpi_ioapic_add(ACPI_HANDLE(root_bus->bridge)); 2227 } 2228 } 2229 2230 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge) 2231 { 2232 struct pci_bus *parent = bridge->subordinate; 2233 /* List of resources that want additional resources */ 2234 LIST_HEAD(add_list); 2235 2236 int tried_times = 0; 2237 LIST_HEAD(fail_head); 2238 struct pci_dev_resource *fail_res; 2239 int retval; 2240 2241 again: 2242 __pci_bus_size_bridges(parent, &add_list); 2243 2244 /* 2245 * Distribute remaining resources (if any) equally between hotplug 2246 * bridges below. This makes it possible to extend the hierarchy 2247 * later without running out of resources. 2248 */ 2249 pci_bridge_distribute_available_resources(bridge, &add_list); 2250 2251 __pci_bridge_assign_resources(bridge, &add_list, &fail_head); 2252 BUG_ON(!list_empty(&add_list)); 2253 tried_times++; 2254 2255 if (list_empty(&fail_head)) 2256 goto enable_all; 2257 2258 if (tried_times >= 2) { 2259 /* Still fail, don't need to try more */ 2260 free_list(&fail_head); 2261 goto enable_all; 2262 } 2263 2264 printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n", 2265 tried_times + 1); 2266 2267 /* 2268 * Try to release leaf bridge's resources that aren't big enough 2269 * to contain child device resources. 2270 */ 2271 list_for_each_entry(fail_res, &fail_head, list) 2272 pci_bus_release_bridge_resources(fail_res->dev->bus, 2273 fail_res->flags & PCI_RES_TYPE_MASK, 2274 whole_subtree); 2275 2276 /* Restore size and flags */ 2277 list_for_each_entry(fail_res, &fail_head, list) { 2278 struct resource *res = fail_res->res; 2279 int idx; 2280 2281 res->start = fail_res->start; 2282 res->end = fail_res->end; 2283 res->flags = fail_res->flags; 2284 2285 if (pci_is_bridge(fail_res->dev)) { 2286 idx = res - &fail_res->dev->resource[0]; 2287 if (idx >= PCI_BRIDGE_RESOURCES && 2288 idx <= PCI_BRIDGE_RESOURCE_END) 2289 res->flags = 0; 2290 } 2291 } 2292 free_list(&fail_head); 2293 2294 goto again; 2295 2296 enable_all: 2297 retval = pci_reenable_device(bridge); 2298 if (retval) 2299 pci_err(bridge, "Error reenabling bridge (%d)\n", retval); 2300 pci_set_master(bridge); 2301 } 2302 EXPORT_SYMBOL_GPL(pci_assign_unassigned_bridge_resources); 2303 2304 int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type) 2305 { 2306 struct pci_dev_resource *dev_res; 2307 struct pci_dev *next; 2308 LIST_HEAD(saved); 2309 LIST_HEAD(added); 2310 LIST_HEAD(failed); 2311 unsigned int i; 2312 int ret; 2313 2314 down_read(&pci_bus_sem); 2315 2316 /* Walk to the root hub, releasing bridge BARs when possible */ 2317 next = bridge; 2318 do { 2319 bridge = next; 2320 for (i = PCI_BRIDGE_RESOURCES; i < PCI_BRIDGE_RESOURCE_END; 2321 i++) { 2322 struct resource *res = &bridge->resource[i]; 2323 const char *res_name = pci_resource_name(bridge, i); 2324 2325 if ((res->flags ^ type) & PCI_RES_TYPE_MASK) 2326 continue; 2327 2328 /* Ignore BARs which are still in use */ 2329 if (res->child) 2330 continue; 2331 2332 ret = add_to_list(&saved, bridge, res, 0, 0); 2333 if (ret) 2334 goto cleanup; 2335 2336 pci_info(bridge, "%s %pR: releasing\n", res_name, res); 2337 2338 if (res->parent) 2339 release_resource(res); 2340 res->start = 0; 2341 res->end = 0; 2342 break; 2343 } 2344 if (i == PCI_BRIDGE_RESOURCE_END) 2345 break; 2346 2347 next = bridge->bus ? bridge->bus->self : NULL; 2348 } while (next); 2349 2350 if (list_empty(&saved)) { 2351 up_read(&pci_bus_sem); 2352 return -ENOENT; 2353 } 2354 2355 __pci_bus_size_bridges(bridge->subordinate, &added); 2356 __pci_bridge_assign_resources(bridge, &added, &failed); 2357 BUG_ON(!list_empty(&added)); 2358 2359 if (!list_empty(&failed)) { 2360 ret = -ENOSPC; 2361 goto cleanup; 2362 } 2363 2364 list_for_each_entry(dev_res, &saved, list) { 2365 /* Skip the bridge we just assigned resources for */ 2366 if (bridge == dev_res->dev) 2367 continue; 2368 2369 bridge = dev_res->dev; 2370 pci_setup_bridge(bridge->subordinate); 2371 } 2372 2373 free_list(&saved); 2374 up_read(&pci_bus_sem); 2375 return 0; 2376 2377 cleanup: 2378 /* Restore size and flags */ 2379 list_for_each_entry(dev_res, &failed, list) { 2380 struct resource *res = dev_res->res; 2381 2382 res->start = dev_res->start; 2383 res->end = dev_res->end; 2384 res->flags = dev_res->flags; 2385 } 2386 free_list(&failed); 2387 2388 /* Revert to the old configuration */ 2389 list_for_each_entry(dev_res, &saved, list) { 2390 struct resource *res = dev_res->res; 2391 2392 bridge = dev_res->dev; 2393 i = res - bridge->resource; 2394 2395 res->start = dev_res->start; 2396 res->end = dev_res->end; 2397 res->flags = dev_res->flags; 2398 2399 pci_claim_resource(bridge, i); 2400 pci_setup_bridge(bridge->subordinate); 2401 } 2402 free_list(&saved); 2403 up_read(&pci_bus_sem); 2404 2405 return ret; 2406 } 2407 2408 void pci_assign_unassigned_bus_resources(struct pci_bus *bus) 2409 { 2410 struct pci_dev *dev; 2411 /* List of resources that want additional resources */ 2412 LIST_HEAD(add_list); 2413 2414 down_read(&pci_bus_sem); 2415 for_each_pci_bridge(dev, bus) 2416 if (pci_has_subordinate(dev)) 2417 __pci_bus_size_bridges(dev->subordinate, &add_list); 2418 up_read(&pci_bus_sem); 2419 __pci_bus_assign_resources(bus, &add_list, NULL); 2420 BUG_ON(!list_empty(&add_list)); 2421 } 2422 EXPORT_SYMBOL_GPL(pci_assign_unassigned_bus_resources); 2423