1[ 2 { 3 "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", 4 "Counter": "0,1,2,3", 5 "EventCode": "0xC3", 6 "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", 7 "PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from memory disambiguation, external snoops, or cross SMT-HW-thread snoop (stores) hitting load buffers. Machine clears can have a significant performance impact if they are happening frequently.", 8 "SampleAfterValue": "100003", 9 "UMask": "0x2" 10 }, 11 { 12 "BriefDescription": "Loads with latency value being above 128.", 13 "Counter": "3", 14 "EventCode": "0xCD", 15 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", 16 "MSRIndex": "0x3F6", 17 "MSRValue": "0x80", 18 "PEBS": "2", 19 "SampleAfterValue": "1009", 20 "UMask": "0x1" 21 }, 22 { 23 "BriefDescription": "Loads with latency value being above 16.", 24 "Counter": "3", 25 "EventCode": "0xCD", 26 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", 27 "MSRIndex": "0x3F6", 28 "MSRValue": "0x10", 29 "PEBS": "2", 30 "SampleAfterValue": "20011", 31 "UMask": "0x1" 32 }, 33 { 34 "BriefDescription": "Loads with latency value being above 256.", 35 "Counter": "3", 36 "EventCode": "0xCD", 37 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", 38 "MSRIndex": "0x3F6", 39 "MSRValue": "0x100", 40 "PEBS": "2", 41 "SampleAfterValue": "503", 42 "UMask": "0x1" 43 }, 44 { 45 "BriefDescription": "Loads with latency value being above 32.", 46 "Counter": "3", 47 "EventCode": "0xCD", 48 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", 49 "MSRIndex": "0x3F6", 50 "MSRValue": "0x20", 51 "PEBS": "2", 52 "SampleAfterValue": "100007", 53 "UMask": "0x1" 54 }, 55 { 56 "BriefDescription": "Loads with latency value being above 4 .", 57 "Counter": "3", 58 "EventCode": "0xCD", 59 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", 60 "MSRIndex": "0x3F6", 61 "MSRValue": "0x4", 62 "PEBS": "2", 63 "SampleAfterValue": "100003", 64 "UMask": "0x1" 65 }, 66 { 67 "BriefDescription": "Loads with latency value being above 512.", 68 "Counter": "3", 69 "EventCode": "0xCD", 70 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", 71 "MSRIndex": "0x3F6", 72 "MSRValue": "0x200", 73 "PEBS": "2", 74 "SampleAfterValue": "101", 75 "UMask": "0x1" 76 }, 77 { 78 "BriefDescription": "Loads with latency value being above 64.", 79 "Counter": "3", 80 "EventCode": "0xCD", 81 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", 82 "MSRIndex": "0x3F6", 83 "MSRValue": "0x40", 84 "PEBS": "2", 85 "SampleAfterValue": "2003", 86 "UMask": "0x1" 87 }, 88 { 89 "BriefDescription": "Loads with latency value being above 8.", 90 "Counter": "3", 91 "EventCode": "0xCD", 92 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", 93 "MSRIndex": "0x3F6", 94 "MSRValue": "0x8", 95 "PEBS": "2", 96 "SampleAfterValue": "50021", 97 "UMask": "0x1" 98 }, 99 { 100 "BriefDescription": "Sample stores and collect precise store operation via PEBS record. PMC3 only. (Precise Event - PEBS).", 101 "Counter": "3", 102 "EventCode": "0xCD", 103 "EventName": "MEM_TRANS_RETIRED.PRECISE_STORE", 104 "PEBS": "2", 105 "SampleAfterValue": "2000003", 106 "UMask": "0x2" 107 }, 108 { 109 "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache.", 110 "Counter": "0,1,2,3", 111 "EventCode": "0x05", 112 "EventName": "MISALIGN_MEM_REF.LOADS", 113 "SampleAfterValue": "2000003", 114 "UMask": "0x1" 115 }, 116 { 117 "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache.", 118 "Counter": "0,1,2,3", 119 "EventCode": "0x05", 120 "EventName": "MISALIGN_MEM_REF.STORES", 121 "SampleAfterValue": "2000003", 122 "UMask": "0x2" 123 }, 124 { 125 "BriefDescription": "Counts all demand & prefetch code reads that miss the LLC and the data returned from dram.", 126 "Counter": "0,1,2,3", 127 "EventCode": "0xB7, 0xBB", 128 "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.DRAM", 129 "MSRIndex": "0x1a6,0x1a7", 130 "MSRValue": "0x300400244", 131 "SampleAfterValue": "100003", 132 "UMask": "0x1" 133 }, 134 { 135 "BriefDescription": "Counts all demand & prefetch data reads that miss the LLC and the data returned from dram.", 136 "Counter": "0,1,2,3", 137 "EventCode": "0xB7, 0xBB", 138 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.DRAM", 139 "MSRIndex": "0x1a6,0x1a7", 140 "MSRValue": "0x300400091", 141 "SampleAfterValue": "100003", 142 "UMask": "0x1" 143 }, 144 { 145 "BriefDescription": "Counts all prefetch code reads that miss the LLC and the data returned from dram.", 146 "Counter": "0,1,2,3", 147 "EventCode": "0xB7, 0xBB", 148 "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_MISS.DRAM", 149 "MSRIndex": "0x1a6,0x1a7", 150 "MSRValue": "0x300400240", 151 "SampleAfterValue": "100003", 152 "UMask": "0x1" 153 }, 154 { 155 "BriefDescription": "Counts all prefetch data reads that miss the LLC and the data returned from dram.", 156 "Counter": "0,1,2,3", 157 "EventCode": "0xB7, 0xBB", 158 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_MISS.DRAM", 159 "MSRIndex": "0x1a6,0x1a7", 160 "MSRValue": "0x300400090", 161 "SampleAfterValue": "100003", 162 "UMask": "0x1" 163 }, 164 { 165 "BriefDescription": "Counts all prefetch RFOs that miss the LLC and the data returned from dram.", 166 "Counter": "0,1,2,3", 167 "EventCode": "0xB7, 0xBB", 168 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.LLC_MISS.DRAM", 169 "MSRIndex": "0x1a6,0x1a7", 170 "MSRValue": "0x300400120", 171 "SampleAfterValue": "100003", 172 "UMask": "0x1" 173 }, 174 { 175 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the LLC and the data returned from dram.", 176 "Counter": "0,1,2,3", 177 "EventCode": "0xB7, 0xBB", 178 "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.DRAM", 179 "MSRIndex": "0x1a6,0x1a7", 180 "MSRValue": "0x3004003f7", 181 "SampleAfterValue": "100003", 182 "UMask": "0x1" 183 }, 184 { 185 "BriefDescription": "Counts all demand & prefetch RFOs that miss the LLC and the data returned from dram.", 186 "Counter": "0,1,2,3", 187 "EventCode": "0xB7, 0xBB", 188 "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.DRAM", 189 "MSRIndex": "0x1a6,0x1a7", 190 "MSRValue": "0x300400122", 191 "SampleAfterValue": "100003", 192 "UMask": "0x1" 193 }, 194 { 195 "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM", 196 "Counter": "0,1,2,3", 197 "EventCode": "0xB7, 0xBB", 198 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_MISS_LOCAL.DRAM", 199 "MSRIndex": "0x1a6,0x1a7", 200 "MSRValue": "0x1f80408fff", 201 "PublicDescription": "This event counts any requests that miss the LLC where the data was returned from local DRAM", 202 "SampleAfterValue": "100003", 203 "UMask": "0x1" 204 }, 205 { 206 "BriefDescription": "Counts LLC replacements.", 207 "Counter": "0,1,2,3", 208 "EventCode": "0xB7, 0xBB", 209 "EventName": "OFFCORE_RESPONSE.DATA_IN_SOCKET.LLC_MISS.LOCAL_DRAM", 210 "MSRIndex": "0x1a6,0x1a7", 211 "MSRValue": "0x6004001b3", 212 "PublicDescription": "This event counts all data requests (demand/prefetch data reads and demand data writes (RFOs) that miss the LLC where the data is returned from local DRAM", 213 "SampleAfterValue": "100003", 214 "UMask": "0x1" 215 }, 216 { 217 "BriefDescription": "REQUEST = DATA_IN_SOCKET and RESPONSE = LLC_MISS_LOCAL and SNOOP = ANY_LLC_HIT", 218 "Counter": "0,1,2,3", 219 "EventCode": "0xB7, 0xBB", 220 "EventName": "OFFCORE_RESPONSE.DATA_IN_SOCKET.LLC_MISS_LOCAL.ANY_LLC_HIT", 221 "MSRIndex": "0x1a6,0x1a7", 222 "MSRValue": "0x17004001b3", 223 "SampleAfterValue": "100003", 224 "UMask": "0x1" 225 }, 226 { 227 "BriefDescription": "Counts demand code reads that miss the LLC and the data returned from dram.", 228 "Counter": "0,1,2,3", 229 "EventCode": "0xB7, 0xBB", 230 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.DRAM", 231 "MSRIndex": "0x1a6,0x1a7", 232 "MSRValue": "0x300400004", 233 "SampleAfterValue": "100003", 234 "UMask": "0x1" 235 }, 236 { 237 "BriefDescription": "Counts demand data reads that miss the LLC and the data returned from dram.", 238 "Counter": "0,1,2,3", 239 "EventCode": "0xB7, 0xBB", 240 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.DRAM", 241 "MSRIndex": "0x1a6,0x1a7", 242 "MSRValue": "0x300400001", 243 "SampleAfterValue": "100003", 244 "UMask": "0x1" 245 }, 246 { 247 "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM", 248 "Counter": "0,1,2,3", 249 "EventCode": "0xB7, 0xBB", 250 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_MISS_LOCAL.DRAM", 251 "MSRIndex": "0x1a6,0x1a7", 252 "MSRValue": "0x1f80400004", 253 "SampleAfterValue": "100003", 254 "UMask": "0x1" 255 }, 256 { 257 "BriefDescription": "Counts demand data writes (RFOs) that miss the LLC and the data returned from dram.", 258 "Counter": "0,1,2,3", 259 "EventCode": "0xB7, 0xBB", 260 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.DRAM", 261 "MSRIndex": "0x1a6,0x1a7", 262 "MSRValue": "0x300400002", 263 "SampleAfterValue": "100003", 264 "UMask": "0x1" 265 }, 266 { 267 "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM", 268 "Counter": "0,1,2,3", 269 "EventCode": "0xB7, 0xBB", 270 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_MISS_LOCAL.DRAM", 271 "MSRIndex": "0x1a6,0x1a7", 272 "MSRValue": "0x1f80400010", 273 "SampleAfterValue": "100003", 274 "UMask": "0x1" 275 }, 276 { 277 "BriefDescription": "REQUEST = PF_RFO and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM", 278 "Counter": "0,1,2,3", 279 "EventCode": "0xB7, 0xBB", 280 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_MISS_LOCAL.DRAM", 281 "MSRIndex": "0x1a6,0x1a7", 282 "MSRValue": "0x1f80400040", 283 "SampleAfterValue": "100003", 284 "UMask": "0x1" 285 }, 286 { 287 "BriefDescription": "Counts all prefetch (that bring data to L2) code reads that miss the LLC and the data returned from dram.", 288 "Counter": "0,1,2,3", 289 "EventCode": "0xB7, 0xBB", 290 "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_MISS.DRAM", 291 "MSRIndex": "0x1a6,0x1a7", 292 "MSRValue": "0x300400040", 293 "SampleAfterValue": "100003", 294 "UMask": "0x1" 295 }, 296 { 297 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from dram.", 298 "Counter": "0,1,2,3", 299 "EventCode": "0xB7, 0xBB", 300 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.DRAM", 301 "MSRIndex": "0x1a6,0x1a7", 302 "MSRValue": "0x300400010", 303 "SampleAfterValue": "100003", 304 "UMask": "0x1" 305 }, 306 { 307 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the LLC and the data returned from dram.", 308 "Counter": "0,1,2,3", 309 "EventCode": "0xB7, 0xBB", 310 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_MISS.DRAM", 311 "MSRIndex": "0x1a6,0x1a7", 312 "MSRValue": "0x300400020", 313 "SampleAfterValue": "100003", 314 "UMask": "0x1" 315 }, 316 { 317 "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that miss the LLC and the data returned from dram.", 318 "Counter": "0,1,2,3", 319 "EventCode": "0xB7, 0xBB", 320 "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.DRAM", 321 "MSRIndex": "0x1a6,0x1a7", 322 "MSRValue": "0x300400200", 323 "SampleAfterValue": "100003", 324 "UMask": "0x1" 325 }, 326 { 327 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the LLC and the data returned from dram.", 328 "Counter": "0,1,2,3", 329 "EventCode": "0xB7, 0xBB", 330 "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_MISS.DRAM", 331 "MSRIndex": "0x1a6,0x1a7", 332 "MSRValue": "0x300400080", 333 "SampleAfterValue": "100003", 334 "UMask": "0x1" 335 }, 336 { 337 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the LLC and the data returned from dram.", 338 "Counter": "0,1,2,3", 339 "EventCode": "0xB7, 0xBB", 340 "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_MISS.DRAM", 341 "MSRIndex": "0x1a6,0x1a7", 342 "MSRValue": "0x300400100", 343 "SampleAfterValue": "100003", 344 "UMask": "0x1" 345 }, 346 { 347 "BriefDescription": "REQUEST = PF_LLC_DATA_RD and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM", 348 "Counter": "0,1,2,3", 349 "EventCode": "0xB7, 0xBB", 350 "EventName": "OFFCORE_RESPONSE.PF_L_DATA_RD.LLC_MISS_LOCAL.DRAM", 351 "MSRIndex": "0x1a6,0x1a7", 352 "MSRValue": "0x1f80400080", 353 "SampleAfterValue": "100003", 354 "UMask": "0x1" 355 }, 356 { 357 "BriefDescription": "REQUEST = PF_LLC_IFETCH and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM", 358 "Counter": "0,1,2,3", 359 "EventCode": "0xB7, 0xBB", 360 "EventName": "OFFCORE_RESPONSE.PF_L_IFETCH.LLC_MISS_LOCAL.DRAM", 361 "MSRIndex": "0x1a6,0x1a7", 362 "MSRValue": "0x1f80400200", 363 "SampleAfterValue": "100003", 364 "UMask": "0x1" 365 }, 366 { 367 "BriefDescription": "Number of any page walk that had a miss in LLC. Does not necessary cause a SUSPEND.", 368 "Counter": "0,1,2,3", 369 "EventCode": "0xBE", 370 "EventName": "PAGE_WALKS.LLC_MISS", 371 "SampleAfterValue": "100003", 372 "UMask": "0x1" 373 } 374] 375