1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/clock/qcom,rpmh.h> 7#include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h> 8#include <dt-bindings/clock/qcom,x1e80100-dispcc.h> 9#include <dt-bindings/clock/qcom,x1e80100-gcc.h> 10#include <dt-bindings/clock/qcom,x1e80100-gpucc.h> 11#include <dt-bindings/clock/qcom,x1e80100-tcsr.h> 12#include <dt-bindings/dma/qcom-gpi.h> 13#include <dt-bindings/interconnect/qcom,icc.h> 14#include <dt-bindings/interconnect/qcom,x1e80100-rpmh.h> 15#include <dt-bindings/interrupt-controller/arm-gic.h> 16#include <dt-bindings/mailbox/qcom-ipcc.h> 17#include <dt-bindings/phy/phy-qcom-qmp.h> 18#include <dt-bindings/power/qcom,rpmhpd.h> 19#include <dt-bindings/power/qcom-rpmpd.h> 20#include <dt-bindings/soc/qcom,gpr.h> 21#include <dt-bindings/soc/qcom,rpmh-rsc.h> 22#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 23 24/ { 25 interrupt-parent = <&intc>; 26 27 #address-cells = <2>; 28 #size-cells = <2>; 29 30 chosen { }; 31 32 clocks { 33 xo_board: xo-board { 34 compatible = "fixed-clock"; 35 clock-frequency = <76800000>; 36 #clock-cells = <0>; 37 }; 38 39 sleep_clk: sleep-clk { 40 compatible = "fixed-clock"; 41 clock-frequency = <32764>; 42 #clock-cells = <0>; 43 }; 44 45 bi_tcxo_div2: bi-tcxo-div2-clk { 46 compatible = "fixed-factor-clock"; 47 #clock-cells = <0>; 48 49 clocks = <&rpmhcc RPMH_CXO_CLK>; 50 clock-mult = <1>; 51 clock-div = <2>; 52 }; 53 54 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { 55 compatible = "fixed-factor-clock"; 56 #clock-cells = <0>; 57 58 clocks = <&rpmhcc RPMH_CXO_CLK_A>; 59 clock-mult = <1>; 60 clock-div = <2>; 61 }; 62 }; 63 64 cpus { 65 #address-cells = <2>; 66 #size-cells = <0>; 67 68 cpu0: cpu@0 { 69 device_type = "cpu"; 70 compatible = "qcom,oryon"; 71 reg = <0x0 0x0>; 72 enable-method = "psci"; 73 next-level-cache = <&l2_0>; 74 power-domains = <&cpu_pd0>; 75 power-domain-names = "psci"; 76 cpu-idle-states = <&cluster_c4>; 77 78 l2_0: l2-cache { 79 compatible = "cache"; 80 cache-level = <2>; 81 cache-unified; 82 }; 83 }; 84 85 cpu1: cpu@100 { 86 device_type = "cpu"; 87 compatible = "qcom,oryon"; 88 reg = <0x0 0x100>; 89 enable-method = "psci"; 90 next-level-cache = <&l2_0>; 91 power-domains = <&cpu_pd1>; 92 power-domain-names = "psci"; 93 cpu-idle-states = <&cluster_c4>; 94 }; 95 96 cpu2: cpu@200 { 97 device_type = "cpu"; 98 compatible = "qcom,oryon"; 99 reg = <0x0 0x200>; 100 enable-method = "psci"; 101 next-level-cache = <&l2_0>; 102 power-domains = <&cpu_pd2>; 103 power-domain-names = "psci"; 104 cpu-idle-states = <&cluster_c4>; 105 }; 106 107 cpu3: cpu@300 { 108 device_type = "cpu"; 109 compatible = "qcom,oryon"; 110 reg = <0x0 0x300>; 111 enable-method = "psci"; 112 next-level-cache = <&l2_0>; 113 power-domains = <&cpu_pd3>; 114 power-domain-names = "psci"; 115 cpu-idle-states = <&cluster_c4>; 116 }; 117 118 cpu4: cpu@10000 { 119 device_type = "cpu"; 120 compatible = "qcom,oryon"; 121 reg = <0x0 0x10000>; 122 enable-method = "psci"; 123 next-level-cache = <&l2_1>; 124 power-domains = <&cpu_pd4>; 125 power-domain-names = "psci"; 126 cpu-idle-states = <&cluster_c4>; 127 128 l2_1: l2-cache { 129 compatible = "cache"; 130 cache-level = <2>; 131 cache-unified; 132 }; 133 }; 134 135 cpu5: cpu@10100 { 136 device_type = "cpu"; 137 compatible = "qcom,oryon"; 138 reg = <0x0 0x10100>; 139 enable-method = "psci"; 140 next-level-cache = <&l2_1>; 141 power-domains = <&cpu_pd5>; 142 power-domain-names = "psci"; 143 cpu-idle-states = <&cluster_c4>; 144 }; 145 146 cpu6: cpu@10200 { 147 device_type = "cpu"; 148 compatible = "qcom,oryon"; 149 reg = <0x0 0x10200>; 150 enable-method = "psci"; 151 next-level-cache = <&l2_1>; 152 power-domains = <&cpu_pd6>; 153 power-domain-names = "psci"; 154 cpu-idle-states = <&cluster_c4>; 155 }; 156 157 cpu7: cpu@10300 { 158 device_type = "cpu"; 159 compatible = "qcom,oryon"; 160 reg = <0x0 0x10300>; 161 enable-method = "psci"; 162 next-level-cache = <&l2_1>; 163 power-domains = <&cpu_pd7>; 164 power-domain-names = "psci"; 165 cpu-idle-states = <&cluster_c4>; 166 }; 167 168 cpu8: cpu@20000 { 169 device_type = "cpu"; 170 compatible = "qcom,oryon"; 171 reg = <0x0 0x20000>; 172 enable-method = "psci"; 173 next-level-cache = <&l2_2>; 174 power-domains = <&cpu_pd8>; 175 power-domain-names = "psci"; 176 cpu-idle-states = <&cluster_c4>; 177 178 l2_2: l2-cache { 179 compatible = "cache"; 180 cache-level = <2>; 181 cache-unified; 182 }; 183 }; 184 185 cpu9: cpu@20100 { 186 device_type = "cpu"; 187 compatible = "qcom,oryon"; 188 reg = <0x0 0x20100>; 189 enable-method = "psci"; 190 next-level-cache = <&l2_2>; 191 power-domains = <&cpu_pd9>; 192 power-domain-names = "psci"; 193 cpu-idle-states = <&cluster_c4>; 194 }; 195 196 cpu10: cpu@20200 { 197 device_type = "cpu"; 198 compatible = "qcom,oryon"; 199 reg = <0x0 0x20200>; 200 enable-method = "psci"; 201 next-level-cache = <&l2_2>; 202 power-domains = <&cpu_pd10>; 203 power-domain-names = "psci"; 204 cpu-idle-states = <&cluster_c4>; 205 }; 206 207 cpu11: cpu@20300 { 208 device_type = "cpu"; 209 compatible = "qcom,oryon"; 210 reg = <0x0 0x20300>; 211 enable-method = "psci"; 212 next-level-cache = <&l2_2>; 213 power-domains = <&cpu_pd11>; 214 power-domain-names = "psci"; 215 cpu-idle-states = <&cluster_c4>; 216 }; 217 218 cpu-map { 219 cluster0 { 220 core0 { 221 cpu = <&cpu0>; 222 }; 223 224 core1 { 225 cpu = <&cpu1>; 226 }; 227 228 core2 { 229 cpu = <&cpu2>; 230 }; 231 232 core3 { 233 cpu = <&cpu3>; 234 }; 235 }; 236 237 cluster1 { 238 core0 { 239 cpu = <&cpu4>; 240 }; 241 242 core1 { 243 cpu = <&cpu5>; 244 }; 245 246 core2 { 247 cpu = <&cpu6>; 248 }; 249 250 core3 { 251 cpu = <&cpu7>; 252 }; 253 }; 254 255 cluster2 { 256 core0 { 257 cpu = <&cpu8>; 258 }; 259 260 core1 { 261 cpu = <&cpu9>; 262 }; 263 264 core2 { 265 cpu = <&cpu10>; 266 }; 267 268 core3 { 269 cpu = <&cpu11>; 270 }; 271 }; 272 }; 273 274 idle-states { 275 entry-method = "psci"; 276 277 cluster_c4: cpu-sleep-0 { 278 compatible = "arm,idle-state"; 279 idle-state-name = "ret"; 280 arm,psci-suspend-param = <0x00000004>; 281 entry-latency-us = <180>; 282 exit-latency-us = <500>; 283 min-residency-us = <600>; 284 }; 285 }; 286 287 domain-idle-states { 288 cluster_cl4: cluster-sleep-0 { 289 compatible = "domain-idle-state"; 290 arm,psci-suspend-param = <0x01000044>; 291 entry-latency-us = <350>; 292 exit-latency-us = <500>; 293 min-residency-us = <2500>; 294 }; 295 296 cluster_cl5: cluster-sleep-1 { 297 compatible = "domain-idle-state"; 298 arm,psci-suspend-param = <0x01000054>; 299 entry-latency-us = <2200>; 300 exit-latency-us = <4000>; 301 min-residency-us = <7000>; 302 }; 303 }; 304 }; 305 306 dummy-sink { 307 compatible = "arm,coresight-dummy-sink"; 308 309 in-ports { 310 port { 311 eud_in: endpoint { 312 remote-endpoint = <&swao_rep_out1>; 313 }; 314 }; 315 }; 316 }; 317 318 firmware { 319 scm: scm { 320 compatible = "qcom,scm-x1e80100", "qcom,scm"; 321 interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 322 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 323 qcom,dload-mode = <&tcsr 0x19000>; 324 }; 325 }; 326 327 clk_virt: interconnect-0 { 328 compatible = "qcom,x1e80100-clk-virt"; 329 #interconnect-cells = <2>; 330 qcom,bcm-voters = <&apps_bcm_voter>; 331 }; 332 333 mc_virt: interconnect-1 { 334 compatible = "qcom,x1e80100-mc-virt"; 335 #interconnect-cells = <2>; 336 qcom,bcm-voters = <&apps_bcm_voter>; 337 }; 338 339 memory@80000000 { 340 device_type = "memory"; 341 /* We expect the bootloader to fill in the size */ 342 reg = <0 0x80000000 0 0>; 343 }; 344 345 pmu { 346 compatible = "arm,armv8-pmuv3"; 347 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 348 }; 349 350 psci { 351 compatible = "arm,psci-1.0"; 352 method = "smc"; 353 354 cpu_pd0: power-domain-cpu0 { 355 #power-domain-cells = <0>; 356 power-domains = <&cluster_pd0>; 357 }; 358 359 cpu_pd1: power-domain-cpu1 { 360 #power-domain-cells = <0>; 361 power-domains = <&cluster_pd0>; 362 }; 363 364 cpu_pd2: power-domain-cpu2 { 365 #power-domain-cells = <0>; 366 power-domains = <&cluster_pd0>; 367 }; 368 369 cpu_pd3: power-domain-cpu3 { 370 #power-domain-cells = <0>; 371 power-domains = <&cluster_pd0>; 372 }; 373 374 cpu_pd4: power-domain-cpu4 { 375 #power-domain-cells = <0>; 376 power-domains = <&cluster_pd1>; 377 }; 378 379 cpu_pd5: power-domain-cpu5 { 380 #power-domain-cells = <0>; 381 power-domains = <&cluster_pd1>; 382 }; 383 384 cpu_pd6: power-domain-cpu6 { 385 #power-domain-cells = <0>; 386 power-domains = <&cluster_pd1>; 387 }; 388 389 cpu_pd7: power-domain-cpu7 { 390 #power-domain-cells = <0>; 391 power-domains = <&cluster_pd1>; 392 }; 393 394 cpu_pd8: power-domain-cpu8 { 395 #power-domain-cells = <0>; 396 power-domains = <&cluster_pd2>; 397 }; 398 399 cpu_pd9: power-domain-cpu9 { 400 #power-domain-cells = <0>; 401 power-domains = <&cluster_pd2>; 402 }; 403 404 cpu_pd10: power-domain-cpu10 { 405 #power-domain-cells = <0>; 406 power-domains = <&cluster_pd2>; 407 }; 408 409 cpu_pd11: power-domain-cpu11 { 410 #power-domain-cells = <0>; 411 power-domains = <&cluster_pd2>; 412 }; 413 414 cluster_pd0: power-domain-cpu-cluster0 { 415 #power-domain-cells = <0>; 416 domain-idle-states = <&cluster_cl4>, <&cluster_cl5>; 417 power-domains = <&system_pd>; 418 }; 419 420 cluster_pd1: power-domain-cpu-cluster1 { 421 #power-domain-cells = <0>; 422 domain-idle-states = <&cluster_cl4>, <&cluster_cl5>; 423 power-domains = <&system_pd>; 424 }; 425 426 cluster_pd2: power-domain-cpu-cluster2 { 427 #power-domain-cells = <0>; 428 domain-idle-states = <&cluster_cl4>, <&cluster_cl5>; 429 power-domains = <&system_pd>; 430 }; 431 432 system_pd: power-domain-system { 433 #power-domain-cells = <0>; 434 /* TODO: system-wide idle states */ 435 }; 436 }; 437 438 reserved-memory { 439 #address-cells = <2>; 440 #size-cells = <2>; 441 ranges; 442 443 gunyah_hyp_mem: gunyah-hyp@80000000 { 444 reg = <0x0 0x80000000 0x0 0x800000>; 445 no-map; 446 }; 447 448 hyp_elf_package_mem: hyp-elf-package@80800000 { 449 reg = <0x0 0x80800000 0x0 0x200000>; 450 no-map; 451 }; 452 453 ncc_mem: ncc@80a00000 { 454 reg = <0x0 0x80a00000 0x0 0x400000>; 455 no-map; 456 }; 457 458 cpucp_log_mem: cpucp-log@80e00000 { 459 reg = <0x0 0x80e00000 0x0 0x40000>; 460 no-map; 461 }; 462 463 cpucp_mem: cpucp@80e40000 { 464 reg = <0x0 0x80e40000 0x0 0x540000>; 465 no-map; 466 }; 467 468 reserved-region@81380000 { 469 reg = <0x0 0x81380000 0x0 0x80000>; 470 no-map; 471 }; 472 473 tags_mem: tags-region@81400000 { 474 reg = <0x0 0x81400000 0x0 0x1a0000>; 475 no-map; 476 }; 477 478 xbl_dtlog_mem: xbl-dtlog@81a00000 { 479 reg = <0x0 0x81a00000 0x0 0x40000>; 480 no-map; 481 }; 482 483 xbl_ramdump_mem: xbl-ramdump@81a40000 { 484 reg = <0x0 0x81a40000 0x0 0x1c0000>; 485 no-map; 486 }; 487 488 aop_image_mem: aop-image@81c00000 { 489 reg = <0x0 0x81c00000 0x0 0x60000>; 490 no-map; 491 }; 492 493 aop_cmd_db_mem: aop-cmd-db@81c60000 { 494 compatible = "qcom,cmd-db"; 495 reg = <0x0 0x81c60000 0x0 0x20000>; 496 no-map; 497 }; 498 499 aop_config_mem: aop-config@81c80000 { 500 reg = <0x0 0x81c80000 0x0 0x20000>; 501 no-map; 502 }; 503 504 tme_crash_dump_mem: tme-crash-dump@81ca0000 { 505 reg = <0x0 0x81ca0000 0x0 0x40000>; 506 no-map; 507 }; 508 509 tme_log_mem: tme-log@81ce0000 { 510 reg = <0x0 0x81ce0000 0x0 0x4000>; 511 no-map; 512 }; 513 514 uefi_log_mem: uefi-log@81ce4000 { 515 reg = <0x0 0x81ce4000 0x0 0x10000>; 516 no-map; 517 }; 518 519 secdata_apss_mem: secdata-apss@81cff000 { 520 reg = <0x0 0x81cff000 0x0 0x1000>; 521 no-map; 522 }; 523 524 pdp_ns_shared_mem: pdp-ns-shared@81e00000 { 525 reg = <0x0 0x81e00000 0x0 0x100000>; 526 no-map; 527 }; 528 529 gpu_prr_mem: gpu-prr@81f00000 { 530 reg = <0x0 0x81f00000 0x0 0x10000>; 531 no-map; 532 }; 533 534 tpm_control_mem: tpm-control@81f10000 { 535 reg = <0x0 0x81f10000 0x0 0x10000>; 536 no-map; 537 }; 538 539 usb_ucsi_shared_mem: usb-ucsi-shared@81f20000 { 540 reg = <0x0 0x81f20000 0x0 0x10000>; 541 no-map; 542 }; 543 544 pld_pep_mem: pld-pep@81f30000 { 545 reg = <0x0 0x81f30000 0x0 0x6000>; 546 no-map; 547 }; 548 549 pld_gmu_mem: pld-gmu@81f36000 { 550 reg = <0x0 0x81f36000 0x0 0x1000>; 551 no-map; 552 }; 553 554 pld_pdp_mem: pld-pdp@81f37000 { 555 reg = <0x0 0x81f37000 0x0 0x1000>; 556 no-map; 557 }; 558 559 tz_stat_mem: tz-stat@82700000 { 560 reg = <0x0 0x82700000 0x0 0x100000>; 561 no-map; 562 }; 563 564 xbl_tmp_buffer_mem: xbl-tmp-buffer@82800000 { 565 reg = <0x0 0x82800000 0x0 0xc00000>; 566 no-map; 567 }; 568 569 adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@84b00000 { 570 reg = <0x0 0x84b00000 0x0 0x800000>; 571 no-map; 572 }; 573 574 spu_secure_shared_memory_mem: spu-secure-shared-memory@85300000 { 575 reg = <0x0 0x85300000 0x0 0x80000>; 576 no-map; 577 }; 578 579 adsp_boot_dtb_mem: adsp-boot-dtb@866c0000 { 580 reg = <0x0 0x866c0000 0x0 0x40000>; 581 no-map; 582 }; 583 584 spss_region_mem: spss-region@86700000 { 585 reg = <0x0 0x86700000 0x0 0x400000>; 586 no-map; 587 }; 588 589 adsp_boot_mem: adsp-boot@86b00000 { 590 reg = <0x0 0x86b00000 0x0 0xc00000>; 591 no-map; 592 }; 593 594 video_mem: video@87700000 { 595 reg = <0x0 0x87700000 0x0 0x700000>; 596 no-map; 597 }; 598 599 adspslpi_mem: adspslpi@87e00000 { 600 reg = <0x0 0x87e00000 0x0 0x3a00000>; 601 no-map; 602 }; 603 604 q6_adsp_dtb_mem: q6-adsp-dtb@8b800000 { 605 reg = <0x0 0x8b800000 0x0 0x80000>; 606 no-map; 607 }; 608 609 cdsp_mem: cdsp@8b900000 { 610 reg = <0x0 0x8b900000 0x0 0x2000000>; 611 no-map; 612 }; 613 614 q6_cdsp_dtb_mem: q6-cdsp-dtb@8d900000 { 615 reg = <0x0 0x8d900000 0x0 0x80000>; 616 no-map; 617 }; 618 619 gpu_microcode_mem: gpu-microcode@8d9fe000 { 620 reg = <0x0 0x8d9fe000 0x0 0x2000>; 621 no-map; 622 }; 623 624 cvp_mem: cvp@8da00000 { 625 reg = <0x0 0x8da00000 0x0 0x700000>; 626 no-map; 627 }; 628 629 camera_mem: camera@8e100000 { 630 reg = <0x0 0x8e100000 0x0 0x800000>; 631 no-map; 632 }; 633 634 av1_encoder_mem: av1-encoder@8e900000 { 635 reg = <0x0 0x8e900000 0x0 0x700000>; 636 no-map; 637 }; 638 639 reserved-region@8f000000 { 640 reg = <0x0 0x8f000000 0x0 0xa00000>; 641 no-map; 642 }; 643 644 wpss_mem: wpss@8fa00000 { 645 reg = <0x0 0x8fa00000 0x0 0x1900000>; 646 no-map; 647 }; 648 649 q6_wpss_dtb_mem: q6-wpss-dtb@91300000 { 650 reg = <0x0 0x91300000 0x0 0x80000>; 651 no-map; 652 }; 653 654 xbl_sc_mem: xbl-sc@d8000000 { 655 reg = <0x0 0xd8000000 0x0 0x40000>; 656 no-map; 657 }; 658 659 reserved-region@d8040000 { 660 reg = <0x0 0xd8040000 0x0 0xa0000>; 661 no-map; 662 }; 663 664 qtee_mem: qtee@d80e0000 { 665 reg = <0x0 0xd80e0000 0x0 0x520000>; 666 no-map; 667 }; 668 669 ta_mem: ta@d8600000 { 670 reg = <0x0 0xd8600000 0x0 0x8a00000>; 671 no-map; 672 }; 673 674 tags_mem1: tags@e1000000 { 675 reg = <0x0 0xe1000000 0x0 0x26a0000>; 676 no-map; 677 }; 678 679 llcc_lpi_mem: llcc-lpi@ff800000 { 680 reg = <0x0 0xff800000 0x0 0x600000>; 681 no-map; 682 }; 683 684 smem_mem: smem@ffe00000 { 685 compatible = "qcom,smem"; 686 reg = <0x0 0xffe00000 0x0 0x200000>; 687 hwlocks = <&tcsr_mutex 3>; 688 no-map; 689 }; 690 }; 691 692 qup_opp_table_100mhz: opp-table-qup100mhz { 693 compatible = "operating-points-v2"; 694 695 opp-75000000 { 696 opp-hz = /bits/ 64 <75000000>; 697 required-opps = <&rpmhpd_opp_low_svs>; 698 }; 699 700 opp-100000000 { 701 opp-hz = /bits/ 64 <100000000>; 702 required-opps = <&rpmhpd_opp_svs>; 703 }; 704 }; 705 706 qup_opp_table_120mhz: opp-table-qup120mhz { 707 compatible = "operating-points-v2"; 708 709 opp-75000000 { 710 opp-hz = /bits/ 64 <75000000>; 711 required-opps = <&rpmhpd_opp_low_svs>; 712 }; 713 714 opp-120000000 { 715 opp-hz = /bits/ 64 <120000000>; 716 required-opps = <&rpmhpd_opp_svs>; 717 }; 718 }; 719 720 smp2p-adsp { 721 compatible = "qcom,smp2p"; 722 723 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 724 IPCC_MPROC_SIGNAL_SMP2P 725 IRQ_TYPE_EDGE_RISING>; 726 727 mboxes = <&ipcc IPCC_CLIENT_LPASS 728 IPCC_MPROC_SIGNAL_SMP2P>; 729 730 qcom,smem = <443>, <429>; 731 qcom,local-pid = <0>; 732 qcom,remote-pid = <2>; 733 734 smp2p_adsp_out: master-kernel { 735 qcom,entry-name = "master-kernel"; 736 #qcom,smem-state-cells = <1>; 737 }; 738 739 smp2p_adsp_in: slave-kernel { 740 qcom,entry-name = "slave-kernel"; 741 interrupt-controller; 742 #interrupt-cells = <2>; 743 }; 744 }; 745 746 smp2p-cdsp { 747 compatible = "qcom,smp2p"; 748 749 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 750 IPCC_MPROC_SIGNAL_SMP2P 751 IRQ_TYPE_EDGE_RISING>; 752 753 mboxes = <&ipcc IPCC_CLIENT_CDSP 754 IPCC_MPROC_SIGNAL_SMP2P>; 755 756 qcom,smem = <94>, <432>; 757 qcom,local-pid = <0>; 758 qcom,remote-pid = <5>; 759 760 smp2p_cdsp_out: master-kernel { 761 qcom,entry-name = "master-kernel"; 762 #qcom,smem-state-cells = <1>; 763 }; 764 765 smp2p_cdsp_in: slave-kernel { 766 qcom,entry-name = "slave-kernel"; 767 interrupt-controller; 768 #interrupt-cells = <2>; 769 }; 770 }; 771 772 soc: soc@0 { 773 compatible = "simple-bus"; 774 775 #address-cells = <2>; 776 #size-cells = <2>; 777 dma-ranges = <0 0 0 0 0x10 0>; 778 ranges = <0 0 0 0 0x10 0>; 779 780 gcc: clock-controller@100000 { 781 compatible = "qcom,x1e80100-gcc"; 782 reg = <0 0x00100000 0 0x200000>; 783 784 clocks = <&bi_tcxo_div2>, 785 <&sleep_clk>, 786 <&pcie3_phy>, 787 <&pcie4_phy>, 788 <&pcie5_phy>, 789 <&pcie6a_phy>, 790 <0>, 791 <&usb_1_ss0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 792 <&usb_1_ss1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 793 <&usb_1_ss2_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; 794 795 power-domains = <&rpmhpd RPMHPD_CX>; 796 #clock-cells = <1>; 797 #reset-cells = <1>; 798 #power-domain-cells = <1>; 799 }; 800 801 ipcc: mailbox@408000 { 802 compatible = "qcom,x1e80100-ipcc", "qcom,ipcc"; 803 reg = <0 0x00408000 0 0x1000>; 804 805 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 806 interrupt-controller; 807 #interrupt-cells = <3>; 808 809 #mbox-cells = <2>; 810 }; 811 812 gpi_dma2: dma-controller@800000 { 813 compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma"; 814 reg = <0 0x00800000 0 0x60000>; 815 816 interrupts = <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>, 817 <GIC_SPI 789 IRQ_TYPE_LEVEL_HIGH>, 818 <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>, 819 <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>, 820 <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>, 821 <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>, 822 <GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>, 823 <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>, 824 <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>, 825 <GIC_SPI 797 IRQ_TYPE_LEVEL_HIGH>, 826 <GIC_SPI 798 IRQ_TYPE_LEVEL_HIGH>, 827 <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH>; 828 829 dma-channels = <12>; 830 dma-channel-mask = <0x3e>; 831 #dma-cells = <3>; 832 833 iommus = <&apps_smmu 0x436 0x0>; 834 835 status = "disabled"; 836 }; 837 838 qupv3_2: geniqup@8c0000 { 839 compatible = "qcom,geni-se-qup"; 840 reg = <0 0x008c0000 0 0x2000>; 841 842 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 843 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 844 clock-names = "m-ahb", 845 "s-ahb"; 846 847 iommus = <&apps_smmu 0x423 0x0>; 848 849 #address-cells = <2>; 850 #size-cells = <2>; 851 ranges; 852 853 status = "disabled"; 854 855 i2c16: i2c@880000 { 856 compatible = "qcom,geni-i2c"; 857 reg = <0 0x00880000 0 0x4000>; 858 859 interrupts = <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>; 860 861 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 862 clock-names = "se"; 863 864 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 865 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 866 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 867 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 868 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 869 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 870 interconnect-names = "qup-core", 871 "qup-config", 872 "qup-memory"; 873 874 power-domains = <&rpmhpd RPMHPD_CX>; 875 required-opps = <&rpmhpd_opp_low_svs>; 876 877 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 878 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 879 dma-names = "tx", 880 "rx"; 881 882 pinctrl-0 = <&qup_i2c16_data_clk>; 883 pinctrl-names = "default"; 884 885 #address-cells = <1>; 886 #size-cells = <0>; 887 888 status = "disabled"; 889 }; 890 891 spi16: spi@880000 { 892 compatible = "qcom,geni-spi"; 893 reg = <0 0x00880000 0 0x4000>; 894 895 interrupts = <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>; 896 897 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 898 clock-names = "se"; 899 900 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 901 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 902 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 903 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 904 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 905 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 906 interconnect-names = "qup-core", 907 "qup-config", 908 "qup-memory"; 909 910 power-domains = <&rpmhpd RPMHPD_CX>; 911 operating-points-v2 = <&qup_opp_table_120mhz>; 912 913 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 914 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 915 dma-names = "tx", 916 "rx"; 917 918 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>; 919 pinctrl-names = "default"; 920 921 #address-cells = <1>; 922 #size-cells = <0>; 923 924 status = "disabled"; 925 }; 926 927 i2c17: i2c@884000 { 928 compatible = "qcom,geni-i2c"; 929 reg = <0 0x00884000 0 0x4000>; 930 931 interrupts = <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>; 932 933 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 934 clock-names = "se"; 935 936 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 937 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 938 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 939 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 940 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 941 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 942 interconnect-names = "qup-core", 943 "qup-config", 944 "qup-memory"; 945 946 power-domains = <&rpmhpd RPMHPD_CX>; 947 required-opps = <&rpmhpd_opp_low_svs>; 948 949 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 950 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 951 dma-names = "tx", 952 "rx"; 953 954 pinctrl-0 = <&qup_i2c17_data_clk>; 955 pinctrl-names = "default"; 956 957 #address-cells = <1>; 958 #size-cells = <0>; 959 960 status = "disabled"; 961 }; 962 963 spi17: spi@884000 { 964 compatible = "qcom,geni-spi"; 965 reg = <0 0x00884000 0 0x4000>; 966 967 interrupts = <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>; 968 969 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 970 clock-names = "se"; 971 972 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 973 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 974 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 975 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 976 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 977 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 978 interconnect-names = "qup-core", 979 "qup-config", 980 "qup-memory"; 981 982 power-domains = <&rpmhpd RPMHPD_CX>; 983 operating-points-v2 = <&qup_opp_table_120mhz>; 984 985 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 986 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 987 dma-names = "tx", 988 "rx"; 989 990 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>; 991 pinctrl-names = "default"; 992 993 #address-cells = <1>; 994 #size-cells = <0>; 995 996 status = "disabled"; 997 }; 998 999 i2c18: i2c@888000 { 1000 compatible = "qcom,geni-i2c"; 1001 reg = <0 0x00888000 0 0x4000>; 1002 1003 interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>; 1004 1005 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1006 clock-names = "se"; 1007 1008 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1009 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1010 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1011 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1012 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1013 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1014 interconnect-names = "qup-core", 1015 "qup-config", 1016 "qup-memory"; 1017 1018 power-domains = <&rpmhpd RPMHPD_CX>; 1019 required-opps = <&rpmhpd_opp_low_svs>; 1020 1021 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 1022 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 1023 dma-names = "tx", 1024 "rx"; 1025 1026 pinctrl-0 = <&qup_i2c18_data_clk>; 1027 pinctrl-names = "default"; 1028 1029 #address-cells = <1>; 1030 #size-cells = <0>; 1031 1032 status = "disabled"; 1033 }; 1034 1035 spi18: spi@888000 { 1036 compatible = "qcom,geni-spi"; 1037 reg = <0 0x00888000 0 0x4000>; 1038 1039 interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>; 1040 1041 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1042 clock-names = "se"; 1043 1044 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1045 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1046 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1047 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1048 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1049 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1050 interconnect-names = "qup-core", 1051 "qup-config", 1052 "qup-memory"; 1053 1054 power-domains = <&rpmhpd RPMHPD_CX>; 1055 operating-points-v2 = <&qup_opp_table_100mhz>; 1056 1057 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1058 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1059 dma-names = "tx", 1060 "rx"; 1061 1062 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>; 1063 pinctrl-names = "default"; 1064 1065 #address-cells = <1>; 1066 #size-cells = <0>; 1067 1068 status = "disabled"; 1069 }; 1070 1071 i2c19: i2c@88c000 { 1072 compatible = "qcom,geni-i2c"; 1073 reg = <0 0x0088c000 0 0x4000>; 1074 1075 interrupts = <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>; 1076 1077 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1078 clock-names = "se"; 1079 1080 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1081 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1082 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1083 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1084 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1085 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1086 interconnect-names = "qup-core", 1087 "qup-config", 1088 "qup-memory"; 1089 1090 power-domains = <&rpmhpd RPMHPD_CX>; 1091 required-opps = <&rpmhpd_opp_low_svs>; 1092 1093 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1094 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1095 dma-names = "tx", 1096 "rx"; 1097 1098 pinctrl-0 = <&qup_i2c19_data_clk>; 1099 pinctrl-names = "default"; 1100 1101 #address-cells = <1>; 1102 #size-cells = <0>; 1103 1104 status = "disabled"; 1105 }; 1106 1107 spi19: spi@88c000 { 1108 compatible = "qcom,geni-spi"; 1109 reg = <0 0x0088c000 0 0x4000>; 1110 1111 interrupts = <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>; 1112 1113 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1114 clock-names = "se"; 1115 1116 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1117 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1118 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1119 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1120 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1121 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1122 interconnect-names = "qup-core", 1123 "qup-config", 1124 "qup-memory"; 1125 1126 power-domains = <&rpmhpd RPMHPD_CX>; 1127 operating-points-v2 = <&qup_opp_table_100mhz>; 1128 1129 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1130 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1131 dma-names = "tx", 1132 "rx"; 1133 1134 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>; 1135 pinctrl-names = "default"; 1136 1137 #address-cells = <1>; 1138 #size-cells = <0>; 1139 1140 status = "disabled"; 1141 }; 1142 1143 i2c20: i2c@890000 { 1144 compatible = "qcom,geni-i2c"; 1145 reg = <0 0x00890000 0 0x4000>; 1146 1147 interrupts = <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>; 1148 1149 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1150 clock-names = "se"; 1151 1152 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1153 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1154 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1155 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1156 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1157 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1158 interconnect-names = "qup-core", 1159 "qup-config", 1160 "qup-memory"; 1161 1162 power-domains = <&rpmhpd RPMHPD_CX>; 1163 required-opps = <&rpmhpd_opp_low_svs>; 1164 1165 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1166 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1167 dma-names = "tx", 1168 "rx"; 1169 1170 pinctrl-0 = <&qup_i2c20_data_clk>; 1171 pinctrl-names = "default"; 1172 1173 #address-cells = <1>; 1174 #size-cells = <0>; 1175 1176 status = "disabled"; 1177 }; 1178 1179 spi20: spi@890000 { 1180 compatible = "qcom,geni-spi"; 1181 reg = <0 0x00890000 0 0x4000>; 1182 1183 interrupts = <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>; 1184 1185 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1186 clock-names = "se"; 1187 1188 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1189 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1190 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1191 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1192 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1193 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1194 interconnect-names = "qup-core", 1195 "qup-config", 1196 "qup-memory"; 1197 1198 power-domains = <&rpmhpd RPMHPD_CX>; 1199 operating-points-v2 = <&qup_opp_table_100mhz>; 1200 1201 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1202 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1203 dma-names = "tx", 1204 "rx"; 1205 1206 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>; 1207 pinctrl-names = "default"; 1208 1209 #address-cells = <1>; 1210 #size-cells = <0>; 1211 1212 status = "disabled"; 1213 }; 1214 1215 i2c21: i2c@894000 { 1216 compatible = "qcom,geni-i2c"; 1217 reg = <0 0x00894000 0 0x4000>; 1218 1219 interrupts = <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>; 1220 1221 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1222 clock-names = "se"; 1223 1224 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1225 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1226 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1227 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1228 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1229 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1230 interconnect-names = "qup-core", 1231 "qup-config", 1232 "qup-memory"; 1233 1234 power-domains = <&rpmhpd RPMHPD_CX>; 1235 required-opps = <&rpmhpd_opp_low_svs>; 1236 1237 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1238 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1239 dma-names = "tx", 1240 "rx"; 1241 1242 pinctrl-0 = <&qup_i2c21_data_clk>; 1243 pinctrl-names = "default"; 1244 1245 #address-cells = <1>; 1246 #size-cells = <0>; 1247 1248 status = "disabled"; 1249 }; 1250 1251 spi21: spi@894000 { 1252 compatible = "qcom,geni-spi"; 1253 reg = <0 0x00894000 0 0x4000>; 1254 1255 interrupts = <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>; 1256 1257 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1258 clock-names = "se"; 1259 1260 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1261 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1262 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1263 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1264 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1265 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1266 interconnect-names = "qup-core", 1267 "qup-config", 1268 "qup-memory"; 1269 1270 power-domains = <&rpmhpd RPMHPD_CX>; 1271 operating-points-v2 = <&qup_opp_table_100mhz>; 1272 1273 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1274 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1275 dma-names = "tx", 1276 "rx"; 1277 1278 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>; 1279 pinctrl-names = "default"; 1280 1281 #address-cells = <1>; 1282 #size-cells = <0>; 1283 1284 status = "disabled"; 1285 }; 1286 1287 uart21: serial@894000 { 1288 compatible = "qcom,geni-uart"; 1289 reg = <0 0x00894000 0 0x4000>; 1290 1291 interrupts = <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>; 1292 1293 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1294 clock-names = "se"; 1295 1296 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1297 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1298 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1299 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1300 interconnect-names = "qup-core", 1301 "qup-config"; 1302 1303 power-domains = <&rpmhpd RPMHPD_CX>; 1304 operating-points-v2 = <&qup_opp_table_100mhz>; 1305 1306 pinctrl-0 = <&qup_uart21_default>; 1307 pinctrl-names = "default"; 1308 1309 status = "disabled"; 1310 }; 1311 1312 i2c22: i2c@898000 { 1313 compatible = "qcom,geni-i2c"; 1314 reg = <0 0x00898000 0 0x4000>; 1315 1316 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 1317 1318 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1319 clock-names = "se"; 1320 1321 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1322 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1323 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1324 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1325 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1326 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1327 interconnect-names = "qup-core", 1328 "qup-config", 1329 "qup-memory"; 1330 1331 power-domains = <&rpmhpd RPMHPD_CX>; 1332 required-opps = <&rpmhpd_opp_low_svs>; 1333 1334 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>, 1335 <&gpi_dma2 1 6 QCOM_GPI_I2C>; 1336 dma-names = "tx", 1337 "rx"; 1338 1339 pinctrl-0 = <&qup_i2c22_data_clk>; 1340 pinctrl-names = "default"; 1341 1342 #address-cells = <1>; 1343 #size-cells = <0>; 1344 1345 status = "disabled"; 1346 }; 1347 1348 spi22: spi@898000 { 1349 compatible = "qcom,geni-spi"; 1350 reg = <0 0x00898000 0 0x4000>; 1351 1352 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 1353 1354 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1355 clock-names = "se"; 1356 1357 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1358 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1359 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1360 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1361 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1362 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1363 interconnect-names = "qup-core", 1364 "qup-config", 1365 "qup-memory"; 1366 1367 power-domains = <&rpmhpd RPMHPD_CX>; 1368 operating-points-v2 = <&qup_opp_table_100mhz>; 1369 1370 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>, 1371 <&gpi_dma2 1 6 QCOM_GPI_SPI>; 1372 dma-names = "tx", 1373 "rx"; 1374 1375 pinctrl-0 = <&qup_spi22_data_clk>, <&qup_spi22_cs>; 1376 pinctrl-names = "default"; 1377 1378 #address-cells = <1>; 1379 #size-cells = <0>; 1380 1381 status = "disabled"; 1382 }; 1383 1384 i2c23: i2c@89c000 { 1385 compatible = "qcom,geni-i2c"; 1386 reg = <0 0x0089c000 0 0x4000>; 1387 1388 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1389 1390 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1391 clock-names = "se"; 1392 1393 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1394 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1395 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1396 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1397 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1398 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1399 interconnect-names = "qup-core", 1400 "qup-config", 1401 "qup-memory"; 1402 1403 power-domains = <&rpmhpd RPMHPD_CX>; 1404 required-opps = <&rpmhpd_opp_low_svs>; 1405 1406 dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>, 1407 <&gpi_dma2 1 7 QCOM_GPI_I2C>; 1408 dma-names = "tx", 1409 "rx"; 1410 1411 pinctrl-0 = <&qup_i2c23_data_clk>; 1412 pinctrl-names = "default"; 1413 1414 #address-cells = <1>; 1415 #size-cells = <0>; 1416 1417 status = "disabled"; 1418 }; 1419 1420 spi23: spi@89c000 { 1421 compatible = "qcom,geni-spi"; 1422 reg = <0 0x0089c000 0 0x4000>; 1423 1424 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1425 1426 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1427 clock-names = "se"; 1428 1429 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1430 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1431 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1432 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1433 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1434 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1435 interconnect-names = "qup-core", 1436 "qup-config", 1437 "qup-memory"; 1438 1439 power-domains = <&rpmhpd RPMHPD_CX>; 1440 operating-points-v2 = <&qup_opp_table_100mhz>; 1441 1442 dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>, 1443 <&gpi_dma2 1 7 QCOM_GPI_SPI>; 1444 dma-names = "tx", 1445 "rx"; 1446 1447 pinctrl-0 = <&qup_spi23_data_clk>, <&qup_spi23_cs>; 1448 pinctrl-names = "default"; 1449 1450 #address-cells = <1>; 1451 #size-cells = <0>; 1452 1453 status = "disabled"; 1454 }; 1455 }; 1456 1457 gpi_dma1: dma-controller@a00000 { 1458 compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma"; 1459 reg = <0 0x00a00000 0 0x60000>; 1460 1461 interrupts = <GIC_SPI 776 IRQ_TYPE_LEVEL_HIGH>, 1462 <GIC_SPI 777 IRQ_TYPE_LEVEL_HIGH>, 1463 <GIC_SPI 778 IRQ_TYPE_LEVEL_HIGH>, 1464 <GIC_SPI 779 IRQ_TYPE_LEVEL_HIGH>, 1465 <GIC_SPI 780 IRQ_TYPE_LEVEL_HIGH>, 1466 <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>, 1467 <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>, 1468 <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>, 1469 <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>, 1470 <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>, 1471 <GIC_SPI 786 IRQ_TYPE_LEVEL_HIGH>, 1472 <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>; 1473 1474 dma-channels = <12>; 1475 dma-channel-mask = <0x3e>; 1476 #dma-cells = <3>; 1477 1478 iommus = <&apps_smmu 0x136 0x0>; 1479 1480 status = "disabled"; 1481 }; 1482 1483 qupv3_1: geniqup@ac0000 { 1484 compatible = "qcom,geni-se-qup"; 1485 reg = <0 0x00ac0000 0 0x2000>; 1486 1487 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1488 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1489 clock-names = "m-ahb", 1490 "s-ahb"; 1491 1492 iommus = <&apps_smmu 0x123 0x0>; 1493 1494 #address-cells = <2>; 1495 #size-cells = <2>; 1496 ranges; 1497 1498 status = "disabled"; 1499 1500 i2c8: i2c@a80000 { 1501 compatible = "qcom,geni-i2c"; 1502 reg = <0 0x00a80000 0 0x4000>; 1503 1504 interrupts = <GIC_SPI 800 IRQ_TYPE_LEVEL_HIGH>; 1505 1506 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1507 clock-names = "se"; 1508 1509 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1510 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1511 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1512 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1513 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1514 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1515 interconnect-names = "qup-core", 1516 "qup-config", 1517 "qup-memory"; 1518 1519 power-domains = <&rpmhpd RPMHPD_CX>; 1520 required-opps = <&rpmhpd_opp_low_svs>; 1521 1522 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1523 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1524 dma-names = "tx", 1525 "rx"; 1526 1527 pinctrl-0 = <&qup_i2c8_data_clk>; 1528 pinctrl-names = "default"; 1529 1530 #address-cells = <1>; 1531 #size-cells = <0>; 1532 1533 status = "disabled"; 1534 }; 1535 1536 spi8: spi@a80000 { 1537 compatible = "qcom,geni-spi"; 1538 reg = <0 0x00a80000 0 0x4000>; 1539 1540 interrupts = <GIC_SPI 800 IRQ_TYPE_LEVEL_HIGH>; 1541 1542 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1543 clock-names = "se"; 1544 1545 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1546 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1547 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1548 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1549 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1550 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1551 interconnect-names = "qup-core", 1552 "qup-config", 1553 "qup-memory"; 1554 1555 power-domains = <&rpmhpd RPMHPD_CX>; 1556 operating-points-v2 = <&qup_opp_table_120mhz>; 1557 1558 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1559 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1560 dma-names = "tx", 1561 "rx"; 1562 1563 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1564 pinctrl-names = "default"; 1565 1566 #address-cells = <1>; 1567 #size-cells = <0>; 1568 1569 status = "disabled"; 1570 }; 1571 1572 i2c9: i2c@a84000 { 1573 compatible = "qcom,geni-i2c"; 1574 reg = <0 0x00a84000 0 0x4000>; 1575 1576 interrupts = <GIC_SPI 801 IRQ_TYPE_LEVEL_HIGH>; 1577 1578 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1579 clock-names = "se"; 1580 1581 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1582 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1583 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1584 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1585 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1586 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1587 interconnect-names = "qup-core", 1588 "qup-config", 1589 "qup-memory"; 1590 1591 power-domains = <&rpmhpd RPMHPD_CX>; 1592 required-opps = <&rpmhpd_opp_low_svs>; 1593 1594 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1595 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1596 dma-names = "tx", 1597 "rx"; 1598 1599 pinctrl-0 = <&qup_i2c9_data_clk>; 1600 pinctrl-names = "default"; 1601 1602 #address-cells = <1>; 1603 #size-cells = <0>; 1604 1605 status = "disabled"; 1606 }; 1607 1608 spi9: spi@a84000 { 1609 compatible = "qcom,geni-spi"; 1610 reg = <0 0x00a84000 0 0x4000>; 1611 1612 interrupts = <GIC_SPI 801 IRQ_TYPE_LEVEL_HIGH>; 1613 1614 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1615 clock-names = "se"; 1616 1617 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1618 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1619 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1620 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1621 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1622 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1623 interconnect-names = "qup-core", 1624 "qup-config", 1625 "qup-memory"; 1626 1627 power-domains = <&rpmhpd RPMHPD_CX>; 1628 operating-points-v2 = <&qup_opp_table_120mhz>; 1629 1630 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1631 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1632 dma-names = "tx", 1633 "rx"; 1634 1635 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1636 pinctrl-names = "default"; 1637 1638 #address-cells = <1>; 1639 #size-cells = <0>; 1640 1641 status = "disabled"; 1642 }; 1643 1644 i2c10: i2c@a88000 { 1645 compatible = "qcom,geni-i2c"; 1646 reg = <0 0x00a88000 0 0x4000>; 1647 1648 interrupts = <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>; 1649 1650 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1651 clock-names = "se"; 1652 1653 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1654 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1655 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1656 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1657 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1658 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1659 interconnect-names = "qup-core", 1660 "qup-config", 1661 "qup-memory"; 1662 1663 power-domains = <&rpmhpd RPMHPD_CX>; 1664 required-opps = <&rpmhpd_opp_low_svs>; 1665 1666 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1667 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1668 dma-names = "tx", 1669 "rx"; 1670 1671 pinctrl-0 = <&qup_i2c10_data_clk>; 1672 pinctrl-names = "default"; 1673 1674 #address-cells = <1>; 1675 #size-cells = <0>; 1676 1677 status = "disabled"; 1678 }; 1679 1680 spi10: spi@a88000 { 1681 compatible = "qcom,geni-spi"; 1682 reg = <0 0x00a88000 0 0x4000>; 1683 1684 interrupts = <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>; 1685 1686 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1687 clock-names = "se"; 1688 1689 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1690 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1691 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1692 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1693 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1694 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1695 interconnect-names = "qup-core", 1696 "qup-config", 1697 "qup-memory"; 1698 1699 power-domains = <&rpmhpd RPMHPD_CX>; 1700 operating-points-v2 = <&qup_opp_table_100mhz>; 1701 1702 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1703 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1704 dma-names = "tx", 1705 "rx"; 1706 1707 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1708 pinctrl-names = "default"; 1709 1710 #address-cells = <1>; 1711 #size-cells = <0>; 1712 1713 status = "disabled"; 1714 }; 1715 1716 i2c11: i2c@a8c000 { 1717 compatible = "qcom,geni-i2c"; 1718 reg = <0 0x00a8c000 0 0x4000>; 1719 1720 interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>; 1721 1722 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1723 clock-names = "se"; 1724 1725 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1726 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1727 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1728 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1729 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1730 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1731 interconnect-names = "qup-core", 1732 "qup-config", 1733 "qup-memory"; 1734 1735 power-domains = <&rpmhpd RPMHPD_CX>; 1736 required-opps = <&rpmhpd_opp_low_svs>; 1737 1738 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1739 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1740 dma-names = "tx", 1741 "rx"; 1742 1743 pinctrl-0 = <&qup_i2c11_data_clk>; 1744 pinctrl-names = "default"; 1745 1746 #address-cells = <1>; 1747 #size-cells = <0>; 1748 1749 status = "disabled"; 1750 }; 1751 1752 spi11: spi@a8c000 { 1753 compatible = "qcom,geni-spi"; 1754 reg = <0 0x00a8c000 0 0x4000>; 1755 1756 interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>; 1757 1758 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1759 clock-names = "se"; 1760 1761 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1762 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1763 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1764 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1765 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1766 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1767 interconnect-names = "qup-core", 1768 "qup-config", 1769 "qup-memory"; 1770 1771 power-domains = <&rpmhpd RPMHPD_CX>; 1772 operating-points-v2 = <&qup_opp_table_100mhz>; 1773 1774 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1775 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1776 dma-names = "tx", 1777 "rx"; 1778 1779 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1780 pinctrl-names = "default"; 1781 1782 #address-cells = <1>; 1783 #size-cells = <0>; 1784 1785 status = "disabled"; 1786 }; 1787 1788 i2c12: i2c@a90000 { 1789 compatible = "qcom,geni-i2c"; 1790 reg = <0 0x00a90000 0 0x4000>; 1791 1792 interrupts = <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>; 1793 1794 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1795 clock-names = "se"; 1796 1797 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1798 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1799 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1800 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1801 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1802 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1803 interconnect-names = "qup-core", 1804 "qup-config", 1805 "qup-memory"; 1806 1807 power-domains = <&rpmhpd RPMHPD_CX>; 1808 required-opps = <&rpmhpd_opp_low_svs>; 1809 1810 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1811 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1812 dma-names = "tx", 1813 "rx"; 1814 1815 pinctrl-0 = <&qup_i2c12_data_clk>; 1816 pinctrl-names = "default"; 1817 1818 #address-cells = <1>; 1819 #size-cells = <0>; 1820 1821 status = "disabled"; 1822 }; 1823 1824 spi12: spi@a90000 { 1825 compatible = "qcom,geni-spi"; 1826 reg = <0 0x00a90000 0 0x4000>; 1827 1828 interrupts = <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>; 1829 1830 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1831 clock-names = "se"; 1832 1833 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1834 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1835 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1836 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1837 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1838 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1839 interconnect-names = "qup-core", 1840 "qup-config", 1841 "qup-memory"; 1842 1843 power-domains = <&rpmhpd RPMHPD_CX>; 1844 operating-points-v2 = <&qup_opp_table_100mhz>; 1845 1846 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1847 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1848 dma-names = "tx", 1849 "rx"; 1850 1851 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1852 pinctrl-names = "default"; 1853 1854 #address-cells = <1>; 1855 #size-cells = <0>; 1856 1857 status = "disabled"; 1858 }; 1859 1860 i2c13: i2c@a94000 { 1861 compatible = "qcom,geni-i2c"; 1862 reg = <0 0x00a94000 0 0x4000>; 1863 1864 interrupts = <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>; 1865 1866 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1867 clock-names = "se"; 1868 1869 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1870 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1871 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1872 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1873 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1874 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1875 interconnect-names = "qup-core", 1876 "qup-config", 1877 "qup-memory"; 1878 1879 power-domains = <&rpmhpd RPMHPD_CX>; 1880 required-opps = <&rpmhpd_opp_low_svs>; 1881 1882 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1883 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1884 dma-names = "tx", 1885 "rx"; 1886 1887 pinctrl-0 = <&qup_i2c13_data_clk>; 1888 pinctrl-names = "default"; 1889 1890 #address-cells = <1>; 1891 #size-cells = <0>; 1892 1893 status = "disabled"; 1894 }; 1895 1896 spi13: spi@a94000 { 1897 compatible = "qcom,geni-spi"; 1898 reg = <0 0x00a94000 0 0x4000>; 1899 1900 interrupts = <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>; 1901 1902 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1903 clock-names = "se"; 1904 1905 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1906 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1907 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1908 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1909 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1910 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1911 interconnect-names = "qup-core", 1912 "qup-config", 1913 "qup-memory"; 1914 1915 power-domains = <&rpmhpd RPMHPD_CX>; 1916 operating-points-v2 = <&qup_opp_table_100mhz>; 1917 1918 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1919 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1920 dma-names = "tx", 1921 "rx"; 1922 1923 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1924 pinctrl-names = "default"; 1925 1926 #address-cells = <1>; 1927 #size-cells = <0>; 1928 1929 status = "disabled"; 1930 }; 1931 1932 i2c14: i2c@a98000 { 1933 compatible = "qcom,geni-i2c"; 1934 reg = <0 0x00a98000 0 0x4000>; 1935 1936 interrupts = <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>; 1937 1938 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1939 clock-names = "se"; 1940 1941 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1942 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1943 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1944 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1945 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1946 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1947 interconnect-names = "qup-core", 1948 "qup-config", 1949 "qup-memory"; 1950 1951 power-domains = <&rpmhpd RPMHPD_CX>; 1952 required-opps = <&rpmhpd_opp_low_svs>; 1953 1954 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1955 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1956 dma-names = "tx", 1957 "rx"; 1958 1959 pinctrl-0 = <&qup_i2c14_data_clk>; 1960 pinctrl-names = "default"; 1961 1962 #address-cells = <1>; 1963 #size-cells = <0>; 1964 1965 status = "disabled"; 1966 }; 1967 1968 spi14: spi@a98000 { 1969 compatible = "qcom,geni-spi"; 1970 reg = <0 0x00a98000 0 0x4000>; 1971 1972 interrupts = <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>; 1973 1974 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1975 clock-names = "se"; 1976 1977 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1978 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1979 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1980 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1981 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1982 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1983 interconnect-names = "qup-core", 1984 "qup-config", 1985 "qup-memory"; 1986 1987 power-domains = <&rpmhpd RPMHPD_CX>; 1988 operating-points-v2 = <&qup_opp_table_100mhz>; 1989 1990 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1991 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1992 dma-names = "tx", 1993 "rx"; 1994 1995 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1996 pinctrl-names = "default"; 1997 1998 #address-cells = <1>; 1999 #size-cells = <0>; 2000 2001 status = "disabled"; 2002 }; 2003 2004 uart14: serial@a98000 { 2005 compatible = "qcom,geni-uart"; 2006 reg = <0 0x00a98000 0 0x4000>; 2007 2008 interrupts = <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>; 2009 2010 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2011 clock-names = "se"; 2012 2013 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2014 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2015 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2016 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 2017 interconnect-names = "qup-core", 2018 "qup-config"; 2019 2020 power-domains = <&rpmhpd RPMHPD_CX>; 2021 operating-points-v2 = <&qup_opp_table_100mhz>; 2022 2023 pinctrl-0 = <&qup_uart14_default>; 2024 pinctrl-names = "default"; 2025 2026 status = "disabled"; 2027 }; 2028 2029 i2c15: i2c@a9c000 { 2030 compatible = "qcom,geni-i2c"; 2031 reg = <0 0x00a9c000 0 0x4000>; 2032 2033 interrupts = <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>; 2034 2035 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2036 clock-names = "se"; 2037 2038 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2039 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2040 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2041 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2042 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2043 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2044 interconnect-names = "qup-core", 2045 "qup-config", 2046 "qup-memory"; 2047 2048 power-domains = <&rpmhpd RPMHPD_CX>; 2049 required-opps = <&rpmhpd_opp_low_svs>; 2050 2051 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 2052 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 2053 dma-names = "tx", 2054 "rx"; 2055 2056 pinctrl-0 = <&qup_i2c15_data_clk>; 2057 pinctrl-names = "default"; 2058 2059 #address-cells = <1>; 2060 #size-cells = <0>; 2061 2062 status = "disabled"; 2063 }; 2064 2065 spi15: spi@a9c000 { 2066 compatible = "qcom,geni-spi"; 2067 reg = <0 0x00a9c000 0 0x4000>; 2068 2069 interrupts = <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>; 2070 2071 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2072 clock-names = "se"; 2073 2074 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2075 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2076 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2077 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2078 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2079 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2080 interconnect-names = "qup-core", 2081 "qup-config", 2082 "qup-memory"; 2083 2084 power-domains = <&rpmhpd RPMHPD_CX>; 2085 operating-points-v2 = <&qup_opp_table_100mhz>; 2086 2087 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 2088 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 2089 dma-names = "tx", 2090 "rx"; 2091 2092 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 2093 pinctrl-names = "default"; 2094 2095 #address-cells = <1>; 2096 #size-cells = <0>; 2097 2098 status = "disabled"; 2099 }; 2100 }; 2101 2102 gpi_dma0: dma-controller@b00000 { 2103 compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma"; 2104 reg = <0 0x00b00000 0 0x60000>; 2105 2106 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 2107 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 2108 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 2109 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 2110 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 2111 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 2112 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 2113 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 2114 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 2115 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 2116 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 2117 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 2118 2119 dma-channels = <12>; 2120 dma-channel-mask = <0x3e>; 2121 #dma-cells = <3>; 2122 2123 iommus = <&apps_smmu 0x456 0x0>; 2124 2125 status = "disabled"; 2126 }; 2127 2128 qupv3_0: geniqup@bc0000 { 2129 compatible = "qcom,geni-se-qup"; 2130 reg = <0 0x00bc0000 0 0x2000>; 2131 2132 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 2133 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 2134 clock-names = "m-ahb", 2135 "s-ahb"; 2136 2137 iommus = <&apps_smmu 0x443 0x0>; 2138 #address-cells = <2>; 2139 #size-cells = <2>; 2140 ranges; 2141 2142 status = "disabled"; 2143 2144 i2c0: i2c@b80000 { 2145 compatible = "qcom,geni-i2c"; 2146 reg = <0 0x00b80000 0 0x4000>; 2147 2148 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 2149 2150 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 2151 clock-names = "se"; 2152 2153 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2154 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2155 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2156 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2157 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2158 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2159 interconnect-names = "qup-core", 2160 "qup-config", 2161 "qup-memory"; 2162 2163 power-domains = <&rpmhpd RPMHPD_CX>; 2164 required-opps = <&rpmhpd_opp_low_svs>; 2165 2166 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 2167 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 2168 dma-names = "tx", 2169 "rx"; 2170 2171 pinctrl-0 = <&qup_i2c0_data_clk>; 2172 pinctrl-names = "default"; 2173 2174 #address-cells = <1>; 2175 #size-cells = <0>; 2176 2177 status = "disabled"; 2178 }; 2179 2180 spi0: spi@b80000 { 2181 compatible = "qcom,geni-spi"; 2182 reg = <0 0x00b80000 0 0x4000>; 2183 2184 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 2185 2186 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 2187 clock-names = "se"; 2188 2189 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2190 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2191 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2192 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2193 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2194 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2195 interconnect-names = "qup-core", 2196 "qup-config", 2197 "qup-memory"; 2198 2199 power-domains = <&rpmhpd RPMHPD_CX>; 2200 operating-points-v2 = <&qup_opp_table_120mhz>; 2201 2202 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 2203 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 2204 dma-names = "tx", 2205 "rx"; 2206 2207 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 2208 pinctrl-names = "default"; 2209 2210 #address-cells = <1>; 2211 #size-cells = <0>; 2212 2213 status = "disabled"; 2214 }; 2215 2216 i2c1: i2c@b84000 { 2217 compatible = "qcom,geni-i2c"; 2218 reg = <0 0x00b84000 0 0x4000>; 2219 2220 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 2221 2222 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 2223 clock-names = "se"; 2224 2225 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2226 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2227 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2228 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2229 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2230 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2231 interconnect-names = "qup-core", 2232 "qup-config", 2233 "qup-memory"; 2234 2235 power-domains = <&rpmhpd RPMHPD_CX>; 2236 required-opps = <&rpmhpd_opp_low_svs>; 2237 2238 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 2239 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 2240 dma-names = "tx", 2241 "rx"; 2242 2243 pinctrl-0 = <&qup_i2c1_data_clk>; 2244 pinctrl-names = "default"; 2245 2246 #address-cells = <1>; 2247 #size-cells = <0>; 2248 2249 status = "disabled"; 2250 }; 2251 2252 spi1: spi@b84000 { 2253 compatible = "qcom,geni-spi"; 2254 reg = <0 0x00b84000 0 0x4000>; 2255 2256 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 2257 2258 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 2259 clock-names = "se"; 2260 2261 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2262 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2263 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2264 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2265 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2266 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2267 interconnect-names = "qup-core", 2268 "qup-config", 2269 "qup-memory"; 2270 2271 power-domains = <&rpmhpd RPMHPD_CX>; 2272 operating-points-v2 = <&qup_opp_table_120mhz>; 2273 2274 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 2275 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 2276 dma-names = "tx", 2277 "rx"; 2278 2279 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 2280 pinctrl-names = "default"; 2281 2282 #address-cells = <1>; 2283 #size-cells = <0>; 2284 2285 status = "disabled"; 2286 }; 2287 2288 i2c2: i2c@b88000 { 2289 compatible = "qcom,geni-i2c"; 2290 reg = <0 0x00b88000 0 0x4000>; 2291 2292 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 2293 2294 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 2295 clock-names = "se"; 2296 2297 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2298 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2299 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2300 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2301 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2302 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2303 interconnect-names = "qup-core", 2304 "qup-config", 2305 "qup-memory"; 2306 2307 power-domains = <&rpmhpd RPMHPD_CX>; 2308 required-opps = <&rpmhpd_opp_low_svs>; 2309 2310 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 2311 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 2312 dma-names = "tx", 2313 "rx"; 2314 2315 pinctrl-0 = <&qup_i2c2_data_clk>; 2316 pinctrl-names = "default"; 2317 2318 #address-cells = <1>; 2319 #size-cells = <0>; 2320 2321 status = "disabled"; 2322 }; 2323 2324 uart2: serial@b88000 { 2325 compatible = "qcom,geni-uart"; 2326 reg = <0 0x00b88000 0 0x4000>; 2327 2328 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 2329 2330 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 2331 clock-names = "se"; 2332 2333 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2334 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2335 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2336 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 2337 interconnect-names = "qup-core", 2338 "qup-config"; 2339 2340 power-domains = <&rpmhpd RPMHPD_CX>; 2341 operating-points-v2 = <&qup_opp_table_100mhz>; 2342 2343 pinctrl-0 = <&qup_uart2_default>; 2344 pinctrl-names = "default"; 2345 2346 status = "disabled"; 2347 }; 2348 2349 spi2: spi@b88000 { 2350 compatible = "qcom,geni-spi"; 2351 reg = <0 0x00b88000 0 0x4000>; 2352 2353 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 2354 2355 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 2356 clock-names = "se"; 2357 2358 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2359 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2360 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2361 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2362 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2363 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2364 interconnect-names = "qup-core", 2365 "qup-config", 2366 "qup-memory"; 2367 2368 power-domains = <&rpmhpd RPMHPD_CX>; 2369 operating-points-v2 = <&qup_opp_table_100mhz>; 2370 2371 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 2372 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 2373 dma-names = "tx", 2374 "rx"; 2375 2376 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 2377 pinctrl-names = "default"; 2378 2379 #address-cells = <1>; 2380 #size-cells = <0>; 2381 2382 status = "disabled"; 2383 }; 2384 2385 i2c3: i2c@b8c000 { 2386 compatible = "qcom,geni-i2c"; 2387 reg = <0 0x00b8c000 0 0x4000>; 2388 2389 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 2390 2391 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 2392 clock-names = "se"; 2393 2394 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2395 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2396 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2397 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2398 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2399 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2400 interconnect-names = "qup-core", 2401 "qup-config", 2402 "qup-memory"; 2403 2404 power-domains = <&rpmhpd RPMHPD_CX>; 2405 required-opps = <&rpmhpd_opp_low_svs>; 2406 2407 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 2408 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 2409 dma-names = "tx", 2410 "rx"; 2411 2412 pinctrl-0 = <&qup_i2c3_data_clk>; 2413 pinctrl-names = "default"; 2414 2415 #address-cells = <1>; 2416 #size-cells = <0>; 2417 2418 status = "disabled"; 2419 }; 2420 2421 spi3: spi@b8c000 { 2422 compatible = "qcom,geni-spi"; 2423 reg = <0 0x00b8c000 0 0x4000>; 2424 2425 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 2426 2427 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 2428 clock-names = "se"; 2429 2430 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2431 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2432 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2433 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2434 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2435 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2436 interconnect-names = "qup-core", 2437 "qup-config", 2438 "qup-memory"; 2439 2440 power-domains = <&rpmhpd RPMHPD_CX>; 2441 operating-points-v2 = <&qup_opp_table_100mhz>; 2442 2443 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 2444 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 2445 dma-names = "tx", 2446 "rx"; 2447 2448 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 2449 pinctrl-names = "default"; 2450 2451 #address-cells = <1>; 2452 #size-cells = <0>; 2453 2454 status = "disabled"; 2455 }; 2456 2457 i2c4: i2c@b90000 { 2458 compatible = "qcom,geni-i2c"; 2459 reg = <0 0x00b90000 0 0x4000>; 2460 2461 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 2462 2463 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 2464 clock-names = "se"; 2465 2466 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2467 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2468 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2469 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2470 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2471 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2472 interconnect-names = "qup-core", 2473 "qup-config", 2474 "qup-memory"; 2475 2476 power-domains = <&rpmhpd RPMHPD_CX>; 2477 required-opps = <&rpmhpd_opp_low_svs>; 2478 2479 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 2480 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 2481 dma-names = "tx", 2482 "rx"; 2483 2484 pinctrl-0 = <&qup_i2c4_data_clk>; 2485 pinctrl-names = "default"; 2486 2487 #address-cells = <1>; 2488 #size-cells = <0>; 2489 2490 status = "disabled"; 2491 }; 2492 2493 spi4: spi@b90000 { 2494 compatible = "qcom,geni-spi"; 2495 reg = <0 0x00b90000 0 0x4000>; 2496 2497 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 2498 2499 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 2500 clock-names = "se"; 2501 2502 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2503 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2504 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2505 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2506 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2507 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2508 interconnect-names = "qup-core", 2509 "qup-config", 2510 "qup-memory"; 2511 2512 power-domains = <&rpmhpd RPMHPD_CX>; 2513 operating-points-v2 = <&qup_opp_table_100mhz>; 2514 2515 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 2516 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 2517 dma-names = "tx", 2518 "rx"; 2519 2520 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 2521 pinctrl-names = "default"; 2522 2523 #address-cells = <1>; 2524 #size-cells = <0>; 2525 2526 status = "disabled"; 2527 }; 2528 2529 i2c5: i2c@b94000 { 2530 compatible = "qcom,geni-i2c"; 2531 reg = <0 0x00b94000 0 0x4000>; 2532 2533 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 2534 2535 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 2536 clock-names = "se"; 2537 2538 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2539 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2540 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2541 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2542 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2543 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2544 interconnect-names = "qup-core", 2545 "qup-config", 2546 "qup-memory"; 2547 2548 power-domains = <&rpmhpd RPMHPD_CX>; 2549 required-opps = <&rpmhpd_opp_low_svs>; 2550 2551 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 2552 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 2553 dma-names = "tx", 2554 "rx"; 2555 2556 pinctrl-0 = <&qup_i2c5_data_clk>; 2557 pinctrl-names = "default"; 2558 2559 #address-cells = <1>; 2560 #size-cells = <0>; 2561 2562 status = "disabled"; 2563 }; 2564 2565 spi5: spi@b94000 { 2566 compatible = "qcom,geni-spi"; 2567 reg = <0 0x00b94000 0 0x4000>; 2568 2569 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 2570 2571 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 2572 clock-names = "se"; 2573 2574 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2575 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2576 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2577 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2578 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2579 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2580 interconnect-names = "qup-core", 2581 "qup-config", 2582 "qup-memory"; 2583 2584 power-domains = <&rpmhpd RPMHPD_CX>; 2585 operating-points-v2 = <&qup_opp_table_100mhz>; 2586 2587 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 2588 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 2589 dma-names = "tx", 2590 "rx"; 2591 2592 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 2593 pinctrl-names = "default"; 2594 2595 #address-cells = <1>; 2596 #size-cells = <0>; 2597 2598 status = "disabled"; 2599 }; 2600 2601 i2c6: i2c@b98000 { 2602 compatible = "qcom,geni-i2c"; 2603 reg = <0 0x00b98000 0 0x4000>; 2604 2605 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 2606 2607 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 2608 clock-names = "se"; 2609 2610 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2611 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2612 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2613 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2614 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2615 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2616 interconnect-names = "qup-core", 2617 "qup-config", 2618 "qup-memory"; 2619 2620 power-domains = <&rpmhpd RPMHPD_CX>; 2621 required-opps = <&rpmhpd_opp_low_svs>; 2622 2623 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 2624 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 2625 dma-names = "tx", 2626 "rx"; 2627 2628 pinctrl-0 = <&qup_i2c6_data_clk>; 2629 pinctrl-names = "default"; 2630 2631 #address-cells = <1>; 2632 #size-cells = <0>; 2633 2634 status = "disabled"; 2635 }; 2636 2637 spi6: spi@b98000 { 2638 compatible = "qcom,geni-spi"; 2639 reg = <0 0x00b98000 0 0x4000>; 2640 2641 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 2642 2643 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 2644 clock-names = "se"; 2645 2646 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2647 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2648 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2649 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2650 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2651 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2652 interconnect-names = "qup-core", 2653 "qup-config", 2654 "qup-memory"; 2655 2656 power-domains = <&rpmhpd RPMHPD_CX>; 2657 operating-points-v2 = <&qup_opp_table_100mhz>; 2658 2659 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 2660 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 2661 dma-names = "tx", 2662 "rx"; 2663 2664 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 2665 pinctrl-names = "default"; 2666 2667 #address-cells = <1>; 2668 #size-cells = <0>; 2669 2670 status = "disabled"; 2671 }; 2672 2673 i2c7: i2c@b9c000 { 2674 compatible = "qcom,geni-i2c"; 2675 reg = <0 0x00b9c000 0 0x4000>; 2676 2677 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 2678 2679 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 2680 clock-names = "se"; 2681 2682 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2683 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2684 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2685 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2686 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2687 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2688 interconnect-names = "qup-core", 2689 "qup-config", 2690 "qup-memory"; 2691 2692 power-domains = <&rpmhpd RPMHPD_CX>; 2693 required-opps = <&rpmhpd_opp_low_svs>; 2694 2695 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 2696 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 2697 dma-names = "tx", 2698 "rx"; 2699 2700 pinctrl-0 = <&qup_i2c7_data_clk>; 2701 pinctrl-names = "default"; 2702 2703 #address-cells = <1>; 2704 #size-cells = <0>; 2705 2706 status = "disabled"; 2707 }; 2708 2709 spi7: spi@b9c000 { 2710 compatible = "qcom,geni-spi"; 2711 reg = <0 0x00b9c000 0 0x4000>; 2712 2713 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 2714 2715 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 2716 clock-names = "se"; 2717 2718 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2719 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2720 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2721 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2722 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2723 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2724 interconnect-names = "qup-core", 2725 "qup-config", 2726 "qup-memory"; 2727 2728 power-domains = <&rpmhpd RPMHPD_CX>; 2729 operating-points-v2 = <&qup_opp_table_100mhz>; 2730 2731 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 2732 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 2733 dma-names = "tx", 2734 "rx"; 2735 2736 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 2737 pinctrl-names = "default"; 2738 2739 #address-cells = <1>; 2740 #size-cells = <0>; 2741 2742 status = "disabled"; 2743 }; 2744 }; 2745 2746 tsens0: thermal-sensor@c271000 { 2747 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2"; 2748 reg = <0 0x0c271000 0 0x1000>, 2749 <0 0x0c222000 0 0x1000>; 2750 2751 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 2752 <&intc GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>; 2753 interrupt-names = "uplow", 2754 "critical"; 2755 2756 #qcom,sensors = <16>; 2757 2758 #thermal-sensor-cells = <1>; 2759 }; 2760 2761 tsens1: thermal-sensor@c272000 { 2762 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2"; 2763 reg = <0 0x0c272000 0 0x1000>, 2764 <0 0x0c223000 0 0x1000>; 2765 2766 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 2767 <&intc GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>; 2768 interrupt-names = "uplow", 2769 "critical"; 2770 2771 #qcom,sensors = <16>; 2772 2773 #thermal-sensor-cells = <1>; 2774 }; 2775 2776 tsens2: thermal-sensor@c273000 { 2777 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2"; 2778 reg = <0 0x0c273000 0 0x1000>, 2779 <0 0x0c224000 0 0x1000>; 2780 2781 interrupts-extended = <&pdc 28 IRQ_TYPE_LEVEL_HIGH>, 2782 <&intc GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH>; 2783 interrupt-names = "uplow", 2784 "critical"; 2785 2786 #qcom,sensors = <16>; 2787 2788 #thermal-sensor-cells = <1>; 2789 }; 2790 2791 tsens3: thermal-sensor@c274000 { 2792 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2"; 2793 reg = <0 0x0c274000 0 0x1000>, 2794 <0 0x0c225000 0 0x1000>; 2795 2796 interrupts-extended = <&pdc 29 IRQ_TYPE_LEVEL_HIGH>, 2797 <&intc GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>; 2798 interrupt-names = "uplow", 2799 "critical"; 2800 2801 #qcom,sensors = <16>; 2802 2803 #thermal-sensor-cells = <1>; 2804 }; 2805 2806 usb_1_ss0_hsphy: phy@fd3000 { 2807 compatible = "qcom,x1e80100-snps-eusb2-phy", 2808 "qcom,sm8550-snps-eusb2-phy"; 2809 reg = <0 0x00fd3000 0 0x154>; 2810 #phy-cells = <0>; 2811 2812 clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>; 2813 clock-names = "ref"; 2814 2815 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2816 2817 status = "disabled"; 2818 }; 2819 2820 usb_1_ss0_qmpphy: phy@fd5000 { 2821 compatible = "qcom,x1e80100-qmp-usb3-dp-phy"; 2822 reg = <0 0x00fd5000 0 0x4000>; 2823 2824 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2825 <&rpmhcc RPMH_CXO_CLK>, 2826 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2827 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2828 clock-names = "aux", 2829 "ref", 2830 "com_aux", 2831 "usb3_pipe"; 2832 2833 power-domains = <&gcc GCC_USB_0_PHY_GDSC>; 2834 2835 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 2836 <&gcc GCC_USB4_0_DP0_PHY_PRIM_BCR>; 2837 reset-names = "phy", 2838 "common"; 2839 2840 #clock-cells = <1>; 2841 #phy-cells = <1>; 2842 2843 orientation-switch; 2844 2845 status = "disabled"; 2846 2847 ports { 2848 #address-cells = <1>; 2849 #size-cells = <0>; 2850 2851 port@0 { 2852 reg = <0>; 2853 2854 usb_1_ss0_qmpphy_out: endpoint { 2855 }; 2856 }; 2857 2858 port@1 { 2859 reg = <1>; 2860 2861 usb_1_ss0_qmpphy_usb_ss_in: endpoint { 2862 remote-endpoint = <&usb_1_ss0_dwc3_ss>; 2863 }; 2864 }; 2865 2866 port@2 { 2867 reg = <2>; 2868 2869 usb_1_ss0_qmpphy_dp_in: endpoint { 2870 remote-endpoint = <&mdss_dp0_out>; 2871 }; 2872 }; 2873 }; 2874 }; 2875 2876 usb_1_ss1_hsphy: phy@fd9000 { 2877 compatible = "qcom,x1e80100-snps-eusb2-phy", 2878 "qcom,sm8550-snps-eusb2-phy"; 2879 reg = <0 0x00fd9000 0 0x154>; 2880 #phy-cells = <0>; 2881 2882 clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>; 2883 clock-names = "ref"; 2884 2885 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2886 2887 status = "disabled"; 2888 }; 2889 2890 usb_1_ss1_qmpphy: phy@fda000 { 2891 compatible = "qcom,x1e80100-qmp-usb3-dp-phy"; 2892 reg = <0 0x00fda000 0 0x4000>; 2893 2894 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 2895 <&rpmhcc RPMH_CXO_CLK>, 2896 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 2897 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 2898 clock-names = "aux", 2899 "ref", 2900 "com_aux", 2901 "usb3_pipe"; 2902 2903 power-domains = <&gcc GCC_USB_1_PHY_GDSC>; 2904 2905 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 2906 <&gcc GCC_USB4_1_DP0_PHY_SEC_BCR>; 2907 reset-names = "phy", 2908 "common"; 2909 2910 #clock-cells = <1>; 2911 #phy-cells = <1>; 2912 2913 orientation-switch; 2914 2915 status = "disabled"; 2916 2917 ports { 2918 #address-cells = <1>; 2919 #size-cells = <0>; 2920 2921 port@0 { 2922 reg = <0>; 2923 2924 usb_1_ss1_qmpphy_out: endpoint { 2925 }; 2926 }; 2927 2928 port@1 { 2929 reg = <1>; 2930 2931 usb_1_ss1_qmpphy_usb_ss_in: endpoint { 2932 remote-endpoint = <&usb_1_ss1_dwc3_ss>; 2933 }; 2934 }; 2935 2936 port@2 { 2937 reg = <2>; 2938 2939 usb_1_ss1_qmpphy_dp_in: endpoint { 2940 remote-endpoint = <&mdss_dp1_out>; 2941 }; 2942 }; 2943 }; 2944 }; 2945 2946 usb_1_ss2_hsphy: phy@fde000 { 2947 compatible = "qcom,x1e80100-snps-eusb2-phy", 2948 "qcom,sm8550-snps-eusb2-phy"; 2949 reg = <0 0x00fde000 0 0x154>; 2950 #phy-cells = <0>; 2951 2952 clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>; 2953 clock-names = "ref"; 2954 2955 resets = <&gcc GCC_QUSB2PHY_TERT_BCR>; 2956 2957 status = "disabled"; 2958 }; 2959 2960 usb_1_ss2_qmpphy: phy@fdf000 { 2961 compatible = "qcom,x1e80100-qmp-usb3-dp-phy"; 2962 reg = <0 0x00fdf000 0 0x4000>; 2963 2964 clocks = <&gcc GCC_USB3_TERT_PHY_AUX_CLK>, 2965 <&rpmhcc RPMH_CXO_CLK>, 2966 <&gcc GCC_USB3_TERT_PHY_COM_AUX_CLK>, 2967 <&gcc GCC_USB3_TERT_PHY_PIPE_CLK>; 2968 clock-names = "aux", 2969 "ref", 2970 "com_aux", 2971 "usb3_pipe"; 2972 2973 power-domains = <&gcc GCC_USB_2_PHY_GDSC>; 2974 2975 resets = <&gcc GCC_USB3_PHY_TERT_BCR>, 2976 <&gcc GCC_USB4_2_DP0_PHY_TERT_BCR>; 2977 reset-names = "phy", 2978 "common"; 2979 2980 #clock-cells = <1>; 2981 #phy-cells = <1>; 2982 2983 orientation-switch; 2984 2985 status = "disabled"; 2986 2987 ports { 2988 #address-cells = <1>; 2989 #size-cells = <0>; 2990 2991 port@0 { 2992 reg = <0>; 2993 2994 usb_1_ss2_qmpphy_out: endpoint { 2995 }; 2996 }; 2997 2998 port@1 { 2999 reg = <1>; 3000 3001 usb_1_ss2_qmpphy_usb_ss_in: endpoint { 3002 remote-endpoint = <&usb_1_ss2_dwc3_ss>; 3003 }; 3004 }; 3005 3006 port@2 { 3007 reg = <2>; 3008 3009 usb_1_ss2_qmpphy_dp_in: endpoint { 3010 remote-endpoint = <&mdss_dp2_out>; 3011 }; 3012 }; 3013 }; 3014 }; 3015 3016 cnoc_main: interconnect@1500000 { 3017 compatible = "qcom,x1e80100-cnoc-main"; 3018 reg = <0 0x01500000 0 0x14400>; 3019 3020 qcom,bcm-voters = <&apps_bcm_voter>; 3021 3022 #interconnect-cells = <2>; 3023 }; 3024 3025 config_noc: interconnect@1600000 { 3026 compatible = "qcom,x1e80100-cnoc-cfg"; 3027 reg = <0 0x01600000 0 0x6600>; 3028 3029 qcom,bcm-voters = <&apps_bcm_voter>; 3030 3031 #interconnect-cells = <2>; 3032 }; 3033 3034 system_noc: interconnect@1680000 { 3035 compatible = "qcom,x1e80100-system-noc"; 3036 reg = <0 0x01680000 0 0x1c080>; 3037 3038 qcom,bcm-voters = <&apps_bcm_voter>; 3039 3040 #interconnect-cells = <2>; 3041 }; 3042 3043 pcie_south_anoc: interconnect@16c0000 { 3044 compatible = "qcom,x1e80100-pcie-south-anoc"; 3045 reg = <0 0x016c0000 0 0xd080>; 3046 3047 qcom,bcm-voters = <&apps_bcm_voter>; 3048 3049 #interconnect-cells = <2>; 3050 }; 3051 3052 pcie_center_anoc: interconnect@16d0000 { 3053 compatible = "qcom,x1e80100-pcie-center-anoc"; 3054 reg = <0 0x016d0000 0 0x7000>; 3055 3056 qcom,bcm-voters = <&apps_bcm_voter>; 3057 3058 #interconnect-cells = <2>; 3059 }; 3060 3061 aggre1_noc: interconnect@16e0000 { 3062 compatible = "qcom,x1e80100-aggre1-noc"; 3063 reg = <0 0x016e0000 0 0x14400>; 3064 3065 qcom,bcm-voters = <&apps_bcm_voter>; 3066 3067 #interconnect-cells = <2>; 3068 }; 3069 3070 aggre2_noc: interconnect@1700000 { 3071 compatible = "qcom,x1e80100-aggre2-noc"; 3072 reg = <0 0x01700000 0 0x1c400>; 3073 3074 qcom,bcm-voters = <&apps_bcm_voter>; 3075 3076 #interconnect-cells = <2>; 3077 }; 3078 3079 pcie_north_anoc: interconnect@1740000 { 3080 compatible = "qcom,x1e80100-pcie-north-anoc"; 3081 reg = <0 0x01740000 0 0x9080>; 3082 3083 qcom,bcm-voters = <&apps_bcm_voter>; 3084 3085 #interconnect-cells = <2>; 3086 }; 3087 3088 usb_center_anoc: interconnect@1750000 { 3089 compatible = "qcom,x1e80100-usb-center-anoc"; 3090 reg = <0 0x01750000 0 0x8800>; 3091 3092 qcom,bcm-voters = <&apps_bcm_voter>; 3093 3094 #interconnect-cells = <2>; 3095 }; 3096 3097 usb_north_anoc: interconnect@1760000 { 3098 compatible = "qcom,x1e80100-usb-north-anoc"; 3099 reg = <0 0x01760000 0 0x7080>; 3100 3101 qcom,bcm-voters = <&apps_bcm_voter>; 3102 3103 #interconnect-cells = <2>; 3104 }; 3105 3106 usb_south_anoc: interconnect@1770000 { 3107 compatible = "qcom,x1e80100-usb-south-anoc"; 3108 reg = <0 0x01770000 0 0xf080>; 3109 3110 qcom,bcm-voters = <&apps_bcm_voter>; 3111 3112 #interconnect-cells = <2>; 3113 }; 3114 3115 mmss_noc: interconnect@1780000 { 3116 compatible = "qcom,x1e80100-mmss-noc"; 3117 reg = <0 0x01780000 0 0x5B800>; 3118 3119 qcom,bcm-voters = <&apps_bcm_voter>; 3120 3121 #interconnect-cells = <2>; 3122 }; 3123 3124 pcie3: pcie@1bd0000 { 3125 device_type = "pci"; 3126 compatible = "qcom,pcie-x1e80100"; 3127 reg = <0x0 0x01bd0000 0x0 0x3000>, 3128 <0x0 0x78000000 0x0 0xf1d>, 3129 <0x0 0x78000f40 0x0 0xa8>, 3130 <0x0 0x78001000 0x0 0x1000>, 3131 <0x0 0x78100000 0x0 0x100000>, 3132 <0x0 0x01bd3000 0x0 0x1000>; 3133 reg-names = "parf", 3134 "dbi", 3135 "elbi", 3136 "atu", 3137 "config", 3138 "mhi"; 3139 #address-cells = <3>; 3140 #size-cells = <2>; 3141 ranges = <0x01000000 0x0 0x00000000 0x0 0x78200000 0x0 0x100000>, 3142 <0x02000000 0x0 0x78300000 0x0 0x78300000 0x0 0x3d00000>, 3143 <0x03000000 0x7 0x40000000 0x7 0x40000000 0x0 0x40000000>; 3144 bus-range = <0x00 0xff>; 3145 3146 dma-coherent; 3147 3148 linux,pci-domain = <3>; 3149 num-lanes = <8>; 3150 3151 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 3152 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, 3153 <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>, 3154 <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>, 3155 <GIC_SPI 671 IRQ_TYPE_LEVEL_HIGH>, 3156 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 3157 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 3158 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 3159 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 3160 interrupt-names = "msi0", 3161 "msi1", 3162 "msi2", 3163 "msi3", 3164 "msi4", 3165 "msi5", 3166 "msi6", 3167 "msi7", 3168 "global"; 3169 3170 #interrupt-cells = <1>; 3171 interrupt-map-mask = <0 0 0 0x7>; 3172 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 3173 <0 0 0 2 &intc 0 0 GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>, 3174 <0 0 0 3 &intc 0 0 GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>, 3175 <0 0 0 4 &intc 0 0 GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 3176 3177 clocks = <&gcc GCC_PCIE_3_AUX_CLK>, 3178 <&gcc GCC_PCIE_3_CFG_AHB_CLK>, 3179 <&gcc GCC_PCIE_3_MSTR_AXI_CLK>, 3180 <&gcc GCC_PCIE_3_SLV_AXI_CLK>, 3181 <&gcc GCC_PCIE_3_SLV_Q2A_AXI_CLK>, 3182 <&gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK>, 3183 <&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>; 3184 clock-names = "aux", 3185 "cfg", 3186 "bus_master", 3187 "bus_slave", 3188 "slave_q2a", 3189 "noc_aggr", 3190 "cnoc_sf_axi"; 3191 3192 assigned-clocks = <&gcc GCC_PCIE_3_AUX_CLK>; 3193 assigned-clock-rates = <19200000>; 3194 3195 interconnects = <&pcie_north_anoc MASTER_PCIE_3 QCOM_ICC_TAG_ALWAYS 3196 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3197 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 3198 &cnoc_main SLAVE_PCIE_3 QCOM_ICC_TAG_ALWAYS>; 3199 interconnect-names = "pcie-mem", 3200 "cpu-pcie"; 3201 3202 resets = <&gcc GCC_PCIE_3_BCR>, 3203 <&gcc GCC_PCIE_3_LINK_DOWN_BCR>; 3204 reset-names = "pci", 3205 "link_down"; 3206 3207 power-domains = <&gcc GCC_PCIE_3_GDSC>; 3208 3209 phys = <&pcie3_phy>; 3210 phy-names = "pciephy"; 3211 3212 operating-points-v2 = <&pcie3_opp_table>; 3213 3214 status = "disabled"; 3215 3216 pcie3_opp_table: opp-table { 3217 compatible = "operating-points-v2"; 3218 3219 /* GEN 1 x1 */ 3220 opp-2500000 { 3221 opp-hz = /bits/ 64 <2500000>; 3222 required-opps = <&rpmhpd_opp_low_svs>; 3223 opp-peak-kBps = <250000 1>; 3224 }; 3225 3226 /* GEN 1 x2 and GEN 2 x1 */ 3227 opp-5000000 { 3228 opp-hz = /bits/ 64 <5000000>; 3229 required-opps = <&rpmhpd_opp_low_svs>; 3230 opp-peak-kBps = <500000 1>; 3231 }; 3232 3233 /* GEN 1 x4 and GEN 2 x2 */ 3234 opp-10000000 { 3235 opp-hz = /bits/ 64 <10000000>; 3236 required-opps = <&rpmhpd_opp_low_svs>; 3237 opp-peak-kBps = <1000000 1>; 3238 }; 3239 3240 /* GEN 1 x8 and GEN 2 x4 */ 3241 opp-20000000 { 3242 opp-hz = /bits/ 64 <20000000>; 3243 required-opps = <&rpmhpd_opp_low_svs>; 3244 opp-peak-kBps = <2000000 1>; 3245 }; 3246 3247 /* GEN 2 x8 */ 3248 opp-40000000 { 3249 opp-hz = /bits/ 64 <40000000>; 3250 required-opps = <&rpmhpd_opp_low_svs>; 3251 opp-peak-kBps = <4000000 1>; 3252 }; 3253 3254 /* GEN 3 x1 */ 3255 opp-8000000 { 3256 opp-hz = /bits/ 64 <8000000>; 3257 required-opps = <&rpmhpd_opp_svs>; 3258 opp-peak-kBps = <984500 1>; 3259 }; 3260 3261 /* GEN 3 x2 and GEN 4 x1 */ 3262 opp-16000000 { 3263 opp-hz = /bits/ 64 <16000000>; 3264 required-opps = <&rpmhpd_opp_svs>; 3265 opp-peak-kBps = <1969000 1>; 3266 }; 3267 3268 /* GEN 3 x4 and GEN 4 x2 */ 3269 opp-32000000 { 3270 opp-hz = /bits/ 64 <32000000>; 3271 required-opps = <&rpmhpd_opp_svs>; 3272 opp-peak-kBps = <3938000 1>; 3273 }; 3274 3275 /* GEN 3 x8 and GEN 4 x4 */ 3276 opp-64000000 { 3277 opp-hz = /bits/ 64 <64000000>; 3278 required-opps = <&rpmhpd_opp_svs>; 3279 opp-peak-kBps = <7876000 1>; 3280 }; 3281 3282 /* GEN 4 x8 */ 3283 opp-128000000 { 3284 opp-hz = /bits/ 64 <128000000>; 3285 required-opps = <&rpmhpd_opp_svs>; 3286 opp-peak-kBps = <15753000 1>; 3287 }; 3288 }; 3289 }; 3290 3291 pcie3_phy: phy@1be0000 { 3292 compatible = "qcom,x1e80100-qmp-gen4x8-pcie-phy"; 3293 reg = <0 0x01be0000 0 0x10000>; 3294 3295 clocks = <&gcc GCC_PCIE_3_PHY_AUX_CLK>, 3296 <&gcc GCC_PCIE_3_CFG_AHB_CLK>, 3297 <&tcsr TCSR_PCIE_8L_CLKREF_EN>, 3298 <&gcc GCC_PCIE_3_PHY_RCHNG_CLK>, 3299 <&gcc GCC_PCIE_3_PIPE_CLK>, 3300 <&gcc GCC_PCIE_3_PIPEDIV2_CLK>; 3301 clock-names = "aux", 3302 "cfg_ahb", 3303 "ref", 3304 "rchng", 3305 "pipe", 3306 "pipediv2"; 3307 3308 resets = <&gcc GCC_PCIE_3_PHY_BCR>, 3309 <&gcc GCC_PCIE_3_NOCSR_COM_PHY_BCR>; 3310 reset-names = "phy", 3311 "phy_nocsr"; 3312 3313 assigned-clocks = <&gcc GCC_PCIE_3_PHY_RCHNG_CLK>; 3314 assigned-clock-rates = <100000000>; 3315 3316 power-domains = <&gcc GCC_PCIE_3_PHY_GDSC>; 3317 3318 #clock-cells = <0>; 3319 clock-output-names = "pcie3_pipe_clk"; 3320 3321 #phy-cells = <0>; 3322 3323 status = "disabled"; 3324 }; 3325 3326 pcie6a: pci@1bf8000 { 3327 device_type = "pci"; 3328 compatible = "qcom,pcie-x1e80100"; 3329 reg = <0 0x01bf8000 0 0x3000>, 3330 <0 0x70000000 0 0xf20>, 3331 <0 0x70000f40 0 0xa8>, 3332 <0 0x70001000 0 0x1000>, 3333 <0 0x70100000 0 0x100000>, 3334 <0 0x01bfb000 0 0x1000>; 3335 reg-names = "parf", 3336 "dbi", 3337 "elbi", 3338 "atu", 3339 "config", 3340 "mhi"; 3341 #address-cells = <3>; 3342 #size-cells = <2>; 3343 ranges = <0x01000000 0x0 0x00000000 0x0 0x70200000 0x0 0x100000>, 3344 <0x02000000 0x0 0x70300000 0x0 0x70300000 0x0 0x3d00000>; 3345 bus-range = <0x00 0xff>; 3346 3347 dma-coherent; 3348 3349 linux,pci-domain = <6>; 3350 num-lanes = <4>; 3351 3352 msi-map = <0x0 &gic_its 0xe0000 0x10000>; 3353 3354 interrupts = <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>, 3355 <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>, 3356 <GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>, 3357 <GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>, 3358 <GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>, 3359 <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>, 3360 <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>, 3361 <GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>; 3362 interrupt-names = "msi0", 3363 "msi1", 3364 "msi2", 3365 "msi3", 3366 "msi4", 3367 "msi5", 3368 "msi6", 3369 "msi7"; 3370 3371 #interrupt-cells = <1>; 3372 interrupt-map-mask = <0 0 0 0x7>; 3373 interrupt-map = <0 0 0 1 &intc 0 0 0 843 IRQ_TYPE_LEVEL_HIGH>, 3374 <0 0 0 2 &intc 0 0 0 844 IRQ_TYPE_LEVEL_HIGH>, 3375 <0 0 0 3 &intc 0 0 0 845 IRQ_TYPE_LEVEL_HIGH>, 3376 <0 0 0 4 &intc 0 0 0 772 IRQ_TYPE_LEVEL_HIGH>; 3377 3378 clocks = <&gcc GCC_PCIE_6A_AUX_CLK>, 3379 <&gcc GCC_PCIE_6A_CFG_AHB_CLK>, 3380 <&gcc GCC_PCIE_6A_MSTR_AXI_CLK>, 3381 <&gcc GCC_PCIE_6A_SLV_AXI_CLK>, 3382 <&gcc GCC_PCIE_6A_SLV_Q2A_AXI_CLK>, 3383 <&gcc GCC_CFG_NOC_PCIE_ANOC_SOUTH_AHB_CLK>, 3384 <&gcc GCC_CNOC_PCIE_SOUTH_SF_AXI_CLK>; 3385 clock-names = "aux", 3386 "cfg", 3387 "bus_master", 3388 "bus_slave", 3389 "slave_q2a", 3390 "noc_aggr", 3391 "cnoc_sf_axi"; 3392 3393 assigned-clocks = <&gcc GCC_PCIE_6A_AUX_CLK>; 3394 assigned-clock-rates = <19200000>; 3395 3396 interconnects = <&pcie_south_anoc MASTER_PCIE_6A QCOM_ICC_TAG_ALWAYS 3397 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3398 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 3399 &cnoc_main SLAVE_PCIE_6A QCOM_ICC_TAG_ALWAYS>; 3400 interconnect-names = "pcie-mem", 3401 "cpu-pcie"; 3402 3403 resets = <&gcc GCC_PCIE_6A_BCR>, 3404 <&gcc GCC_PCIE_6A_LINK_DOWN_BCR>; 3405 reset-names = "pci", 3406 "link_down"; 3407 3408 power-domains = <&gcc GCC_PCIE_6A_GDSC>; 3409 required-opps = <&rpmhpd_opp_nom>; 3410 3411 phys = <&pcie6a_phy>; 3412 phy-names = "pciephy"; 3413 3414 status = "disabled"; 3415 }; 3416 3417 pcie6a_phy: phy@1bfc000 { 3418 compatible = "qcom,x1e80100-qmp-gen4x4-pcie-phy"; 3419 reg = <0 0x01bfc000 0 0x2000>, 3420 <0 0x01bfe000 0 0x2000>; 3421 3422 clocks = <&gcc GCC_PCIE_6A_PHY_AUX_CLK>, 3423 <&gcc GCC_PCIE_6A_CFG_AHB_CLK>, 3424 <&tcsr TCSR_PCIE_4L_CLKREF_EN>, 3425 <&gcc GCC_PCIE_6A_PHY_RCHNG_CLK>, 3426 <&gcc GCC_PCIE_6A_PIPE_CLK>, 3427 <&gcc GCC_PCIE_6A_PIPEDIV2_CLK>; 3428 clock-names = "aux", 3429 "cfg_ahb", 3430 "ref", 3431 "rchng", 3432 "pipe", 3433 "pipediv2"; 3434 3435 resets = <&gcc GCC_PCIE_6A_PHY_BCR>, 3436 <&gcc GCC_PCIE_6A_NOCSR_COM_PHY_BCR>; 3437 reset-names = "phy", 3438 "phy_nocsr"; 3439 3440 assigned-clocks = <&gcc GCC_PCIE_6A_PHY_RCHNG_CLK>; 3441 assigned-clock-rates = <100000000>; 3442 3443 power-domains = <&gcc GCC_PCIE_6_PHY_GDSC>; 3444 3445 qcom,4ln-config-sel = <&tcsr 0x1a000 0>; 3446 3447 #clock-cells = <0>; 3448 clock-output-names = "pcie6a_pipe_clk"; 3449 3450 #phy-cells = <0>; 3451 3452 status = "disabled"; 3453 }; 3454 3455 pcie5: pci@1c00000 { 3456 device_type = "pci"; 3457 compatible = "qcom,pcie-x1e80100"; 3458 reg = <0 0x01c00000 0 0x3000>, 3459 <0 0x7e000000 0 0xf1d>, 3460 <0 0x7e000f40 0 0xa8>, 3461 <0 0x7e001000 0 0x1000>, 3462 <0 0x7e100000 0 0x100000>, 3463 <0 0x01c03000 0 0x1000>; 3464 reg-names = "parf", 3465 "dbi", 3466 "elbi", 3467 "atu", 3468 "config", 3469 "mhi"; 3470 #address-cells = <3>; 3471 #size-cells = <2>; 3472 ranges = <0x01000000 0x0 0x00000000 0x0 0x7e200000 0x0 0x100000>, 3473 <0x02000000 0x0 0x7e300000 0x0 0x7e300000 0x0 0x1d00000>; 3474 bus-range = <0x00 0xff>; 3475 3476 dma-coherent; 3477 3478 linux,pci-domain = <5>; 3479 num-lanes = <2>; 3480 3481 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 3482 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 3483 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 3484 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 3485 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 3486 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 3487 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 3488 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 3489 interrupt-names = "msi0", 3490 "msi1", 3491 "msi2", 3492 "msi3", 3493 "msi4", 3494 "msi5", 3495 "msi6", 3496 "msi7"; 3497 3498 #interrupt-cells = <1>; 3499 interrupt-map-mask = <0 0 0 0x7>; 3500 interrupt-map = <0 0 0 1 &intc 0 0 0 70 IRQ_TYPE_LEVEL_HIGH>, 3501 <0 0 0 2 &intc 0 0 0 71 IRQ_TYPE_LEVEL_HIGH>, 3502 <0 0 0 3 &intc 0 0 0 72 IRQ_TYPE_LEVEL_HIGH>, 3503 <0 0 0 4 &intc 0 0 0 73 IRQ_TYPE_LEVEL_HIGH>; 3504 3505 clocks = <&gcc GCC_PCIE_5_AUX_CLK>, 3506 <&gcc GCC_PCIE_5_CFG_AHB_CLK>, 3507 <&gcc GCC_PCIE_5_MSTR_AXI_CLK>, 3508 <&gcc GCC_PCIE_5_SLV_AXI_CLK>, 3509 <&gcc GCC_PCIE_5_SLV_Q2A_AXI_CLK>, 3510 <&gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK>, 3511 <&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>; 3512 clock-names = "aux", 3513 "cfg", 3514 "bus_master", 3515 "bus_slave", 3516 "slave_q2a", 3517 "noc_aggr", 3518 "cnoc_sf_axi"; 3519 3520 assigned-clocks = <&gcc GCC_PCIE_5_AUX_CLK>; 3521 assigned-clock-rates = <19200000>; 3522 3523 interconnects = <&pcie_north_anoc MASTER_PCIE_5 QCOM_ICC_TAG_ALWAYS 3524 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3525 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 3526 &cnoc_main SLAVE_PCIE_5 QCOM_ICC_TAG_ALWAYS>; 3527 interconnect-names = "pcie-mem", 3528 "cpu-pcie"; 3529 3530 resets = <&gcc GCC_PCIE_5_BCR>, 3531 <&gcc GCC_PCIE_5_LINK_DOWN_BCR>; 3532 reset-names = "pci", 3533 "link_down"; 3534 3535 power-domains = <&gcc GCC_PCIE_5_GDSC>; 3536 required-opps = <&rpmhpd_opp_nom>; 3537 3538 phys = <&pcie5_phy>; 3539 phy-names = "pciephy"; 3540 3541 status = "disabled"; 3542 }; 3543 3544 pcie5_phy: phy@1c06000 { 3545 compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy"; 3546 reg = <0 0x01c06000 0 0x2000>; 3547 3548 clocks = <&gcc GCC_PCIE_5_AUX_CLK>, 3549 <&gcc GCC_PCIE_5_CFG_AHB_CLK>, 3550 <&tcsr TCSR_PCIE_2L_5_CLKREF_EN>, 3551 <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>, 3552 <&gcc GCC_PCIE_5_PIPE_CLK>, 3553 <&gcc GCC_PCIE_5_PIPEDIV2_CLK>; 3554 clock-names = "aux", 3555 "cfg_ahb", 3556 "ref", 3557 "rchng", 3558 "pipe", 3559 "pipediv2"; 3560 3561 resets = <&gcc GCC_PCIE_5_PHY_BCR>; 3562 reset-names = "phy"; 3563 3564 assigned-clocks = <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>; 3565 assigned-clock-rates = <100000000>; 3566 3567 power-domains = <&gcc GCC_PCIE_5_PHY_GDSC>; 3568 3569 #clock-cells = <0>; 3570 clock-output-names = "pcie5_pipe_clk"; 3571 3572 #phy-cells = <0>; 3573 3574 status = "disabled"; 3575 }; 3576 3577 pcie4: pci@1c08000 { 3578 device_type = "pci"; 3579 compatible = "qcom,pcie-x1e80100"; 3580 reg = <0 0x01c08000 0 0x3000>, 3581 <0 0x7c000000 0 0xf1d>, 3582 <0 0x7c000f40 0 0xa8>, 3583 <0 0x7c001000 0 0x1000>, 3584 <0 0x7c100000 0 0x100000>, 3585 <0 0x01c0b000 0 0x1000>; 3586 reg-names = "parf", 3587 "dbi", 3588 "elbi", 3589 "atu", 3590 "config", 3591 "mhi"; 3592 #address-cells = <3>; 3593 #size-cells = <2>; 3594 ranges = <0x01000000 0x0 0x00000000 0x0 0x7c200000 0x0 0x100000>, 3595 <0x02000000 0x0 0x7c300000 0x0 0x7c300000 0x0 0x1d00000>; 3596 bus-range = <0x00 0xff>; 3597 3598 dma-coherent; 3599 3600 linux,pci-domain = <4>; 3601 num-lanes = <2>; 3602 3603 msi-map = <0x0 &gic_its 0xc0000 0x10000>; 3604 3605 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 3606 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 3607 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 3608 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 3609 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 3610 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 3611 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 3612 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 3613 interrupt-names = "msi0", 3614 "msi1", 3615 "msi2", 3616 "msi3", 3617 "msi4", 3618 "msi5", 3619 "msi6", 3620 "msi7"; 3621 3622 #interrupt-cells = <1>; 3623 interrupt-map-mask = <0 0 0 0x7>; 3624 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, 3625 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, 3626 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, 3627 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; 3628 3629 clocks = <&gcc GCC_PCIE_4_AUX_CLK>, 3630 <&gcc GCC_PCIE_4_CFG_AHB_CLK>, 3631 <&gcc GCC_PCIE_4_MSTR_AXI_CLK>, 3632 <&gcc GCC_PCIE_4_SLV_AXI_CLK>, 3633 <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>, 3634 <&gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK>, 3635 <&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>; 3636 clock-names = "aux", 3637 "cfg", 3638 "bus_master", 3639 "bus_slave", 3640 "slave_q2a", 3641 "noc_aggr", 3642 "cnoc_sf_axi"; 3643 3644 assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>; 3645 assigned-clock-rates = <19200000>; 3646 3647 interconnects = <&pcie_north_anoc MASTER_PCIE_4 QCOM_ICC_TAG_ALWAYS 3648 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3649 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 3650 &cnoc_main SLAVE_PCIE_4 QCOM_ICC_TAG_ALWAYS>; 3651 interconnect-names = "pcie-mem", 3652 "cpu-pcie"; 3653 3654 resets = <&gcc GCC_PCIE_4_BCR>, 3655 <&gcc GCC_PCIE_4_LINK_DOWN_BCR>; 3656 reset-names = "pci", 3657 "link_down"; 3658 3659 power-domains = <&gcc GCC_PCIE_4_GDSC>; 3660 required-opps = <&rpmhpd_opp_nom>; 3661 3662 phys = <&pcie4_phy>; 3663 phy-names = "pciephy"; 3664 3665 status = "disabled"; 3666 3667 pcie4_port0: pcie@0 { 3668 device_type = "pci"; 3669 reg = <0x0 0x0 0x0 0x0 0x0>; 3670 bus-range = <0x01 0xff>; 3671 3672 #address-cells = <3>; 3673 #size-cells = <2>; 3674 ranges; 3675 }; 3676 }; 3677 3678 pcie4_phy: phy@1c0e000 { 3679 compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy"; 3680 reg = <0 0x01c0e000 0 0x2000>; 3681 3682 clocks = <&gcc GCC_PCIE_4_AUX_CLK>, 3683 <&gcc GCC_PCIE_4_CFG_AHB_CLK>, 3684 <&tcsr TCSR_PCIE_2L_4_CLKREF_EN>, 3685 <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>, 3686 <&gcc GCC_PCIE_4_PIPE_CLK>, 3687 <&gcc GCC_PCIE_4_PIPEDIV2_CLK>; 3688 clock-names = "aux", 3689 "cfg_ahb", 3690 "ref", 3691 "rchng", 3692 "pipe", 3693 "pipediv2"; 3694 3695 resets = <&gcc GCC_PCIE_4_PHY_BCR>; 3696 reset-names = "phy"; 3697 3698 assigned-clocks = <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>; 3699 assigned-clock-rates = <100000000>; 3700 3701 power-domains = <&gcc GCC_PCIE_4_PHY_GDSC>; 3702 3703 #clock-cells = <0>; 3704 clock-output-names = "pcie4_pipe_clk"; 3705 3706 #phy-cells = <0>; 3707 3708 status = "disabled"; 3709 }; 3710 3711 tcsr_mutex: hwlock@1f40000 { 3712 compatible = "qcom,tcsr-mutex"; 3713 reg = <0 0x01f40000 0 0x20000>; 3714 #hwlock-cells = <1>; 3715 }; 3716 3717 tcsr: clock-controller@1fc0000 { 3718 compatible = "qcom,x1e80100-tcsr", "syscon"; 3719 reg = <0 0x01fc0000 0 0x30000>; 3720 clocks = <&rpmhcc RPMH_CXO_CLK>; 3721 #clock-cells = <1>; 3722 #reset-cells = <1>; 3723 }; 3724 3725 gpu: gpu@3d00000 { 3726 compatible = "qcom,adreno-43050c01", "qcom,adreno"; 3727 reg = <0x0 0x03d00000 0x0 0x40000>, 3728 <0x0 0x03d9e000 0x0 0x1000>, 3729 <0x0 0x03d61000 0x0 0x800>; 3730 3731 reg-names = "kgsl_3d0_reg_memory", 3732 "cx_mem", 3733 "cx_dbgc"; 3734 3735 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 3736 3737 iommus = <&adreno_smmu 0 0x0>, 3738 <&adreno_smmu 1 0x0>; 3739 3740 operating-points-v2 = <&gpu_opp_table>; 3741 3742 qcom,gmu = <&gmu>; 3743 #cooling-cells = <2>; 3744 3745 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 3746 interconnect-names = "gfx-mem"; 3747 3748 status = "disabled"; 3749 3750 zap-shader { 3751 memory-region = <&gpu_microcode_mem>; 3752 }; 3753 3754 gpu_opp_table: opp-table { 3755 compatible = "operating-points-v2-adreno", "operating-points-v2"; 3756 3757 opp-1250000000 { 3758 opp-hz = /bits/ 64 <1250000000>; 3759 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L3>; 3760 opp-peak-kBps = <16500000>; 3761 qcom,opp-acd-level = <0xa82a5ffd>; 3762 }; 3763 3764 opp-1175000000 { 3765 opp-hz = /bits/ 64 <1175000000>; 3766 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L2>; 3767 opp-peak-kBps = <14398438>; 3768 qcom,opp-acd-level = <0xa82a5ffd>; 3769 }; 3770 3771 opp-1100000000 { 3772 opp-hz = /bits/ 64 <1100000000>; 3773 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3774 opp-peak-kBps = <14398438>; 3775 qcom,opp-acd-level = <0xa82a5ffd>; 3776 }; 3777 3778 opp-1000000000 { 3779 opp-hz = /bits/ 64 <1000000000>; 3780 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3781 opp-peak-kBps = <14398438>; 3782 qcom,opp-acd-level = <0xa82b5ffd>; 3783 }; 3784 3785 opp-925000000 { 3786 opp-hz = /bits/ 64 <925000000>; 3787 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3788 opp-peak-kBps = <14398438>; 3789 qcom,opp-acd-level = <0xa82b5ffd>; 3790 }; 3791 3792 opp-800000000 { 3793 opp-hz = /bits/ 64 <800000000>; 3794 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3795 opp-peak-kBps = <12449219>; 3796 qcom,opp-acd-level = <0xa82c5ffd>; 3797 }; 3798 3799 opp-744000000 { 3800 opp-hz = /bits/ 64 <744000000>; 3801 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 3802 opp-peak-kBps = <10687500>; 3803 qcom,opp-acd-level = <0x882e5ffd>; 3804 }; 3805 3806 opp-687000000 { 3807 opp-hz = /bits/ 64 <687000000>; 3808 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3809 opp-peak-kBps = <8171875>; 3810 qcom,opp-acd-level = <0x882e5ffd>; 3811 }; 3812 3813 opp-550000000 { 3814 opp-hz = /bits/ 64 <550000000>; 3815 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3816 opp-peak-kBps = <6074219>; 3817 qcom,opp-acd-level = <0xc0285ffd>; 3818 }; 3819 3820 opp-390000000 { 3821 opp-hz = /bits/ 64 <390000000>; 3822 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3823 opp-peak-kBps = <3000000>; 3824 qcom,opp-acd-level = <0xc0285ffd>; 3825 }; 3826 3827 opp-300000000 { 3828 opp-hz = /bits/ 64 <300000000>; 3829 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 3830 opp-peak-kBps = <2136719>; 3831 qcom,opp-acd-level = <0xc02b5ffd>; 3832 }; 3833 }; 3834 }; 3835 3836 gmu: gmu@3d6a000 { 3837 compatible = "qcom,adreno-gmu-x185.1", "qcom,adreno-gmu"; 3838 reg = <0x0 0x03d6a000 0x0 0x35000>, 3839 <0x0 0x03d50000 0x0 0x10000>, 3840 <0x0 0x0b280000 0x0 0x10000>; 3841 reg-names = "gmu", "rscc", "gmu_pdc"; 3842 3843 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 3844 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 3845 interrupt-names = "hfi", "gmu"; 3846 3847 clocks = <&gpucc GPU_CC_AHB_CLK>, 3848 <&gpucc GPU_CC_CX_GMU_CLK>, 3849 <&gpucc GPU_CC_CXO_CLK>, 3850 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 3851 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 3852 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 3853 <&gpucc GPU_CC_DEMET_CLK>; 3854 clock-names = "ahb", 3855 "gmu", 3856 "cxo", 3857 "axi", 3858 "memnoc", 3859 "hub", 3860 "demet"; 3861 3862 power-domains = <&gpucc GPU_CX_GDSC>, 3863 <&gpucc GPU_GX_GDSC>; 3864 power-domain-names = "cx", 3865 "gx"; 3866 3867 iommus = <&adreno_smmu 5 0x0>; 3868 3869 qcom,qmp = <&aoss_qmp>; 3870 3871 operating-points-v2 = <&gmu_opp_table>; 3872 3873 gmu_opp_table: opp-table { 3874 compatible = "operating-points-v2"; 3875 3876 opp-550000000 { 3877 opp-hz = /bits/ 64 <550000000>; 3878 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3879 }; 3880 3881 opp-220000000 { 3882 opp-hz = /bits/ 64 <220000000>; 3883 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3884 }; 3885 }; 3886 }; 3887 3888 gpucc: clock-controller@3d90000 { 3889 compatible = "qcom,x1e80100-gpucc"; 3890 reg = <0 0x03d90000 0 0xa000>; 3891 clocks = <&bi_tcxo_div2>, 3892 <&gcc GCC_GPU_GPLL0_CPH_CLK_SRC>, 3893 <&gcc GCC_GPU_GPLL0_DIV_CPH_CLK_SRC>; 3894 #clock-cells = <1>; 3895 #reset-cells = <1>; 3896 #power-domain-cells = <1>; 3897 }; 3898 3899 adreno_smmu: iommu@3da0000 { 3900 compatible = "qcom,x1e80100-smmu-500", "qcom,adreno-smmu", 3901 "qcom,smmu-500", "arm,mmu-500"; 3902 reg = <0x0 0x03da0000 0x0 0x40000>; 3903 #iommu-cells = <2>; 3904 #global-interrupts = <1>; 3905 interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 3906 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 3907 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 3908 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 3909 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 3910 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 3911 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 3912 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 3913 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 3914 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 3915 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 3916 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>, 3917 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 3918 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, 3919 <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>, 3920 <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>, 3921 <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>, 3922 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>, 3923 <GIC_SPI 660 IRQ_TYPE_LEVEL_HIGH>, 3924 <GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH>, 3925 <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>, 3926 <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>, 3927 <GIC_SPI 667 IRQ_TYPE_LEVEL_HIGH>, 3928 <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>, 3929 <GIC_SPI 670 IRQ_TYPE_LEVEL_HIGH>, 3930 <GIC_SPI 700 IRQ_TYPE_LEVEL_HIGH>; 3931 clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 3932 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 3933 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 3934 <&gpucc GPU_CC_AHB_CLK>; 3935 clock-names = "hlos", 3936 "bus", 3937 "iface", 3938 "ahb"; 3939 power-domains = <&gpucc GPU_CX_GDSC>; 3940 dma-coherent; 3941 }; 3942 3943 gem_noc: interconnect@26400000 { 3944 compatible = "qcom,x1e80100-gem-noc"; 3945 reg = <0 0x26400000 0 0x311200>; 3946 3947 qcom,bcm-voters = <&apps_bcm_voter>; 3948 3949 #interconnect-cells = <2>; 3950 }; 3951 3952 nsp_noc: interconnect@320c0000 { 3953 compatible = "qcom,x1e80100-nsp-noc"; 3954 reg = <0 0x320C0000 0 0xe080>; 3955 3956 qcom,bcm-voters = <&apps_bcm_voter>; 3957 3958 #interconnect-cells = <2>; 3959 }; 3960 3961 remoteproc_adsp: remoteproc@6800000 { 3962 compatible = "qcom,x1e80100-adsp-pas"; 3963 reg = <0x0 0x06800000 0x0 0x10000>; 3964 3965 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 3966 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 3967 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 3968 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 3969 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 3970 interrupt-names = "wdog", 3971 "fatal", 3972 "ready", 3973 "handover", 3974 "stop-ack"; 3975 3976 clocks = <&rpmhcc RPMH_CXO_CLK>; 3977 clock-names = "xo"; 3978 3979 power-domains = <&rpmhpd RPMHPD_LCX>, 3980 <&rpmhpd RPMHPD_LMX>; 3981 power-domain-names = "lcx", 3982 "lmx"; 3983 3984 interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS 3985 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3986 3987 memory-region = <&adspslpi_mem>, 3988 <&q6_adsp_dtb_mem>; 3989 3990 qcom,qmp = <&aoss_qmp>; 3991 3992 qcom,smem-states = <&smp2p_adsp_out 0>; 3993 qcom,smem-state-names = "stop"; 3994 3995 status = "disabled"; 3996 3997 glink-edge { 3998 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 3999 IPCC_MPROC_SIGNAL_GLINK_QMP 4000 IRQ_TYPE_EDGE_RISING>; 4001 mboxes = <&ipcc IPCC_CLIENT_LPASS 4002 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4003 4004 label = "lpass"; 4005 qcom,remote-pid = <2>; 4006 4007 fastrpc { 4008 compatible = "qcom,fastrpc"; 4009 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4010 label = "adsp"; 4011 qcom,non-secure-domain; 4012 #address-cells = <1>; 4013 #size-cells = <0>; 4014 4015 compute-cb@3 { 4016 compatible = "qcom,fastrpc-compute-cb"; 4017 reg = <3>; 4018 iommus = <&apps_smmu 0x1003 0x80>, 4019 <&apps_smmu 0x1063 0x0>; 4020 dma-coherent; 4021 }; 4022 4023 compute-cb@4 { 4024 compatible = "qcom,fastrpc-compute-cb"; 4025 reg = <4>; 4026 iommus = <&apps_smmu 0x1004 0x80>, 4027 <&apps_smmu 0x1064 0x0>; 4028 dma-coherent; 4029 }; 4030 4031 compute-cb@5 { 4032 compatible = "qcom,fastrpc-compute-cb"; 4033 reg = <5>; 4034 iommus = <&apps_smmu 0x1005 0x80>, 4035 <&apps_smmu 0x1065 0x0>; 4036 dma-coherent; 4037 }; 4038 4039 compute-cb@6 { 4040 compatible = "qcom,fastrpc-compute-cb"; 4041 reg = <6>; 4042 iommus = <&apps_smmu 0x1006 0x80>, 4043 <&apps_smmu 0x1066 0x0>; 4044 dma-coherent; 4045 }; 4046 4047 compute-cb@7 { 4048 compatible = "qcom,fastrpc-compute-cb"; 4049 reg = <7>; 4050 iommus = <&apps_smmu 0x1007 0x80>, 4051 <&apps_smmu 0x1067 0x0>; 4052 dma-coherent; 4053 }; 4054 }; 4055 4056 gpr { 4057 compatible = "qcom,gpr"; 4058 qcom,glink-channels = "adsp_apps"; 4059 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 4060 qcom,intents = <512 20>; 4061 #address-cells = <1>; 4062 #size-cells = <0>; 4063 4064 q6apm: service@1 { 4065 compatible = "qcom,q6apm"; 4066 reg = <GPR_APM_MODULE_IID>; 4067 #sound-dai-cells = <0>; 4068 qcom,protection-domain = "avs/audio", 4069 "msm/adsp/audio_pd"; 4070 4071 q6apmbedai: bedais { 4072 compatible = "qcom,q6apm-lpass-dais"; 4073 #sound-dai-cells = <1>; 4074 }; 4075 4076 q6apmdai: dais { 4077 compatible = "qcom,q6apm-dais"; 4078 iommus = <&apps_smmu 0x1001 0x80>, 4079 <&apps_smmu 0x1061 0x0>; 4080 }; 4081 }; 4082 4083 q6prm: service@2 { 4084 compatible = "qcom,q6prm"; 4085 reg = <GPR_PRM_MODULE_IID>; 4086 qcom,protection-domain = "avs/audio", 4087 "msm/adsp/audio_pd"; 4088 4089 q6prmcc: clock-controller { 4090 compatible = "qcom,q6prm-lpass-clocks"; 4091 #clock-cells = <2>; 4092 }; 4093 }; 4094 }; 4095 }; 4096 }; 4097 4098 lpass_wsa2macro: codec@6aa0000 { 4099 compatible = "qcom,x1e80100-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro"; 4100 reg = <0 0x06aa0000 0 0x1000>; 4101 clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4102 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4103 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4104 <&lpass_vamacro>; 4105 clock-names = "mclk", 4106 "macro", 4107 "dcodec", 4108 "fsgen"; 4109 4110 #clock-cells = <0>; 4111 clock-output-names = "wsa2-mclk"; 4112 #sound-dai-cells = <1>; 4113 sound-name-prefix = "WSA2"; 4114 }; 4115 4116 swr3: soundwire@6ab0000 { 4117 compatible = "qcom,soundwire-v2.0.0"; 4118 reg = <0 0x06ab0000 0 0x10000>; 4119 clocks = <&lpass_wsa2macro>; 4120 clock-names = "iface"; 4121 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 4122 label = "WSA2"; 4123 4124 pinctrl-0 = <&wsa2_swr_active>; 4125 pinctrl-names = "default"; 4126 resets = <&lpass_audiocc LPASS_AUDIO_SWR_WSA2_CGCR>; 4127 reset-names = "swr_audio_cgcr"; 4128 4129 qcom,din-ports = <4>; 4130 qcom,dout-ports = <9>; 4131 4132 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 4133 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 4134 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4135 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 4136 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 4137 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 4138 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 4139 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4140 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4141 4142 #address-cells = <2>; 4143 #size-cells = <0>; 4144 #sound-dai-cells = <1>; 4145 status = "disabled"; 4146 }; 4147 4148 lpass_rxmacro: codec@6ac0000 { 4149 compatible = "qcom,x1e80100-lpass-rx-macro", "qcom,sm8550-lpass-rx-macro"; 4150 reg = <0 0x06ac0000 0 0x1000>; 4151 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4152 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4153 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4154 <&lpass_vamacro>; 4155 clock-names = "mclk", 4156 "macro", 4157 "dcodec", 4158 "fsgen"; 4159 4160 #clock-cells = <0>; 4161 clock-output-names = "mclk"; 4162 #sound-dai-cells = <1>; 4163 }; 4164 4165 swr1: soundwire@6ad0000 { 4166 compatible = "qcom,soundwire-v2.0.0"; 4167 reg = <0 0x06ad0000 0 0x10000>; 4168 clocks = <&lpass_rxmacro>; 4169 clock-names = "iface"; 4170 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 4171 label = "RX"; 4172 4173 pinctrl-0 = <&rx_swr_active>; 4174 pinctrl-names = "default"; 4175 4176 resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>; 4177 reset-names = "swr_audio_cgcr"; 4178 qcom,din-ports = <1>; 4179 qcom,dout-ports = <11>; 4180 4181 qcom,ports-sinterval = /bits/ 16 <0x03 0x1f 0x1f 0x07 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4182 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4183 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4184 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4185 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0x0f 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4186 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4187 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4188 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4189 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4190 4191 #address-cells = <2>; 4192 #size-cells = <0>; 4193 #sound-dai-cells = <1>; 4194 status = "disabled"; 4195 }; 4196 4197 lpass_txmacro: codec@6ae0000 { 4198 compatible = "qcom,x1e80100-lpass-tx-macro", "qcom,sm8550-lpass-tx-macro"; 4199 reg = <0 0x06ae0000 0 0x1000>; 4200 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4201 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4202 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4203 <&lpass_vamacro>; 4204 clock-names = "mclk", 4205 "macro", 4206 "dcodec", 4207 "fsgen"; 4208 4209 #clock-cells = <0>; 4210 clock-output-names = "mclk"; 4211 #sound-dai-cells = <1>; 4212 }; 4213 4214 lpass_wsamacro: codec@6b00000 { 4215 compatible = "qcom,x1e80100-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro"; 4216 reg = <0 0x06b00000 0 0x1000>; 4217 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4218 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4219 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4220 <&lpass_vamacro>; 4221 clock-names = "mclk", 4222 "macro", 4223 "dcodec", 4224 "fsgen"; 4225 4226 #clock-cells = <0>; 4227 clock-output-names = "mclk"; 4228 #sound-dai-cells = <1>; 4229 sound-name-prefix = "WSA"; 4230 }; 4231 4232 swr0: soundwire@6b10000 { 4233 compatible = "qcom,soundwire-v2.0.0"; 4234 reg = <0 0x06b10000 0 0x10000>; 4235 clocks = <&lpass_wsamacro>; 4236 clock-names = "iface"; 4237 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 4238 label = "WSA"; 4239 4240 pinctrl-0 = <&wsa_swr_active>; 4241 pinctrl-names = "default"; 4242 resets = <&lpass_audiocc LPASS_AUDIO_SWR_WSA_CGCR>; 4243 reset-names = "swr_audio_cgcr"; 4244 4245 qcom,din-ports = <4>; 4246 qcom,dout-ports = <9>; 4247 4248 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 4249 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 4250 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4251 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 4252 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 4253 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 4254 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 4255 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4256 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4257 4258 #address-cells = <2>; 4259 #size-cells = <0>; 4260 #sound-dai-cells = <1>; 4261 status = "disabled"; 4262 }; 4263 4264 lpass_audiocc: clock-controller@6b6c000 { 4265 compatible = "qcom,x1e80100-lpassaudiocc", "qcom,sc8280xp-lpassaudiocc"; 4266 reg = <0 0x06b6c000 0 0x1000>; 4267 #clock-cells = <1>; 4268 #reset-cells = <1>; 4269 }; 4270 4271 swr2: soundwire@6d30000 { 4272 compatible = "qcom,soundwire-v2.0.0"; 4273 reg = <0 0x06d30000 0 0x10000>; 4274 clocks = <&lpass_txmacro>; 4275 clock-names = "iface"; 4276 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 4277 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; 4278 interrupt-names = "core", "wakeup"; 4279 label = "TX"; 4280 resets = <&lpasscc LPASS_AUDIO_SWR_TX_CGCR>; 4281 reset-names = "swr_audio_cgcr"; 4282 4283 pinctrl-0 = <&tx_swr_active>; 4284 pinctrl-names = "default"; 4285 4286 qcom,din-ports = <4>; 4287 qcom,dout-ports = <1>; 4288 4289 qcom,ports-sinterval-low = /bits/ 8 <0x00 0x01 0x03 0x03 0x00>; 4290 qcom,ports-offset1 = /bits/ 8 <0x00 0x01 0x02 0x00 0x00>; 4291 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00 0xff>; 4292 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 4293 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 4294 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 4295 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 4296 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 4297 qcom,ports-lane-control = /bits/ 8 <0xff 0x00 0x00 0x01 0xff>; 4298 4299 #address-cells = <2>; 4300 #size-cells = <0>; 4301 #sound-dai-cells = <1>; 4302 status = "disabled"; 4303 }; 4304 4305 lpass_vamacro: codec@6d44000 { 4306 compatible = "qcom,x1e80100-lpass-va-macro", "qcom,sm8550-lpass-va-macro"; 4307 reg = <0 0x06d44000 0 0x1000>; 4308 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4309 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4310 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 4311 clock-names = "mclk", 4312 "macro", 4313 "dcodec"; 4314 4315 #clock-cells = <0>; 4316 clock-output-names = "fsgen"; 4317 #sound-dai-cells = <1>; 4318 }; 4319 4320 lpass_tlmm: pinctrl@6e80000 { 4321 compatible = "qcom,x1e80100-lpass-lpi-pinctrl", "qcom,sm8550-lpass-lpi-pinctrl"; 4322 reg = <0 0x06e80000 0 0x20000>, 4323 <0 0x07250000 0 0x10000>; 4324 4325 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4326 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 4327 clock-names = "core", "audio"; 4328 4329 gpio-controller; 4330 #gpio-cells = <2>; 4331 gpio-ranges = <&lpass_tlmm 0 0 23>; 4332 4333 tx_swr_active: tx-swr-active-state { 4334 clk-pins { 4335 pins = "gpio0"; 4336 function = "swr_tx_clk"; 4337 drive-strength = <2>; 4338 slew-rate = <1>; 4339 bias-disable; 4340 }; 4341 4342 data-pins { 4343 pins = "gpio1", "gpio2"; 4344 function = "swr_tx_data"; 4345 drive-strength = <2>; 4346 slew-rate = <1>; 4347 bias-bus-hold; 4348 }; 4349 }; 4350 4351 rx_swr_active: rx-swr-active-state { 4352 clk-pins { 4353 pins = "gpio3"; 4354 function = "swr_rx_clk"; 4355 drive-strength = <2>; 4356 slew-rate = <1>; 4357 bias-disable; 4358 }; 4359 4360 data-pins { 4361 pins = "gpio4", "gpio5"; 4362 function = "swr_rx_data"; 4363 drive-strength = <2>; 4364 slew-rate = <1>; 4365 bias-bus-hold; 4366 }; 4367 }; 4368 4369 dmic01_default: dmic01-default-state { 4370 clk-pins { 4371 pins = "gpio6"; 4372 function = "dmic1_clk"; 4373 drive-strength = <8>; 4374 output-high; 4375 }; 4376 4377 data-pins { 4378 pins = "gpio7"; 4379 function = "dmic1_data"; 4380 drive-strength = <8>; 4381 input-enable; 4382 }; 4383 }; 4384 4385 dmic23_default: dmic23-default-state { 4386 clk-pins { 4387 pins = "gpio8"; 4388 function = "dmic2_clk"; 4389 drive-strength = <8>; 4390 output-high; 4391 }; 4392 4393 data-pins { 4394 pins = "gpio9"; 4395 function = "dmic2_data"; 4396 drive-strength = <8>; 4397 input-enable; 4398 }; 4399 }; 4400 4401 wsa_swr_active: wsa-swr-active-state { 4402 clk-pins { 4403 pins = "gpio10"; 4404 function = "wsa_swr_clk"; 4405 drive-strength = <2>; 4406 slew-rate = <1>; 4407 bias-disable; 4408 }; 4409 4410 data-pins { 4411 pins = "gpio11"; 4412 function = "wsa_swr_data"; 4413 drive-strength = <2>; 4414 slew-rate = <1>; 4415 bias-bus-hold; 4416 }; 4417 }; 4418 4419 wsa2_swr_active: wsa2-swr-active-state { 4420 clk-pins { 4421 pins = "gpio15"; 4422 function = "wsa2_swr_clk"; 4423 drive-strength = <2>; 4424 slew-rate = <1>; 4425 bias-disable; 4426 }; 4427 4428 data-pins { 4429 pins = "gpio16"; 4430 function = "wsa2_swr_data"; 4431 drive-strength = <2>; 4432 slew-rate = <1>; 4433 bias-bus-hold; 4434 }; 4435 }; 4436 }; 4437 4438 lpasscc: clock-controller@6ea0000 { 4439 compatible = "qcom,x1e80100-lpasscc", "qcom,sc8280xp-lpasscc"; 4440 reg = <0 0x06ea0000 0 0x12000>; 4441 #clock-cells = <1>; 4442 #reset-cells = <1>; 4443 }; 4444 4445 lpass_ag_noc: interconnect@7e40000 { 4446 compatible = "qcom,x1e80100-lpass-ag-noc"; 4447 reg = <0 0x07e40000 0 0xe080>; 4448 4449 qcom,bcm-voters = <&apps_bcm_voter>; 4450 4451 #interconnect-cells = <2>; 4452 }; 4453 4454 lpass_lpiaon_noc: interconnect@7400000 { 4455 compatible = "qcom,x1e80100-lpass-lpiaon-noc"; 4456 reg = <0 0x07400000 0 0x19080>; 4457 4458 qcom,bcm-voters = <&apps_bcm_voter>; 4459 4460 #interconnect-cells = <2>; 4461 }; 4462 4463 lpass_lpicx_noc: interconnect@7430000 { 4464 compatible = "qcom,x1e80100-lpass-lpicx-noc"; 4465 reg = <0 0x07430000 0 0x3A200>; 4466 4467 qcom,bcm-voters = <&apps_bcm_voter>; 4468 4469 #interconnect-cells = <2>; 4470 }; 4471 4472 sdhc_2: mmc@8804000 { 4473 compatible = "qcom,x1e80100-sdhci", "qcom,sdhci-msm-v5"; 4474 reg = <0 0x08804000 0 0x1000>; 4475 4476 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 4477 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 4478 interrupt-names = "hc_irq", "pwr_irq"; 4479 4480 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 4481 <&gcc GCC_SDCC2_APPS_CLK>, 4482 <&rpmhcc RPMH_CXO_CLK>; 4483 clock-names = "iface", "core", "xo"; 4484 iommus = <&apps_smmu 0x520 0>; 4485 qcom,dll-config = <0x0007642c>; 4486 qcom,ddr-config = <0x80040868>; 4487 power-domains = <&rpmhpd RPMHPD_CX>; 4488 operating-points-v2 = <&sdhc2_opp_table>; 4489 4490 interconnects = <&aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS 4491 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4492 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4493 &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>; 4494 interconnect-names = "sdhc-ddr", "cpu-sdhc"; 4495 bus-width = <4>; 4496 dma-coherent; 4497 4498 status = "disabled"; 4499 4500 sdhc2_opp_table: opp-table { 4501 compatible = "operating-points-v2"; 4502 4503 opp-19200000 { 4504 opp-hz = /bits/ 64 <19200000>; 4505 required-opps = <&rpmhpd_opp_min_svs>; 4506 }; 4507 4508 opp-50000000 { 4509 opp-hz = /bits/ 64 <50000000>; 4510 required-opps = <&rpmhpd_opp_low_svs>; 4511 }; 4512 4513 opp-100000000 { 4514 opp-hz = /bits/ 64 <100000000>; 4515 required-opps = <&rpmhpd_opp_svs>; 4516 }; 4517 4518 opp-202000000 { 4519 opp-hz = /bits/ 64 <202000000>; 4520 required-opps = <&rpmhpd_opp_svs_l1>; 4521 }; 4522 }; 4523 }; 4524 4525 sdhc_4: mmc@8844000 { 4526 compatible = "qcom,x1e80100-sdhci", "qcom,sdhci-msm-v5"; 4527 reg = <0 0x08844000 0 0x1000>; 4528 4529 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 4530 <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 4531 interrupt-names = "hc_irq", "pwr_irq"; 4532 4533 clocks = <&gcc GCC_SDCC4_AHB_CLK>, 4534 <&gcc GCC_SDCC4_APPS_CLK>, 4535 <&rpmhcc RPMH_CXO_CLK>; 4536 clock-names = "iface", "core", "xo"; 4537 iommus = <&apps_smmu 0x160 0>; 4538 qcom,dll-config = <0x0007642c>; 4539 qcom,ddr-config = <0x80040868>; 4540 power-domains = <&rpmhpd RPMHPD_CX>; 4541 operating-points-v2 = <&sdhc4_opp_table>; 4542 4543 interconnects = <&aggre2_noc MASTER_SDCC_4 QCOM_ICC_TAG_ALWAYS 4544 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4545 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4546 &config_noc SLAVE_SDCC_4 QCOM_ICC_TAG_ACTIVE_ONLY>; 4547 interconnect-names = "sdhc-ddr", "cpu-sdhc"; 4548 bus-width = <4>; 4549 dma-coherent; 4550 4551 status = "disabled"; 4552 4553 sdhc4_opp_table: opp-table { 4554 compatible = "operating-points-v2"; 4555 4556 opp-19200000 { 4557 opp-hz = /bits/ 64 <19200000>; 4558 required-opps = <&rpmhpd_opp_min_svs>; 4559 }; 4560 4561 opp-50000000 { 4562 opp-hz = /bits/ 64 <50000000>; 4563 required-opps = <&rpmhpd_opp_low_svs>; 4564 }; 4565 4566 opp-100000000 { 4567 opp-hz = /bits/ 64 <100000000>; 4568 required-opps = <&rpmhpd_opp_svs>; 4569 }; 4570 4571 opp-202000000 { 4572 opp-hz = /bits/ 64 <202000000>; 4573 required-opps = <&rpmhpd_opp_svs_l1>; 4574 }; 4575 }; 4576 }; 4577 4578 usb_2_hsphy: phy@88e0000 { 4579 compatible = "qcom,x1e80100-snps-eusb2-phy", 4580 "qcom,sm8550-snps-eusb2-phy"; 4581 reg = <0 0x088e0000 0 0x154>; 4582 #phy-cells = <0>; 4583 4584 clocks = <&tcsr TCSR_USB2_2_CLKREF_EN>; 4585 clock-names = "ref"; 4586 4587 resets = <&gcc GCC_QUSB2PHY_USB20_HS_BCR>; 4588 4589 status = "disabled"; 4590 }; 4591 4592 usb_mp_hsphy0: phy@88e1000 { 4593 compatible = "qcom,x1e80100-snps-eusb2-phy", 4594 "qcom,sm8550-snps-eusb2-phy"; 4595 reg = <0 0x088e1000 0 0x154>; 4596 #phy-cells = <0>; 4597 4598 clocks = <&tcsr TCSR_USB3_MP0_CLKREF_EN>; 4599 clock-names = "ref"; 4600 4601 resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>; 4602 4603 status = "disabled"; 4604 }; 4605 4606 usb_mp_hsphy1: phy@88e2000 { 4607 compatible = "qcom,x1e80100-snps-eusb2-phy", 4608 "qcom,sm8550-snps-eusb2-phy"; 4609 reg = <0 0x088e2000 0 0x154>; 4610 #phy-cells = <0>; 4611 4612 clocks = <&tcsr TCSR_USB3_MP1_CLKREF_EN>; 4613 clock-names = "ref"; 4614 4615 resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>; 4616 4617 status = "disabled"; 4618 }; 4619 4620 usb_mp_qmpphy0: phy@88e3000 { 4621 compatible = "qcom,x1e80100-qmp-usb3-uni-phy"; 4622 reg = <0 0x088e3000 0 0x2000>; 4623 4624 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 4625 <&rpmhcc RPMH_CXO_CLK>, 4626 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 4627 <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>; 4628 clock-names = "aux", 4629 "ref", 4630 "com_aux", 4631 "pipe"; 4632 4633 resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>, 4634 <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>; 4635 reset-names = "phy", 4636 "phy_phy"; 4637 4638 power-domains = <&gcc GCC_USB3_MP_SS0_PHY_GDSC>; 4639 4640 #clock-cells = <0>; 4641 clock-output-names = "usb_mp_phy0_pipe_clk"; 4642 4643 #phy-cells = <0>; 4644 4645 status = "disabled"; 4646 }; 4647 4648 usb_mp_qmpphy1: phy@88e5000 { 4649 compatible = "qcom,x1e80100-qmp-usb3-uni-phy"; 4650 reg = <0 0x088e5000 0 0x2000>; 4651 4652 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 4653 <&rpmhcc RPMH_CXO_CLK>, 4654 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 4655 <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>; 4656 clock-names = "aux", 4657 "ref", 4658 "com_aux", 4659 "pipe"; 4660 4661 resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>, 4662 <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>; 4663 reset-names = "phy", 4664 "phy_phy"; 4665 4666 power-domains = <&gcc GCC_USB3_MP_SS1_PHY_GDSC>; 4667 4668 #clock-cells = <0>; 4669 clock-output-names = "usb_mp_phy1_pipe_clk"; 4670 4671 #phy-cells = <0>; 4672 4673 status = "disabled"; 4674 }; 4675 4676 usb_1_ss2: usb@a0f8800 { 4677 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3"; 4678 reg = <0 0x0a0f8800 0 0x400>; 4679 4680 clocks = <&gcc GCC_CFG_NOC_USB3_TERT_AXI_CLK>, 4681 <&gcc GCC_USB30_TERT_MASTER_CLK>, 4682 <&gcc GCC_AGGRE_USB3_TERT_AXI_CLK>, 4683 <&gcc GCC_USB30_TERT_SLEEP_CLK>, 4684 <&gcc GCC_USB30_TERT_MOCK_UTMI_CLK>, 4685 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 4686 <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>, 4687 <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>, 4688 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 4689 clock-names = "cfg_noc", 4690 "core", 4691 "iface", 4692 "sleep", 4693 "mock_utmi", 4694 "noc_aggr", 4695 "noc_aggr_north", 4696 "noc_aggr_south", 4697 "noc_sys"; 4698 4699 assigned-clocks = <&gcc GCC_USB30_TERT_MOCK_UTMI_CLK>, 4700 <&gcc GCC_USB30_TERT_MASTER_CLK>; 4701 assigned-clock-rates = <19200000>, 4702 <200000000>; 4703 4704 interrupts-extended = <&intc GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, 4705 <&pdc 58 IRQ_TYPE_EDGE_BOTH>, 4706 <&pdc 57 IRQ_TYPE_EDGE_BOTH>, 4707 <&pdc 10 IRQ_TYPE_LEVEL_HIGH>; 4708 interrupt-names = "pwr_event", 4709 "dp_hs_phy_irq", 4710 "dm_hs_phy_irq", 4711 "ss_phy_irq"; 4712 4713 power-domains = <&gcc GCC_USB30_TERT_GDSC>; 4714 required-opps = <&rpmhpd_opp_nom>; 4715 4716 resets = <&gcc GCC_USB30_TERT_BCR>; 4717 4718 interconnects = <&usb_south_anoc MASTER_USB3_2 QCOM_ICC_TAG_ALWAYS 4719 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4720 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 4721 &config_noc SLAVE_USB3_2 QCOM_ICC_TAG_ALWAYS>; 4722 interconnect-names = "usb-ddr", 4723 "apps-usb"; 4724 4725 wakeup-source; 4726 4727 #address-cells = <2>; 4728 #size-cells = <2>; 4729 ranges; 4730 4731 status = "disabled"; 4732 4733 usb_1_ss2_dwc3: usb@a000000 { 4734 compatible = "snps,dwc3"; 4735 reg = <0 0x0a000000 0 0xcd00>; 4736 4737 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 4738 4739 iommus = <&apps_smmu 0x14a0 0x0>; 4740 4741 phys = <&usb_1_ss2_hsphy>, 4742 <&usb_1_ss2_qmpphy QMP_USB43DP_USB3_PHY>; 4743 phy-names = "usb2-phy", 4744 "usb3-phy"; 4745 4746 snps,dis_u2_susphy_quirk; 4747 snps,dis_enblslpm_quirk; 4748 snps,usb3_lpm_capable; 4749 snps,dis-u1-entry-quirk; 4750 snps,dis-u2-entry-quirk; 4751 4752 dma-coherent; 4753 4754 ports { 4755 #address-cells = <1>; 4756 #size-cells = <0>; 4757 4758 port@0 { 4759 reg = <0>; 4760 4761 usb_1_ss2_dwc3_hs: endpoint { 4762 }; 4763 }; 4764 4765 port@1 { 4766 reg = <1>; 4767 4768 usb_1_ss2_dwc3_ss: endpoint { 4769 remote-endpoint = <&usb_1_ss2_qmpphy_usb_ss_in>; 4770 }; 4771 }; 4772 }; 4773 }; 4774 }; 4775 4776 usb_2: usb@a2f8800 { 4777 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3"; 4778 reg = <0 0x0a2f8800 0 0x400>; 4779 #address-cells = <2>; 4780 #size-cells = <2>; 4781 ranges; 4782 4783 clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>, 4784 <&gcc GCC_USB20_MASTER_CLK>, 4785 <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, 4786 <&gcc GCC_USB20_SLEEP_CLK>, 4787 <&gcc GCC_USB20_MOCK_UTMI_CLK>, 4788 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 4789 <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>, 4790 <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>, 4791 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 4792 clock-names = "cfg_noc", 4793 "core", 4794 "iface", 4795 "sleep", 4796 "mock_utmi", 4797 "noc_aggr", 4798 "noc_aggr_north", 4799 "noc_aggr_south", 4800 "noc_sys"; 4801 4802 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 4803 <&gcc GCC_USB20_MASTER_CLK>; 4804 assigned-clock-rates = <19200000>, <200000000>; 4805 4806 interrupts-extended = <&intc GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 4807 <&pdc 50 IRQ_TYPE_EDGE_BOTH>, 4808 <&pdc 49 IRQ_TYPE_EDGE_BOTH>; 4809 interrupt-names = "pwr_event", 4810 "dp_hs_phy_irq", 4811 "dm_hs_phy_irq"; 4812 4813 power-domains = <&gcc GCC_USB20_PRIM_GDSC>; 4814 required-opps = <&rpmhpd_opp_nom>; 4815 4816 resets = <&gcc GCC_USB20_PRIM_BCR>; 4817 4818 interconnects = <&usb_north_anoc MASTER_USB2 QCOM_ICC_TAG_ALWAYS 4819 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4820 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 4821 &config_noc SLAVE_USB2 QCOM_ICC_TAG_ALWAYS>; 4822 interconnect-names = "usb-ddr", 4823 "apps-usb"; 4824 4825 wakeup-source; 4826 4827 status = "disabled"; 4828 4829 usb_2_dwc3: usb@a200000 { 4830 compatible = "snps,dwc3"; 4831 reg = <0 0x0a200000 0 0xcd00>; 4832 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 4833 iommus = <&apps_smmu 0x14e0 0x0>; 4834 phys = <&usb_2_hsphy>; 4835 phy-names = "usb2-phy"; 4836 maximum-speed = "high-speed"; 4837 snps,dis-u1-entry-quirk; 4838 snps,dis-u2-entry-quirk; 4839 4840 ports { 4841 #address-cells = <1>; 4842 #size-cells = <0>; 4843 4844 port@0 { 4845 reg = <0>; 4846 4847 usb_2_dwc3_hs: endpoint { 4848 }; 4849 }; 4850 }; 4851 }; 4852 }; 4853 4854 usb_mp: usb@a4f8800 { 4855 compatible = "qcom,x1e80100-dwc3-mp", "qcom,dwc3"; 4856 reg = <0 0x0a4f8800 0 0x400>; 4857 4858 clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>, 4859 <&gcc GCC_USB30_MP_MASTER_CLK>, 4860 <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>, 4861 <&gcc GCC_USB30_MP_SLEEP_CLK>, 4862 <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, 4863 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 4864 <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>, 4865 <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>, 4866 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 4867 clock-names = "cfg_noc", 4868 "core", 4869 "iface", 4870 "sleep", 4871 "mock_utmi", 4872 "noc_aggr", 4873 "noc_aggr_north", 4874 "noc_aggr_south", 4875 "noc_sys"; 4876 4877 assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, 4878 <&gcc GCC_USB30_MP_MASTER_CLK>; 4879 assigned-clock-rates = <19200000>, 4880 <200000000>; 4881 4882 interrupts-extended = <&intc GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 4883 <&intc GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 4884 <&intc GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 4885 <&intc GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 4886 <&pdc 52 IRQ_TYPE_EDGE_BOTH>, 4887 <&pdc 51 IRQ_TYPE_EDGE_BOTH>, 4888 <&pdc 54 IRQ_TYPE_EDGE_BOTH>, 4889 <&pdc 53 IRQ_TYPE_EDGE_BOTH>, 4890 <&pdc 55 IRQ_TYPE_LEVEL_HIGH>, 4891 <&pdc 56 IRQ_TYPE_LEVEL_HIGH>; 4892 interrupt-names = "pwr_event_1", "pwr_event_2", 4893 "hs_phy_1", "hs_phy_2", 4894 "dp_hs_phy_1", "dm_hs_phy_1", 4895 "dp_hs_phy_2", "dm_hs_phy_2", 4896 "ss_phy_1", "ss_phy_2"; 4897 4898 power-domains = <&gcc GCC_USB30_MP_GDSC>; 4899 required-opps = <&rpmhpd_opp_nom>; 4900 4901 resets = <&gcc GCC_USB30_MP_BCR>; 4902 4903 interconnects = <&usb_north_anoc MASTER_USB3_MP QCOM_ICC_TAG_ALWAYS 4904 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4905 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 4906 &config_noc SLAVE_USB3_MP QCOM_ICC_TAG_ALWAYS>; 4907 interconnect-names = "usb-ddr", 4908 "apps-usb"; 4909 4910 wakeup-source; 4911 4912 #address-cells = <2>; 4913 #size-cells = <2>; 4914 ranges; 4915 4916 status = "disabled"; 4917 4918 usb_mp_dwc3: usb@a400000 { 4919 compatible = "snps,dwc3"; 4920 reg = <0 0x0a400000 0 0xcd00>; 4921 4922 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 4923 4924 iommus = <&apps_smmu 0x1400 0x0>; 4925 4926 phys = <&usb_mp_hsphy0>, <&usb_mp_qmpphy0>, 4927 <&usb_mp_hsphy1>, <&usb_mp_qmpphy1>; 4928 phy-names = "usb2-0", "usb3-0", 4929 "usb2-1", "usb3-1"; 4930 dr_mode = "host"; 4931 4932 snps,dis_u2_susphy_quirk; 4933 snps,dis_enblslpm_quirk; 4934 snps,usb3_lpm_capable; 4935 snps,dis-u1-entry-quirk; 4936 snps,dis-u2-entry-quirk; 4937 4938 dma-coherent; 4939 }; 4940 }; 4941 4942 usb_1_ss0: usb@a6f8800 { 4943 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3"; 4944 reg = <0 0x0a6f8800 0 0x400>; 4945 4946 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 4947 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 4948 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 4949 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 4950 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4951 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 4952 <&gcc GCC_CFG_NOC_USB_ANOC_NORTH_AHB_CLK>, 4953 <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>, 4954 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 4955 clock-names = "cfg_noc", 4956 "core", 4957 "iface", 4958 "sleep", 4959 "mock_utmi", 4960 "noc_aggr", 4961 "noc_aggr_north", 4962 "noc_aggr_south", 4963 "noc_sys"; 4964 4965 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4966 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 4967 assigned-clock-rates = <19200000>, 4968 <200000000>; 4969 4970 interrupts-extended = <&intc GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>, 4971 <&pdc 61 IRQ_TYPE_EDGE_BOTH>, 4972 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 4973 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 4974 interrupt-names = "pwr_event", 4975 "dp_hs_phy_irq", 4976 "dm_hs_phy_irq", 4977 "ss_phy_irq"; 4978 4979 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 4980 required-opps = <&rpmhpd_opp_nom>; 4981 4982 resets = <&gcc GCC_USB30_PRIM_BCR>; 4983 4984 wakeup-source; 4985 4986 #address-cells = <2>; 4987 #size-cells = <2>; 4988 ranges; 4989 4990 status = "disabled"; 4991 4992 usb_1_ss0_dwc3: usb@a600000 { 4993 compatible = "snps,dwc3"; 4994 reg = <0 0x0a600000 0 0xcd00>; 4995 4996 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 4997 4998 iommus = <&apps_smmu 0x1420 0x0>; 4999 5000 phys = <&usb_1_ss0_hsphy>, 5001 <&usb_1_ss0_qmpphy QMP_USB43DP_USB3_PHY>; 5002 phy-names = "usb2-phy", 5003 "usb3-phy"; 5004 5005 snps,dis_u2_susphy_quirk; 5006 snps,dis_enblslpm_quirk; 5007 snps,usb3_lpm_capable; 5008 snps,dis-u1-entry-quirk; 5009 snps,dis-u2-entry-quirk; 5010 5011 dma-coherent; 5012 5013 ports { 5014 #address-cells = <1>; 5015 #size-cells = <0>; 5016 5017 port@0 { 5018 reg = <0>; 5019 5020 usb_1_ss0_dwc3_hs: endpoint { 5021 }; 5022 }; 5023 5024 port@1 { 5025 reg = <1>; 5026 5027 usb_1_ss0_dwc3_ss: endpoint { 5028 remote-endpoint = <&usb_1_ss0_qmpphy_usb_ss_in>; 5029 }; 5030 }; 5031 }; 5032 }; 5033 }; 5034 5035 usb_1_ss1: usb@a8f8800 { 5036 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3"; 5037 reg = <0 0x0a8f8800 0 0x400>; 5038 5039 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 5040 <&gcc GCC_USB30_SEC_MASTER_CLK>, 5041 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 5042 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 5043 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 5044 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 5045 <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>, 5046 <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>, 5047 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 5048 clock-names = "cfg_noc", 5049 "core", 5050 "iface", 5051 "sleep", 5052 "mock_utmi", 5053 "noc_aggr", 5054 "noc_aggr_north", 5055 "noc_aggr_south", 5056 "noc_sys"; 5057 5058 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 5059 <&gcc GCC_USB30_SEC_MASTER_CLK>; 5060 assigned-clock-rates = <19200000>, 5061 <200000000>; 5062 5063 interrupts-extended = <&intc GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>, 5064 <&pdc 60 IRQ_TYPE_EDGE_BOTH>, 5065 <&pdc 11 IRQ_TYPE_EDGE_BOTH>, 5066 <&pdc 47 IRQ_TYPE_LEVEL_HIGH>; 5067 interrupt-names = "pwr_event", 5068 "dp_hs_phy_irq", 5069 "dm_hs_phy_irq", 5070 "ss_phy_irq"; 5071 5072 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 5073 required-opps = <&rpmhpd_opp_nom>; 5074 5075 resets = <&gcc GCC_USB30_SEC_BCR>; 5076 5077 interconnects = <&usb_south_anoc MASTER_USB3_1 QCOM_ICC_TAG_ALWAYS 5078 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 5079 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 5080 &config_noc SLAVE_USB3_1 QCOM_ICC_TAG_ALWAYS>; 5081 interconnect-names = "usb-ddr", 5082 "apps-usb"; 5083 5084 wakeup-source; 5085 5086 #address-cells = <2>; 5087 #size-cells = <2>; 5088 ranges; 5089 5090 status = "disabled"; 5091 5092 usb_1_ss1_dwc3: usb@a800000 { 5093 compatible = "snps,dwc3"; 5094 reg = <0 0x0a800000 0 0xcd00>; 5095 5096 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 5097 5098 iommus = <&apps_smmu 0x1460 0x0>; 5099 5100 phys = <&usb_1_ss1_hsphy>, 5101 <&usb_1_ss1_qmpphy QMP_USB43DP_USB3_PHY>; 5102 phy-names = "usb2-phy", 5103 "usb3-phy"; 5104 5105 snps,dis_u2_susphy_quirk; 5106 snps,dis_enblslpm_quirk; 5107 snps,usb3_lpm_capable; 5108 snps,dis-u1-entry-quirk; 5109 snps,dis-u2-entry-quirk; 5110 5111 dma-coherent; 5112 5113 ports { 5114 #address-cells = <1>; 5115 #size-cells = <0>; 5116 5117 port@0 { 5118 reg = <0>; 5119 5120 usb_1_ss1_dwc3_hs: endpoint { 5121 }; 5122 }; 5123 5124 port@1 { 5125 reg = <1>; 5126 5127 usb_1_ss1_dwc3_ss: endpoint { 5128 remote-endpoint = <&usb_1_ss1_qmpphy_usb_ss_in>; 5129 }; 5130 }; 5131 }; 5132 }; 5133 }; 5134 5135 mdss: display-subsystem@ae00000 { 5136 compatible = "qcom,x1e80100-mdss"; 5137 reg = <0 0x0ae00000 0 0x1000>; 5138 reg-names = "mdss"; 5139 5140 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 5141 5142 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5143 <&gcc GCC_DISP_HF_AXI_CLK>, 5144 <&dispcc DISP_CC_MDSS_MDP_CLK>; 5145 5146 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 5147 5148 interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS 5149 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 5150 <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS 5151 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 5152 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5153 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 5154 interconnect-names = "mdp0-mem", 5155 "mdp1-mem", 5156 "cpu-cfg"; 5157 5158 power-domains = <&dispcc MDSS_GDSC>; 5159 5160 iommus = <&apps_smmu 0x1c00 0x2>; 5161 5162 interrupt-controller; 5163 #interrupt-cells = <1>; 5164 5165 #address-cells = <2>; 5166 #size-cells = <2>; 5167 ranges; 5168 5169 status = "disabled"; 5170 5171 mdss_mdp: display-controller@ae01000 { 5172 compatible = "qcom,x1e80100-dpu"; 5173 reg = <0 0x0ae01000 0 0x8f000>, 5174 <0 0x0aeb0000 0 0x2008>; 5175 reg-names = "mdp", 5176 "vbif"; 5177 5178 interrupts-extended = <&mdss 0>; 5179 5180 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 5181 <&dispcc DISP_CC_MDSS_AHB_CLK>, 5182 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 5183 <&dispcc DISP_CC_MDSS_MDP_CLK>, 5184 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 5185 clock-names = "nrt_bus", 5186 "iface", 5187 "lut", 5188 "core", 5189 "vsync"; 5190 5191 operating-points-v2 = <&mdp_opp_table>; 5192 5193 power-domains = <&rpmhpd RPMHPD_MMCX>; 5194 5195 ports { 5196 #address-cells = <1>; 5197 #size-cells = <0>; 5198 5199 port@0 { 5200 reg = <0>; 5201 5202 mdss_intf0_out: endpoint { 5203 remote-endpoint = <&mdss_dp0_in>; 5204 }; 5205 }; 5206 5207 port@4 { 5208 reg = <4>; 5209 5210 mdss_intf4_out: endpoint { 5211 remote-endpoint = <&mdss_dp1_in>; 5212 }; 5213 }; 5214 5215 port@5 { 5216 reg = <5>; 5217 5218 mdss_intf5_out: endpoint { 5219 remote-endpoint = <&mdss_dp3_in>; 5220 }; 5221 }; 5222 5223 port@6 { 5224 reg = <6>; 5225 5226 mdss_intf6_out: endpoint { 5227 remote-endpoint = <&mdss_dp2_in>; 5228 }; 5229 }; 5230 }; 5231 5232 mdp_opp_table: opp-table { 5233 compatible = "operating-points-v2"; 5234 5235 opp-200000000 { 5236 opp-hz = /bits/ 64 <200000000>; 5237 required-opps = <&rpmhpd_opp_low_svs>; 5238 }; 5239 5240 opp-325000000 { 5241 opp-hz = /bits/ 64 <325000000>; 5242 required-opps = <&rpmhpd_opp_svs>; 5243 }; 5244 5245 opp-375000000 { 5246 opp-hz = /bits/ 64 <375000000>; 5247 required-opps = <&rpmhpd_opp_svs_l1>; 5248 }; 5249 5250 opp-514000000 { 5251 opp-hz = /bits/ 64 <514000000>; 5252 required-opps = <&rpmhpd_opp_nom>; 5253 }; 5254 5255 opp-575000000 { 5256 opp-hz = /bits/ 64 <575000000>; 5257 required-opps = <&rpmhpd_opp_nom_l1>; 5258 }; 5259 }; 5260 }; 5261 5262 mdss_dp0: displayport-controller@ae90000 { 5263 compatible = "qcom,x1e80100-dp"; 5264 reg = <0 0x0ae90000 0 0x200>, 5265 <0 0x0ae90200 0 0x200>, 5266 <0 0x0ae90400 0 0x600>, 5267 <0 0x0ae91000 0 0x400>, 5268 <0 0x0ae91400 0 0x400>; 5269 5270 interrupts-extended = <&mdss 12>; 5271 5272 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5273 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, 5274 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, 5275 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 5276 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; 5277 clock-names = "core_iface", 5278 "core_aux", 5279 "ctrl_link", 5280 "ctrl_link_iface", 5281 "stream_pixel"; 5282 5283 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 5284 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; 5285 assigned-clock-parents = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>, 5286 <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 5287 5288 operating-points-v2 = <&mdss_dp0_opp_table>; 5289 5290 power-domains = <&rpmhpd RPMHPD_MMCX>; 5291 5292 phys = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_PHY>; 5293 phy-names = "dp"; 5294 5295 #sound-dai-cells = <0>; 5296 5297 status = "disabled"; 5298 5299 ports { 5300 #address-cells = <1>; 5301 #size-cells = <0>; 5302 5303 port@0 { 5304 reg = <0>; 5305 5306 mdss_dp0_in: endpoint { 5307 remote-endpoint = <&mdss_intf0_out>; 5308 }; 5309 }; 5310 5311 port@1 { 5312 reg = <1>; 5313 5314 mdss_dp0_out: endpoint { 5315 remote-endpoint = <&usb_1_ss0_qmpphy_dp_in>; 5316 }; 5317 }; 5318 }; 5319 5320 mdss_dp0_opp_table: opp-table { 5321 compatible = "operating-points-v2"; 5322 5323 opp-160000000 { 5324 opp-hz = /bits/ 64 <160000000>; 5325 required-opps = <&rpmhpd_opp_low_svs>; 5326 }; 5327 5328 opp-270000000 { 5329 opp-hz = /bits/ 64 <270000000>; 5330 required-opps = <&rpmhpd_opp_svs>; 5331 }; 5332 5333 opp-540000000 { 5334 opp-hz = /bits/ 64 <540000000>; 5335 required-opps = <&rpmhpd_opp_svs_l1>; 5336 }; 5337 5338 opp-810000000 { 5339 opp-hz = /bits/ 64 <810000000>; 5340 required-opps = <&rpmhpd_opp_nom>; 5341 }; 5342 }; 5343 }; 5344 5345 mdss_dp1: displayport-controller@ae98000 { 5346 compatible = "qcom,x1e80100-dp"; 5347 reg = <0 0x0ae98000 0 0x200>, 5348 <0 0x0ae98200 0 0x200>, 5349 <0 0x0ae98400 0 0x600>, 5350 <0 0x0ae99000 0 0x400>, 5351 <0 0x0ae99400 0 0x400>; 5352 5353 interrupts-extended = <&mdss 13>; 5354 5355 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5356 <&dispcc DISP_CC_MDSS_DPTX1_AUX_CLK>, 5357 <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK>, 5358 <&dispcc DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, 5359 <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK>; 5360 clock-names = "core_iface", 5361 "core_aux", 5362 "ctrl_link", 5363 "ctrl_link_iface", 5364 "stream_pixel"; 5365 5366 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, 5367 <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>; 5368 assigned-clock-parents = <&usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 5369 <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 5370 5371 operating-points-v2 = <&mdss_dp1_opp_table>; 5372 5373 power-domains = <&rpmhpd RPMHPD_MMCX>; 5374 5375 phys = <&usb_1_ss1_qmpphy QMP_USB43DP_DP_PHY>; 5376 phy-names = "dp"; 5377 5378 #sound-dai-cells = <0>; 5379 5380 status = "disabled"; 5381 5382 ports { 5383 #address-cells = <1>; 5384 #size-cells = <0>; 5385 5386 port@0 { 5387 reg = <0>; 5388 5389 mdss_dp1_in: endpoint { 5390 remote-endpoint = <&mdss_intf4_out>; 5391 }; 5392 }; 5393 5394 port@1 { 5395 reg = <1>; 5396 5397 mdss_dp1_out: endpoint { 5398 remote-endpoint = <&usb_1_ss1_qmpphy_dp_in>; 5399 }; 5400 }; 5401 }; 5402 5403 mdss_dp1_opp_table: opp-table { 5404 compatible = "operating-points-v2"; 5405 5406 opp-160000000 { 5407 opp-hz = /bits/ 64 <160000000>; 5408 required-opps = <&rpmhpd_opp_low_svs>; 5409 }; 5410 5411 opp-270000000 { 5412 opp-hz = /bits/ 64 <270000000>; 5413 required-opps = <&rpmhpd_opp_svs>; 5414 }; 5415 5416 opp-540000000 { 5417 opp-hz = /bits/ 64 <540000000>; 5418 required-opps = <&rpmhpd_opp_svs_l1>; 5419 }; 5420 5421 opp-810000000 { 5422 opp-hz = /bits/ 64 <810000000>; 5423 required-opps = <&rpmhpd_opp_nom>; 5424 }; 5425 }; 5426 }; 5427 5428 mdss_dp2: displayport-controller@ae9a000 { 5429 compatible = "qcom,x1e80100-dp"; 5430 reg = <0 0x0ae9a000 0 0x200>, 5431 <0 0x0ae9a200 0 0x200>, 5432 <0 0x0ae9a400 0 0x600>, 5433 <0 0x0ae9b000 0 0x400>, 5434 <0 0x0ae9b400 0 0x400>; 5435 5436 interrupts-extended = <&mdss 14>; 5437 5438 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5439 <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>, 5440 <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK>, 5441 <&dispcc DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, 5442 <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK>; 5443 clock-names = "core_iface", 5444 "core_aux", 5445 "ctrl_link", 5446 "ctrl_link_iface", 5447 "stream_pixel"; 5448 5449 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, 5450 <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>; 5451 assigned-clock-parents = <&usb_1_ss2_qmpphy QMP_USB43DP_DP_LINK_CLK>, 5452 <&usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 5453 5454 operating-points-v2 = <&mdss_dp2_opp_table>; 5455 5456 power-domains = <&rpmhpd RPMHPD_MMCX>; 5457 5458 phys = <&usb_1_ss2_qmpphy QMP_USB43DP_DP_PHY>; 5459 phy-names = "dp"; 5460 5461 #sound-dai-cells = <0>; 5462 5463 status = "disabled"; 5464 5465 ports { 5466 #address-cells = <1>; 5467 #size-cells = <0>; 5468 5469 port@0 { 5470 reg = <0>; 5471 mdss_dp2_in: endpoint { 5472 remote-endpoint = <&mdss_intf6_out>; 5473 }; 5474 }; 5475 5476 port@1 { 5477 reg = <1>; 5478 5479 mdss_dp2_out: endpoint { 5480 remote-endpoint = <&usb_1_ss2_qmpphy_dp_in>; 5481 }; 5482 }; 5483 }; 5484 5485 mdss_dp2_opp_table: opp-table { 5486 compatible = "operating-points-v2"; 5487 5488 opp-160000000 { 5489 opp-hz = /bits/ 64 <160000000>; 5490 required-opps = <&rpmhpd_opp_low_svs>; 5491 }; 5492 5493 opp-270000000 { 5494 opp-hz = /bits/ 64 <270000000>; 5495 required-opps = <&rpmhpd_opp_svs>; 5496 }; 5497 5498 opp-540000000 { 5499 opp-hz = /bits/ 64 <540000000>; 5500 required-opps = <&rpmhpd_opp_svs_l1>; 5501 }; 5502 5503 opp-810000000 { 5504 opp-hz = /bits/ 64 <810000000>; 5505 required-opps = <&rpmhpd_opp_nom>; 5506 }; 5507 }; 5508 }; 5509 5510 mdss_dp3: displayport-controller@aea0000 { 5511 compatible = "qcom,x1e80100-dp"; 5512 reg = <0 0x0aea0000 0 0x200>, 5513 <0 0x0aea0200 0 0x200>, 5514 <0 0x0aea0400 0 0x600>, 5515 <0 0x0aea1000 0 0x400>, 5516 <0 0x0aea1400 0 0x400>; 5517 5518 interrupts-extended = <&mdss 15>; 5519 5520 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5521 <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>, 5522 <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK>, 5523 <&dispcc DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>, 5524 <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK>; 5525 clock-names = "core_iface", 5526 "core_aux", 5527 "ctrl_link", 5528 "ctrl_link_iface", 5529 "stream_pixel"; 5530 5531 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>, 5532 <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>; 5533 assigned-clock-parents = <&mdss_dp3_phy 0>, 5534 <&mdss_dp3_phy 1>; 5535 5536 operating-points-v2 = <&mdss_dp3_opp_table>; 5537 5538 power-domains = <&rpmhpd RPMHPD_MMCX>; 5539 5540 phys = <&mdss_dp3_phy>; 5541 phy-names = "dp"; 5542 5543 #sound-dai-cells = <0>; 5544 5545 status = "disabled"; 5546 5547 ports { 5548 #address-cells = <1>; 5549 #size-cells = <0>; 5550 5551 port@0 { 5552 reg = <0>; 5553 5554 mdss_dp3_in: endpoint { 5555 remote-endpoint = <&mdss_intf5_out>; 5556 }; 5557 }; 5558 5559 port@1 { 5560 reg = <1>; 5561 }; 5562 }; 5563 5564 mdss_dp3_opp_table: opp-table { 5565 compatible = "operating-points-v2"; 5566 5567 opp-160000000 { 5568 opp-hz = /bits/ 64 <160000000>; 5569 required-opps = <&rpmhpd_opp_low_svs>; 5570 }; 5571 5572 opp-270000000 { 5573 opp-hz = /bits/ 64 <270000000>; 5574 required-opps = <&rpmhpd_opp_svs>; 5575 }; 5576 5577 opp-540000000 { 5578 opp-hz = /bits/ 64 <540000000>; 5579 required-opps = <&rpmhpd_opp_svs_l1>; 5580 }; 5581 5582 opp-810000000 { 5583 opp-hz = /bits/ 64 <810000000>; 5584 required-opps = <&rpmhpd_opp_nom>; 5585 }; 5586 }; 5587 }; 5588 5589 }; 5590 5591 mdss_dp2_phy: phy@aec2a00 { 5592 compatible = "qcom,x1e80100-dp-phy"; 5593 reg = <0 0x0aec2a00 0 0x19c>, 5594 <0 0x0aec2200 0 0xec>, 5595 <0 0x0aec2600 0 0xec>, 5596 <0 0x0aec2000 0 0x1c8>; 5597 5598 clocks = <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>, 5599 <&dispcc DISP_CC_MDSS_AHB_CLK>; 5600 clock-names = "aux", 5601 "cfg_ahb"; 5602 5603 power-domains = <&rpmhpd RPMHPD_MX>; 5604 5605 #clock-cells = <1>; 5606 #phy-cells = <0>; 5607 5608 status = "disabled"; 5609 }; 5610 5611 mdss_dp3_phy: phy@aec5a00 { 5612 compatible = "qcom,x1e80100-dp-phy"; 5613 reg = <0 0x0aec5a00 0 0x19c>, 5614 <0 0x0aec5200 0 0xec>, 5615 <0 0x0aec5600 0 0xec>, 5616 <0 0x0aec5000 0 0x1c8>; 5617 5618 clocks = <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>, 5619 <&dispcc DISP_CC_MDSS_AHB_CLK>; 5620 clock-names = "aux", 5621 "cfg_ahb"; 5622 5623 power-domains = <&rpmhpd RPMHPD_MX>; 5624 5625 #clock-cells = <1>; 5626 #phy-cells = <0>; 5627 5628 status = "disabled"; 5629 }; 5630 5631 dispcc: clock-controller@af00000 { 5632 compatible = "qcom,x1e80100-dispcc"; 5633 reg = <0 0x0af00000 0 0x20000>; 5634 clocks = <&bi_tcxo_div2>, 5635 <&bi_tcxo_ao_div2>, 5636 <&gcc GCC_DISP_AHB_CLK>, 5637 <&sleep_clk>, 5638 <0>, /* dsi0 */ 5639 <0>, 5640 <0>, /* dsi1 */ 5641 <0>, 5642 <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp0 */ 5643 <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 5644 <&usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp1 */ 5645 <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 5646 <&usb_1_ss2_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp2 */ 5647 <&usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 5648 <&mdss_dp3_phy 0>, /* dp3 */ 5649 <&mdss_dp3_phy 1>; 5650 power-domains = <&rpmhpd RPMHPD_MMCX>; 5651 required-opps = <&rpmhpd_opp_low_svs>; 5652 #clock-cells = <1>; 5653 #reset-cells = <1>; 5654 #power-domain-cells = <1>; 5655 }; 5656 5657 pdc: interrupt-controller@b220000 { 5658 compatible = "qcom,x1e80100-pdc", "qcom,pdc"; 5659 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; 5660 5661 qcom,pdc-ranges = <0 480 42>, <42 251 5>, 5662 <47 522 52>, <99 609 32>, 5663 <131 717 12>, <143 816 19>; 5664 #interrupt-cells = <2>; 5665 interrupt-parent = <&intc>; 5666 interrupt-controller; 5667 }; 5668 5669 aoss_qmp: power-management@c300000 { 5670 compatible = "qcom,x1e80100-aoss-qmp", "qcom,aoss-qmp"; 5671 reg = <0 0x0c300000 0 0x400>; 5672 interrupt-parent = <&ipcc>; 5673 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 5674 IRQ_TYPE_EDGE_RISING>; 5675 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 5676 5677 #clock-cells = <0>; 5678 }; 5679 5680 sram@c3f0000 { 5681 compatible = "qcom,rpmh-stats"; 5682 reg = <0 0x0c3f0000 0 0x400>; 5683 }; 5684 5685 spmi: arbiter@c400000 { 5686 compatible = "qcom,x1e80100-spmi-pmic-arb"; 5687 reg = <0 0x0c400000 0 0x3000>, 5688 <0 0x0c500000 0 0x400000>, 5689 <0 0x0c440000 0 0x80000>; 5690 reg-names = "core", "chnls", "obsrvr"; 5691 5692 qcom,ee = <0>; 5693 qcom,channel = <0>; 5694 5695 #address-cells = <2>; 5696 #size-cells = <2>; 5697 ranges; 5698 5699 spmi_bus0: spmi@c42d000 { 5700 reg = <0 0x0c42d000 0 0x4000>, 5701 <0 0x0c4c0000 0 0x10000>; 5702 reg-names = "cnfg", "intr"; 5703 5704 interrupt-names = "periph_irq"; 5705 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 5706 interrupt-controller; 5707 #interrupt-cells = <4>; 5708 5709 #address-cells = <2>; 5710 #size-cells = <0>; 5711 }; 5712 5713 spmi_bus1: spmi@c432000 { 5714 reg = <0 0x0c432000 0 0x4000>, 5715 <0 0x0c4d0000 0 0x10000>; 5716 reg-names = "cnfg", "intr"; 5717 5718 interrupt-names = "periph_irq"; 5719 interrupts-extended = <&pdc 3 IRQ_TYPE_LEVEL_HIGH>; 5720 interrupt-controller; 5721 #interrupt-cells = <4>; 5722 5723 #address-cells = <2>; 5724 #size-cells = <0>; 5725 }; 5726 }; 5727 5728 tlmm: pinctrl@f100000 { 5729 compatible = "qcom,x1e80100-tlmm"; 5730 reg = <0 0x0f100000 0 0xf00000>; 5731 5732 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 5733 5734 gpio-controller; 5735 #gpio-cells = <2>; 5736 5737 interrupt-controller; 5738 #interrupt-cells = <2>; 5739 5740 gpio-ranges = <&tlmm 0 0 239>; 5741 wakeup-parent = <&pdc>; 5742 5743 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 5744 /* SDA, SCL */ 5745 pins = "gpio0", "gpio1"; 5746 function = "qup0_se0"; 5747 drive-strength = <2>; 5748 bias-pull-up = <2200>; 5749 }; 5750 5751 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 5752 /* SDA, SCL */ 5753 pins = "gpio4", "gpio5"; 5754 function = "qup0_se1"; 5755 drive-strength = <2>; 5756 bias-pull-up = <2200>; 5757 }; 5758 5759 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 5760 /* SDA, SCL */ 5761 pins = "gpio8", "gpio9"; 5762 function = "qup0_se2"; 5763 drive-strength = <2>; 5764 bias-pull-up = <2200>; 5765 }; 5766 5767 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 5768 /* SDA, SCL */ 5769 pins = "gpio12", "gpio13"; 5770 function = "qup0_se3"; 5771 drive-strength = <2>; 5772 bias-pull-up = <2200>; 5773 }; 5774 5775 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 5776 /* SDA, SCL */ 5777 pins = "gpio16", "gpio17"; 5778 function = "qup0_se4"; 5779 drive-strength = <2>; 5780 bias-pull-up = <2200>; 5781 }; 5782 5783 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 5784 /* SDA, SCL */ 5785 pins = "gpio20", "gpio21"; 5786 function = "qup0_se5"; 5787 drive-strength = <2>; 5788 bias-pull-up = <2200>; 5789 }; 5790 5791 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 5792 /* SDA, SCL */ 5793 pins = "gpio24", "gpio25"; 5794 function = "qup0_se6"; 5795 drive-strength = <2>; 5796 bias-pull-up = <2200>; 5797 }; 5798 5799 qup_i2c7_data_clk: qup-i2c7-data-clk-state { 5800 /* SDA, SCL */ 5801 pins = "gpio14", "gpio15"; 5802 function = "qup0_se7"; 5803 drive-strength = <2>; 5804 bias-pull-up = <2200>; 5805 }; 5806 5807 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 5808 /* SDA, SCL */ 5809 pins = "gpio32", "gpio33"; 5810 function = "qup1_se0"; 5811 drive-strength = <2>; 5812 bias-pull-up = <2200>; 5813 }; 5814 5815 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 5816 /* SDA, SCL */ 5817 pins = "gpio36", "gpio37"; 5818 function = "qup1_se1"; 5819 drive-strength = <2>; 5820 bias-pull-up = <2200>; 5821 }; 5822 5823 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 5824 /* SDA, SCL */ 5825 pins = "gpio40", "gpio41"; 5826 function = "qup1_se2"; 5827 drive-strength = <2>; 5828 bias-pull-up = <2200>; 5829 }; 5830 5831 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 5832 /* SDA, SCL */ 5833 pins = "gpio44", "gpio45"; 5834 function = "qup1_se3"; 5835 drive-strength = <2>; 5836 bias-pull-up = <2200>; 5837 }; 5838 5839 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 5840 /* SDA, SCL */ 5841 pins = "gpio48", "gpio49"; 5842 function = "qup1_se4"; 5843 drive-strength = <2>; 5844 bias-pull-up = <2200>; 5845 }; 5846 5847 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 5848 /* SDA, SCL */ 5849 pins = "gpio52", "gpio53"; 5850 function = "qup1_se5"; 5851 drive-strength = <2>; 5852 bias-pull-up = <2200>; 5853 }; 5854 5855 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 5856 /* SDA, SCL */ 5857 pins = "gpio56", "gpio57"; 5858 function = "qup1_se6"; 5859 drive-strength = <2>; 5860 bias-pull-up = <2200>; 5861 }; 5862 5863 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 5864 /* SDA, SCL */ 5865 pins = "gpio54", "gpio55"; 5866 function = "qup1_se7"; 5867 drive-strength = <2>; 5868 bias-pull-up = <2200>; 5869 }; 5870 5871 qup_i2c16_data_clk: qup-i2c16-data-clk-state { 5872 /* SDA, SCL */ 5873 pins = "gpio64", "gpio65"; 5874 function = "qup2_se0"; 5875 drive-strength = <2>; 5876 bias-pull-up = <2200>; 5877 }; 5878 5879 qup_i2c17_data_clk: qup-i2c17-data-clk-state { 5880 /* SDA, SCL */ 5881 pins = "gpio68", "gpio69"; 5882 function = "qup2_se1"; 5883 drive-strength = <2>; 5884 bias-pull-up = <2200>; 5885 }; 5886 5887 qup_i2c18_data_clk: qup-i2c18-data-clk-state { 5888 /* SDA, SCL */ 5889 pins = "gpio72", "gpio73"; 5890 function = "qup2_se2"; 5891 drive-strength = <2>; 5892 bias-pull-up = <2200>; 5893 }; 5894 5895 qup_i2c19_data_clk: qup-i2c19-data-clk-state { 5896 /* SDA, SCL */ 5897 pins = "gpio76", "gpio77"; 5898 function = "qup2_se3"; 5899 drive-strength = <2>; 5900 bias-pull-up = <2200>; 5901 }; 5902 5903 qup_i2c20_data_clk: qup-i2c20-data-clk-state { 5904 /* SDA, SCL */ 5905 pins = "gpio80", "gpio81"; 5906 function = "qup2_se4"; 5907 drive-strength = <2>; 5908 bias-pull-up = <2200>; 5909 }; 5910 5911 qup_i2c21_data_clk: qup-i2c21-data-clk-state { 5912 /* SDA, SCL */ 5913 pins = "gpio84", "gpio85"; 5914 function = "qup2_se5"; 5915 drive-strength = <2>; 5916 bias-pull-up = <2200>; 5917 }; 5918 5919 qup_i2c22_data_clk: qup-i2c22-data-clk-state { 5920 /* SDA, SCL */ 5921 pins = "gpio88", "gpio89"; 5922 function = "qup2_se6"; 5923 drive-strength = <2>; 5924 bias-pull-up = <2200>; 5925 }; 5926 5927 qup_i2c23_data_clk: qup-i2c23-data-clk-state { 5928 /* SDA, SCL */ 5929 pins = "gpio86", "gpio87"; 5930 function = "qup2_se7"; 5931 drive-strength = <2>; 5932 bias-pull-up = <2200>; 5933 }; 5934 5935 qup_spi0_cs: qup-spi0-cs-state { 5936 pins = "gpio3"; 5937 function = "qup0_se0"; 5938 drive-strength = <6>; 5939 bias-disable; 5940 }; 5941 5942 qup_spi0_data_clk: qup-spi0-data-clk-state { 5943 /* MISO, MOSI, CLK */ 5944 pins = "gpio0", "gpio1", "gpio2"; 5945 function = "qup0_se0"; 5946 drive-strength = <6>; 5947 bias-disable; 5948 }; 5949 5950 qup_spi1_cs: qup-spi1-cs-state { 5951 pins = "gpio7"; 5952 function = "qup0_se1"; 5953 drive-strength = <6>; 5954 bias-disable; 5955 }; 5956 5957 qup_spi1_data_clk: qup-spi1-data-clk-state { 5958 /* MISO, MOSI, CLK */ 5959 pins = "gpio4", "gpio5", "gpio6"; 5960 function = "qup0_se1"; 5961 drive-strength = <6>; 5962 bias-disable; 5963 }; 5964 5965 qup_spi2_cs: qup-spi2-cs-state { 5966 pins = "gpio11"; 5967 function = "qup0_se2"; 5968 drive-strength = <6>; 5969 bias-disable; 5970 }; 5971 5972 qup_spi2_data_clk: qup-spi2-data-clk-state { 5973 /* MISO, MOSI, CLK */ 5974 pins = "gpio8", "gpio9", "gpio10"; 5975 function = "qup0_se2"; 5976 drive-strength = <6>; 5977 bias-disable; 5978 }; 5979 5980 qup_spi3_cs: qup-spi3-cs-state { 5981 pins = "gpio15"; 5982 function = "qup0_se3"; 5983 drive-strength = <6>; 5984 bias-disable; 5985 }; 5986 5987 qup_spi3_data_clk: qup-spi3-data-clk-state { 5988 /* MISO, MOSI, CLK */ 5989 pins = "gpio12", "gpio13", "gpio14"; 5990 function = "qup0_se3"; 5991 drive-strength = <6>; 5992 bias-disable; 5993 }; 5994 5995 qup_spi4_cs: qup-spi4-cs-state { 5996 pins = "gpio19"; 5997 function = "qup0_se4"; 5998 drive-strength = <6>; 5999 bias-disable; 6000 }; 6001 6002 qup_spi4_data_clk: qup-spi4-data-clk-state { 6003 /* MISO, MOSI, CLK */ 6004 pins = "gpio16", "gpio17", "gpio18"; 6005 function = "qup0_se4"; 6006 drive-strength = <6>; 6007 bias-disable; 6008 }; 6009 6010 qup_spi5_cs: qup-spi5-cs-state { 6011 pins = "gpio23"; 6012 function = "qup0_se5"; 6013 drive-strength = <6>; 6014 bias-disable; 6015 }; 6016 6017 qup_spi5_data_clk: qup-spi5-data-clk-state { 6018 /* MISO, MOSI, CLK */ 6019 pins = "gpio20", "gpio21", "gpio22"; 6020 function = "qup0_se5"; 6021 drive-strength = <6>; 6022 bias-disable; 6023 }; 6024 6025 qup_spi6_cs: qup-spi6-cs-state { 6026 pins = "gpio27"; 6027 function = "qup0_se6"; 6028 drive-strength = <6>; 6029 bias-disable; 6030 }; 6031 6032 qup_spi6_data_clk: qup-spi6-data-clk-state { 6033 /* MISO, MOSI, CLK */ 6034 pins = "gpio24", "gpio25", "gpio26"; 6035 function = "qup0_se6"; 6036 drive-strength = <6>; 6037 bias-disable; 6038 }; 6039 6040 qup_spi7_cs: qup-spi7-cs-state { 6041 pins = "gpio13"; 6042 function = "qup0_se7"; 6043 drive-strength = <6>; 6044 bias-disable; 6045 }; 6046 6047 qup_spi7_data_clk: qup-spi7-data-clk-state { 6048 /* MISO, MOSI, CLK */ 6049 pins = "gpio14", "gpio15", "gpio12"; 6050 function = "qup0_se7"; 6051 drive-strength = <6>; 6052 bias-disable; 6053 }; 6054 6055 qup_spi8_cs: qup-spi8-cs-state { 6056 pins = "gpio35"; 6057 function = "qup1_se0"; 6058 drive-strength = <6>; 6059 bias-disable; 6060 }; 6061 6062 qup_spi8_data_clk: qup-spi8-data-clk-state { 6063 /* MISO, MOSI, CLK */ 6064 pins = "gpio32", "gpio33", "gpio34"; 6065 function = "qup1_se0"; 6066 drive-strength = <6>; 6067 bias-disable; 6068 }; 6069 6070 qup_spi9_cs: qup-spi9-cs-state { 6071 pins = "gpio39"; 6072 function = "qup1_se1"; 6073 drive-strength = <6>; 6074 bias-disable; 6075 }; 6076 6077 qup_spi9_data_clk: qup-spi9-data-clk-state { 6078 /* MISO, MOSI, CLK */ 6079 pins = "gpio36", "gpio37", "gpio38"; 6080 function = "qup1_se1"; 6081 drive-strength = <6>; 6082 bias-disable; 6083 }; 6084 6085 qup_spi10_cs: qup-spi10-cs-state { 6086 pins = "gpio43"; 6087 function = "qup1_se2"; 6088 drive-strength = <6>; 6089 bias-disable; 6090 }; 6091 6092 qup_spi10_data_clk: qup-spi10-data-clk-state { 6093 /* MISO, MOSI, CLK */ 6094 pins = "gpio40", "gpio41", "gpio42"; 6095 function = "qup1_se2"; 6096 drive-strength = <6>; 6097 bias-disable; 6098 }; 6099 6100 qup_spi11_cs: qup-spi11-cs-state { 6101 pins = "gpio47"; 6102 function = "qup1_se3"; 6103 drive-strength = <6>; 6104 bias-disable; 6105 }; 6106 6107 qup_spi11_data_clk: qup-spi11-data-clk-state { 6108 /* MISO, MOSI, CLK */ 6109 pins = "gpio44", "gpio45", "gpio46"; 6110 function = "qup1_se3"; 6111 drive-strength = <6>; 6112 bias-disable; 6113 }; 6114 6115 qup_spi12_cs: qup-spi12-cs-state { 6116 pins = "gpio51"; 6117 function = "qup1_se4"; 6118 drive-strength = <6>; 6119 bias-disable; 6120 }; 6121 6122 qup_spi12_data_clk: qup-spi12-data-clk-state { 6123 /* MISO, MOSI, CLK */ 6124 pins = "gpio48", "gpio49", "gpio50"; 6125 function = "qup1_se4"; 6126 drive-strength = <6>; 6127 bias-disable; 6128 }; 6129 6130 qup_spi13_cs: qup-spi13-cs-state { 6131 pins = "gpio55"; 6132 function = "qup1_se5"; 6133 drive-strength = <6>; 6134 bias-disable; 6135 }; 6136 6137 qup_spi13_data_clk: qup-spi13-data-clk-state { 6138 /* MISO, MOSI, CLK */ 6139 pins = "gpio52", "gpio53", "gpio54"; 6140 function = "qup1_se5"; 6141 drive-strength = <6>; 6142 bias-disable; 6143 }; 6144 6145 qup_spi14_cs: qup-spi14-cs-state { 6146 pins = "gpio59"; 6147 function = "qup1_se6"; 6148 drive-strength = <6>; 6149 bias-disable; 6150 }; 6151 6152 qup_spi14_data_clk: qup-spi14-data-clk-state { 6153 /* MISO, MOSI, CLK */ 6154 pins = "gpio56", "gpio57", "gpio58"; 6155 function = "qup1_se6"; 6156 drive-strength = <6>; 6157 bias-disable; 6158 }; 6159 6160 qup_spi15_cs: qup-spi15-cs-state { 6161 pins = "gpio53"; 6162 function = "qup1_se7"; 6163 drive-strength = <6>; 6164 bias-disable; 6165 }; 6166 6167 qup_spi15_data_clk: qup-spi15-data-clk-state { 6168 /* MISO, MOSI, CLK */ 6169 pins = "gpio54", "gpio55", "gpio52"; 6170 function = "qup1_se7"; 6171 drive-strength = <6>; 6172 bias-disable; 6173 }; 6174 6175 qup_spi16_cs: qup-spi16-cs-state { 6176 pins = "gpio67"; 6177 function = "qup2_se0"; 6178 drive-strength = <6>; 6179 bias-disable; 6180 }; 6181 6182 qup_spi16_data_clk: qup-spi16-data-clk-state { 6183 /* MISO, MOSI, CLK */ 6184 pins = "gpio64", "gpio65", "gpio66"; 6185 function = "qup2_se0"; 6186 drive-strength = <6>; 6187 bias-disable; 6188 }; 6189 6190 qup_spi17_cs: qup-spi17-cs-state { 6191 pins = "gpio71"; 6192 function = "qup2_se1"; 6193 drive-strength = <6>; 6194 bias-disable; 6195 }; 6196 6197 qup_spi17_data_clk: qup-spi17-data-clk-state { 6198 /* MISO, MOSI, CLK */ 6199 pins = "gpio68", "gpio69", "gpio70"; 6200 function = "qup2_se1"; 6201 drive-strength = <6>; 6202 bias-disable; 6203 }; 6204 6205 qup_spi18_cs: qup-spi18-cs-state { 6206 pins = "gpio75"; 6207 function = "qup2_se2"; 6208 drive-strength = <6>; 6209 bias-disable; 6210 }; 6211 6212 qup_spi18_data_clk: qup-spi18-data-clk-state { 6213 /* MISO, MOSI, CLK */ 6214 pins = "gpio72", "gpio73", "gpio74"; 6215 function = "qup2_se2"; 6216 drive-strength = <6>; 6217 bias-disable; 6218 }; 6219 6220 qup_spi19_cs: qup-spi19-cs-state { 6221 pins = "gpio79"; 6222 function = "qup2_se3"; 6223 drive-strength = <6>; 6224 bias-disable; 6225 }; 6226 6227 qup_spi19_data_clk: qup-spi19-data-clk-state { 6228 /* MISO, MOSI, CLK */ 6229 pins = "gpio76", "gpio77", "gpio78"; 6230 function = "qup2_se3"; 6231 drive-strength = <6>; 6232 bias-disable; 6233 }; 6234 6235 qup_spi20_cs: qup-spi20-cs-state { 6236 pins = "gpio83"; 6237 function = "qup2_se4"; 6238 drive-strength = <6>; 6239 bias-disable; 6240 }; 6241 6242 qup_spi20_data_clk: qup-spi20-data-clk-state { 6243 /* MISO, MOSI, CLK */ 6244 pins = "gpio80", "gpio81", "gpio82"; 6245 function = "qup2_se4"; 6246 drive-strength = <6>; 6247 bias-disable; 6248 }; 6249 6250 qup_spi21_cs: qup-spi21-cs-state { 6251 pins = "gpio87"; 6252 function = "qup2_se5"; 6253 drive-strength = <6>; 6254 bias-disable; 6255 }; 6256 6257 qup_spi21_data_clk: qup-spi21-data-clk-state { 6258 /* MISO, MOSI, CLK */ 6259 pins = "gpio84", "gpio85", "gpio86"; 6260 function = "qup2_se5"; 6261 drive-strength = <6>; 6262 bias-disable; 6263 }; 6264 6265 qup_spi22_cs: qup-spi22-cs-state { 6266 pins = "gpio91"; 6267 function = "qup2_se6"; 6268 drive-strength = <6>; 6269 bias-disable; 6270 }; 6271 6272 qup_spi22_data_clk: qup-spi22-data-clk-state { 6273 /* MISO, MOSI, CLK */ 6274 pins = "gpio88", "gpio89", "gpio90"; 6275 function = "qup2_se6"; 6276 drive-strength = <6>; 6277 bias-disable; 6278 }; 6279 6280 qup_spi23_cs: qup-spi23-cs-state { 6281 pins = "gpio85"; 6282 function = "qup2_se7"; 6283 drive-strength = <6>; 6284 bias-disable; 6285 }; 6286 6287 qup_spi23_data_clk: qup-spi23-data-clk-state { 6288 /* MISO, MOSI, CLK */ 6289 pins = "gpio86", "gpio87", "gpio84"; 6290 function = "qup2_se7"; 6291 drive-strength = <6>; 6292 bias-disable; 6293 }; 6294 6295 qup_uart2_default: qup-uart2-default-state { 6296 cts-pins { 6297 pins = "gpio8"; 6298 function = "qup0_se2"; 6299 drive-strength = <2>; 6300 bias-disable; 6301 }; 6302 6303 rts-pins { 6304 pins = "gpio9"; 6305 function = "qup0_se2"; 6306 drive-strength = <2>; 6307 bias-disable; 6308 }; 6309 6310 tx-pins { 6311 pins = "gpio10"; 6312 function = "qup0_se2"; 6313 drive-strength = <2>; 6314 bias-disable; 6315 }; 6316 6317 rx-pins { 6318 pins = "gpio11"; 6319 function = "qup0_se2"; 6320 drive-strength = <2>; 6321 bias-disable; 6322 }; 6323 }; 6324 6325 qup_uart14_default: qup-uart14-default-state { 6326 cts-pins { 6327 pins = "gpio56"; 6328 function = "qup1_se6"; 6329 bias-bus-hold; 6330 }; 6331 6332 rts-pins { 6333 pins = "gpio57"; 6334 function = "qup1_se6"; 6335 drive-strength = <2>; 6336 bias-disable; 6337 }; 6338 6339 tx-pins { 6340 pins = "gpio58"; 6341 function = "qup1_se6"; 6342 drive-strength = <2>; 6343 bias-disable; 6344 }; 6345 6346 rx-pins { 6347 pins = "gpio59"; 6348 function = "qup1_se6"; 6349 bias-pull-up; 6350 }; 6351 }; 6352 6353 qup_uart21_default: qup-uart21-default-state { 6354 tx-pins { 6355 pins = "gpio86"; 6356 function = "qup2_se5"; 6357 drive-strength = <2>; 6358 bias-disable; 6359 }; 6360 6361 rx-pins { 6362 pins = "gpio87"; 6363 function = "qup2_se5"; 6364 drive-strength = <2>; 6365 bias-disable; 6366 }; 6367 }; 6368 6369 sdc2_default: sdc2-default-state { 6370 clk-pins { 6371 pins = "sdc2_clk"; 6372 drive-strength = <16>; 6373 bias-disable; 6374 }; 6375 6376 cmd-pins { 6377 pins = "sdc2_cmd"; 6378 drive-strength = <10>; 6379 bias-pull-up; 6380 }; 6381 6382 data-pins { 6383 pins = "sdc2_data"; 6384 drive-strength = <10>; 6385 bias-pull-up; 6386 }; 6387 }; 6388 6389 sdc2_sleep: sdc2-sleep-state { 6390 clk-pins { 6391 pins = "sdc2_clk"; 6392 drive-strength = <2>; 6393 bias-disable; 6394 }; 6395 6396 cmd-pins { 6397 pins = "sdc2_cmd"; 6398 drive-strength = <2>; 6399 bias-pull-up; 6400 }; 6401 6402 data-pins { 6403 pins = "sdc2_data"; 6404 drive-strength = <2>; 6405 bias-pull-up; 6406 }; 6407 }; 6408 }; 6409 6410 stm@10002000 { 6411 compatible = "arm,coresight-stm", "arm,primecell"; 6412 reg = <0x0 0x10002000 0x0 0x1000>, 6413 <0x0 0x16280000 0x0 0x180000>; 6414 reg-names = "stm-base", 6415 "stm-stimulus-base"; 6416 6417 clocks = <&aoss_qmp>; 6418 clock-names = "apb_pclk"; 6419 6420 out-ports { 6421 port { 6422 stm_out: endpoint { 6423 remote-endpoint = <&funnel0_in7>; 6424 }; 6425 }; 6426 }; 6427 }; 6428 6429 tpdm@10003000 { 6430 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6431 reg = <0x0 0x10003000 0x0 0x1000>; 6432 6433 clocks = <&aoss_qmp>; 6434 clock-names = "apb_pclk"; 6435 6436 qcom,cmb-element-bits = <32>; 6437 qcom,cmb-msrs-num = <32>; 6438 status = "disabled"; 6439 6440 out-ports { 6441 port { 6442 dcc_tpdm_out: endpoint { 6443 remote-endpoint = <&qdss_tpda_in0>; 6444 }; 6445 }; 6446 }; 6447 }; 6448 6449 tpda@10004000 { 6450 compatible = "qcom,coresight-tpda", "arm,primecell"; 6451 reg = <0x0 0x10004000 0x0 0x1000>; 6452 6453 clocks = <&aoss_qmp>; 6454 clock-names = "apb_pclk"; 6455 6456 in-ports { 6457 #address-cells = <1>; 6458 #size-cells = <0>; 6459 6460 port@0 { 6461 reg = <0>; 6462 6463 qdss_tpda_in0: endpoint { 6464 remote-endpoint = <&dcc_tpdm_out>; 6465 }; 6466 }; 6467 6468 port@1 { 6469 reg = <1>; 6470 6471 qdss_tpda_in1: endpoint { 6472 remote-endpoint = <&qdss_tpdm_out>; 6473 }; 6474 }; 6475 }; 6476 6477 out-ports { 6478 port { 6479 qdss_tpda_out: endpoint { 6480 remote-endpoint = <&funnel0_in6>; 6481 }; 6482 }; 6483 }; 6484 }; 6485 6486 tpdm@1000f000 { 6487 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6488 reg = <0x0 0x1000f000 0x0 0x1000>; 6489 6490 clocks = <&aoss_qmp>; 6491 clock-names = "apb_pclk"; 6492 6493 qcom,cmb-element-bits = <32>; 6494 qcom,cmb-msrs-num = <32>; 6495 6496 out-ports { 6497 port { 6498 qdss_tpdm_out: endpoint { 6499 remote-endpoint = <&qdss_tpda_in1>; 6500 }; 6501 }; 6502 }; 6503 }; 6504 6505 funnel@10041000 { 6506 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 6507 reg = <0x0 0x10041000 0x0 0x1000>; 6508 6509 clocks = <&aoss_qmp>; 6510 clock-names = "apb_pclk"; 6511 6512 in-ports { 6513 #address-cells = <1>; 6514 #size-cells = <0>; 6515 6516 port@6 { 6517 reg = <6>; 6518 6519 funnel0_in6: endpoint { 6520 remote-endpoint = <&qdss_tpda_out>; 6521 }; 6522 }; 6523 6524 port@7 { 6525 reg = <7>; 6526 6527 funnel0_in7: endpoint { 6528 remote-endpoint = <&stm_out>; 6529 }; 6530 }; 6531 }; 6532 6533 out-ports { 6534 port { 6535 funnel0_out: endpoint { 6536 remote-endpoint = <&qdss_funnel_in0>; 6537 }; 6538 }; 6539 }; 6540 }; 6541 6542 funnel@10042000 { 6543 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 6544 reg = <0x0 0x10042000 0x0 0x1000>; 6545 6546 clocks = <&aoss_qmp>; 6547 clock-names = "apb_pclk"; 6548 6549 in-ports { 6550 #address-cells = <1>; 6551 #size-cells = <0>; 6552 6553 port@2 { 6554 reg = <2>; 6555 6556 funnel1_in2: endpoint { 6557 remote-endpoint = <&tmess_funnel_out>; 6558 }; 6559 }; 6560 6561 port@5 { 6562 reg = <5>; 6563 6564 funnel1_in5: endpoint { 6565 remote-endpoint = <&dlst_funnel_out>; 6566 }; 6567 }; 6568 6569 port@6 { 6570 reg = <6>; 6571 6572 funnel1_in6: endpoint { 6573 remote-endpoint = <&dlct1_funnel_out>; 6574 }; 6575 }; 6576 }; 6577 6578 out-ports { 6579 port { 6580 funnel1_out: endpoint { 6581 remote-endpoint = <&qdss_funnel_in1>; 6582 }; 6583 }; 6584 }; 6585 }; 6586 6587 funnel@10045000 { 6588 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 6589 reg = <0x0 0x10045000 0x0 0x1000>; 6590 6591 clocks = <&aoss_qmp>; 6592 clock-names = "apb_pclk"; 6593 6594 in-ports { 6595 #address-cells = <1>; 6596 #size-cells = <0>; 6597 6598 port@0 { 6599 reg = <0>; 6600 6601 qdss_funnel_in0: endpoint { 6602 remote-endpoint = <&funnel0_out>; 6603 }; 6604 }; 6605 6606 port@1 { 6607 reg = <1>; 6608 6609 qdss_funnel_in1: endpoint { 6610 remote-endpoint = <&funnel1_out>; 6611 }; 6612 }; 6613 }; 6614 6615 out-ports { 6616 port { 6617 qdss_funnel_out: endpoint { 6618 remote-endpoint = <&aoss_funnel_in7>; 6619 }; 6620 }; 6621 }; 6622 }; 6623 6624 tpdm@10800000 { 6625 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6626 reg = <0x0 0x10800000 0x0 0x1000>; 6627 6628 clocks = <&aoss_qmp>; 6629 clock-names = "apb_pclk"; 6630 6631 qcom,cmb-element-bits = <64>; 6632 qcom,cmb-msrs-num = <32>; 6633 6634 out-ports { 6635 port { 6636 mxa_tpdm_out: endpoint { 6637 remote-endpoint = <&dlct2_tpda_in15>; 6638 }; 6639 }; 6640 }; 6641 }; 6642 6643 tpdm@1082c000 { 6644 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6645 reg = <0x0 0x1082c000 0x0 0x1000>; 6646 6647 clocks = <&aoss_qmp>; 6648 clock-names = "apb_pclk"; 6649 6650 qcom,dsb-element-bits = <32>; 6651 qcom,dsb-msrs-num = <32>; 6652 6653 out-ports { 6654 port { 6655 gcc_tpdm_out: endpoint { 6656 remote-endpoint = <&dlct1_tpda_in21>; 6657 }; 6658 }; 6659 }; 6660 }; 6661 6662 tpdm@10841000 { 6663 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6664 reg = <0x0 0x10841000 0x0 0x1000>; 6665 6666 clocks = <&aoss_qmp>; 6667 clock-names = "apb_pclk"; 6668 6669 qcom,cmb-element-bits = <32>; 6670 qcom,cmb-msrs-num = <32>; 6671 6672 out-ports { 6673 port { 6674 prng_tpdm_out: endpoint { 6675 remote-endpoint = <&dlct1_tpda_in19>; 6676 }; 6677 }; 6678 }; 6679 }; 6680 6681 tpdm@10844000 { 6682 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6683 reg = <0x0 0x10844000 0x0 0x1000>; 6684 6685 clocks = <&aoss_qmp>; 6686 clock-names = "apb_pclk"; 6687 6688 qcom,dsb-element-bits = <32>; 6689 qcom,dsb-msrs-num = <32>; 6690 6691 out-ports { 6692 port { 6693 lpass_cx_tpdm_out: endpoint { 6694 remote-endpoint = <&lpass_cx_funnel_in0>; 6695 }; 6696 }; 6697 }; 6698 }; 6699 6700 funnel@10846000 { 6701 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 6702 reg = <0x0 0x10846000 0x0 0x1000>; 6703 6704 clocks = <&aoss_qmp>; 6705 clock-names = "apb_pclk"; 6706 6707 in-ports { 6708 port { 6709 lpass_cx_funnel_in0: endpoint { 6710 remote-endpoint = <&lpass_cx_tpdm_out>; 6711 }; 6712 }; 6713 }; 6714 6715 out-ports { 6716 port { 6717 lpass_cx_funnel_out: endpoint { 6718 remote-endpoint = <&dlct1_tpda_in4>; 6719 }; 6720 }; 6721 }; 6722 }; 6723 6724 cti@1098b000 { 6725 compatible = "arm,coresight-cti", "arm,primecell"; 6726 reg = <0x0 0x1098b000 0x0 0x1000>; 6727 6728 clocks = <&aoss_qmp>; 6729 clock-names = "apb_pclk"; 6730 }; 6731 6732 tpdm@109d0000 { 6733 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6734 reg = <0x0 0x109d0000 0x0 0x1000>; 6735 6736 clocks = <&aoss_qmp>; 6737 clock-names = "apb_pclk"; 6738 6739 qcom,dsb-element-bits = <32>; 6740 qcom,dsb-msrs-num = <32>; 6741 status = "disabled"; 6742 6743 out-ports { 6744 port { 6745 qm_tpdm_out: endpoint { 6746 remote-endpoint = <&dlct1_tpda_in20>; 6747 }; 6748 }; 6749 }; 6750 }; 6751 6752 tpdm@10ac0000 { 6753 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6754 reg = <0x0 0x10ac0000 0x0 0x1000>; 6755 6756 clocks = <&aoss_qmp>; 6757 clock-names = "apb_pclk"; 6758 6759 qcom,dsb-element-bits = <32>; 6760 qcom,dsb-msrs-num = <32>; 6761 status = "disabled"; 6762 6763 out-ports { 6764 port { 6765 dlst_tpdm0_out: endpoint { 6766 remote-endpoint = <&dlst_tpda_in8>; 6767 }; 6768 }; 6769 }; 6770 }; 6771 6772 tpdm@10ac1000 { 6773 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6774 reg = <0x0 0x10ac1000 0x0 0x1000>; 6775 6776 clocks = <&aoss_qmp>; 6777 clock-names = "apb_pclk"; 6778 6779 qcom,cmb-element-bits = <64>; 6780 qcom,cmb-msrs-num = <32>; 6781 6782 out-ports { 6783 port { 6784 dlst_tpdm1_out: endpoint { 6785 remote-endpoint = <&dlst_tpda_in9>; 6786 }; 6787 }; 6788 }; 6789 }; 6790 6791 tpda@10ac4000 { 6792 compatible = "qcom,coresight-tpda", "arm,primecell"; 6793 reg = <0x0 0x10ac4000 0x0 0x1000>; 6794 6795 clocks = <&aoss_qmp>; 6796 clock-names = "apb_pclk"; 6797 6798 in-ports { 6799 #address-cells = <1>; 6800 #size-cells = <0>; 6801 6802 port@8 { 6803 reg = <8>; 6804 6805 dlst_tpda_in8: endpoint { 6806 remote-endpoint = <&dlst_tpdm0_out>; 6807 }; 6808 }; 6809 6810 port@9 { 6811 reg = <9>; 6812 6813 dlst_tpda_in9: endpoint { 6814 remote-endpoint = <&dlst_tpdm1_out>; 6815 }; 6816 }; 6817 }; 6818 6819 out-ports { 6820 port { 6821 dlst_tpda_out: endpoint { 6822 remote-endpoint = <&dlst_funnel_in0>; 6823 }; 6824 }; 6825 }; 6826 }; 6827 6828 funnel@10ac5000 { 6829 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 6830 reg = <0x0 0x10ac5000 0x0 0x1000>; 6831 6832 clocks = <&aoss_qmp>; 6833 clock-names = "apb_pclk"; 6834 6835 in-ports { 6836 port { 6837 dlst_funnel_in0: endpoint { 6838 remote-endpoint = <&dlst_tpda_out>; 6839 }; 6840 }; 6841 }; 6842 6843 out-ports { 6844 port { 6845 dlst_funnel_out: endpoint { 6846 remote-endpoint = <&funnel1_in5>; 6847 }; 6848 }; 6849 }; 6850 }; 6851 6852 funnel@10b04000 { 6853 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 6854 reg = <0x0 0x10b04000 0x0 0x1000>; 6855 6856 clocks = <&aoss_qmp>; 6857 clock-names = "apb_pclk"; 6858 6859 in-ports { 6860 #address-cells = <1>; 6861 #size-cells = <0>; 6862 6863 port@3 { 6864 reg = <3>; 6865 6866 aoss_funnel_in3: endpoint { 6867 remote-endpoint = <&ddr_lpi_funnel_out>; 6868 }; 6869 }; 6870 6871 port@6 { 6872 reg = <6>; 6873 6874 aoss_funnel_in6: endpoint { 6875 remote-endpoint = <&aoss_tpda_out>; 6876 }; 6877 }; 6878 6879 port@7 { 6880 reg = <7>; 6881 6882 aoss_funnel_in7: endpoint { 6883 remote-endpoint = <&qdss_funnel_out>; 6884 }; 6885 }; 6886 }; 6887 6888 out-ports { 6889 port { 6890 aoss_funnel_out: endpoint { 6891 remote-endpoint = <&etf0_in>; 6892 }; 6893 }; 6894 }; 6895 }; 6896 6897 etf0: tmc@10b05000 { 6898 compatible = "arm,coresight-tmc", "arm,primecell"; 6899 reg = <0x0 0x10b05000 0x0 0x1000>; 6900 6901 clocks = <&aoss_qmp>; 6902 clock-names = "apb_pclk"; 6903 6904 in-ports { 6905 port { 6906 etf0_in: endpoint { 6907 remote-endpoint = <&aoss_funnel_out>; 6908 }; 6909 }; 6910 }; 6911 6912 out-ports { 6913 port { 6914 etf0_out: endpoint { 6915 remote-endpoint = <&swao_rep_in>; 6916 }; 6917 }; 6918 }; 6919 }; 6920 6921 replicator@10b06000 { 6922 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 6923 reg = <0x0 0x10b06000 0x0 0x1000>; 6924 6925 clocks = <&aoss_qmp>; 6926 clock-names = "apb_pclk"; 6927 6928 in-ports { 6929 port { 6930 swao_rep_in: endpoint { 6931 remote-endpoint = <&etf0_out>; 6932 }; 6933 }; 6934 }; 6935 6936 out-ports { 6937 port { 6938 swao_rep_out1: endpoint { 6939 remote-endpoint = <&eud_in>; 6940 }; 6941 }; 6942 }; 6943 }; 6944 6945 tpda@10b08000 { 6946 compatible = "qcom,coresight-tpda", "arm,primecell"; 6947 reg = <0x0 0x10b08000 0x0 0x1000>; 6948 6949 clocks = <&aoss_qmp>; 6950 clock-names = "apb_pclk"; 6951 6952 in-ports { 6953 #address-cells = <1>; 6954 #size-cells = <0>; 6955 6956 port@0 { 6957 reg = <0>; 6958 6959 aoss_tpda_in0: endpoint { 6960 remote-endpoint = <&aoss_tpdm0_out>; 6961 }; 6962 }; 6963 6964 port@1 { 6965 reg = <1>; 6966 6967 aoss_tpda_in1: endpoint { 6968 remote-endpoint = <&aoss_tpdm1_out>; 6969 }; 6970 }; 6971 6972 port@2 { 6973 reg = <2>; 6974 6975 aoss_tpda_in2: endpoint { 6976 remote-endpoint = <&aoss_tpdm2_out>; 6977 }; 6978 }; 6979 6980 port@3 { 6981 reg = <3>; 6982 6983 aoss_tpda_in3: endpoint { 6984 remote-endpoint = <&aoss_tpdm3_out>; 6985 }; 6986 }; 6987 6988 port@4 { 6989 reg = <4>; 6990 6991 aoss_tpda_in4: endpoint { 6992 remote-endpoint = <&aoss_tpdm4_out>; 6993 }; 6994 }; 6995 }; 6996 6997 out-ports { 6998 port { 6999 aoss_tpda_out: endpoint { 7000 remote-endpoint = <&aoss_funnel_in6>; 7001 }; 7002 }; 7003 }; 7004 }; 7005 7006 tpdm@10b09000 { 7007 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7008 reg = <0x0 0x10b09000 0x0 0x1000>; 7009 7010 clocks = <&aoss_qmp>; 7011 clock-names = "apb_pclk"; 7012 7013 qcom,cmb-element-bits = <64>; 7014 qcom,cmb-msrs-num = <32>; 7015 7016 out-ports { 7017 port { 7018 aoss_tpdm0_out: endpoint { 7019 remote-endpoint = <&aoss_tpda_in0>; 7020 }; 7021 }; 7022 }; 7023 }; 7024 7025 tpdm@10b0a000 { 7026 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7027 reg = <0x0 0x10b0a000 0x0 0x1000>; 7028 7029 clocks = <&aoss_qmp>; 7030 clock-names = "apb_pclk"; 7031 7032 qcom,cmb-element-bits = <64>; 7033 qcom,cmb-msrs-num = <32>; 7034 7035 out-ports { 7036 port { 7037 aoss_tpdm1_out: endpoint { 7038 remote-endpoint = <&aoss_tpda_in1>; 7039 }; 7040 }; 7041 }; 7042 }; 7043 7044 tpdm@10b0b000 { 7045 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7046 reg = <0x0 0x10b0b000 0x0 0x1000>; 7047 7048 clocks = <&aoss_qmp>; 7049 clock-names = "apb_pclk"; 7050 7051 qcom,cmb-element-bits = <64>; 7052 qcom,cmb-msrs-num = <32>; 7053 7054 out-ports { 7055 port { 7056 aoss_tpdm2_out: endpoint { 7057 remote-endpoint = <&aoss_tpda_in2>; 7058 }; 7059 }; 7060 }; 7061 }; 7062 7063 tpdm@10b0c000 { 7064 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7065 reg = <0x0 0x10b0c000 0x0 0x1000>; 7066 7067 clocks = <&aoss_qmp>; 7068 clock-names = "apb_pclk"; 7069 7070 qcom,cmb-element-bits = <64>; 7071 qcom,cmb-msrs-num = <32>; 7072 7073 out-ports { 7074 port { 7075 aoss_tpdm3_out: endpoint { 7076 remote-endpoint = <&aoss_tpda_in3>; 7077 }; 7078 }; 7079 }; 7080 }; 7081 7082 tpdm@10b0d000 { 7083 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7084 reg = <0x0 0x10b0d000 0x0 0x1000>; 7085 7086 clocks = <&aoss_qmp>; 7087 clock-names = "apb_pclk"; 7088 7089 qcom,dsb-element-bits = <32>; 7090 qcom,dsb-msrs-num = <32>; 7091 7092 out-ports { 7093 port { 7094 aoss_tpdm4_out: endpoint { 7095 remote-endpoint = <&aoss_tpda_in4>; 7096 }; 7097 }; 7098 }; 7099 }; 7100 7101 tpdm@10b20000 { 7102 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7103 reg = <0x0 0x10b20000 0x0 0x1000>; 7104 7105 clocks = <&aoss_qmp>; 7106 clock-names = "apb_pclk"; 7107 7108 qcom,dsb-element-bits = <32>; 7109 qcom,dsb-msrs-num = <32>; 7110 status = "disabled"; 7111 7112 out-ports { 7113 port { 7114 lpicc_tpdm_out: endpoint { 7115 remote-endpoint = <&ddr_lpi_tpda_in>; 7116 }; 7117 }; 7118 }; 7119 }; 7120 7121 tpda@10b23000 { 7122 compatible = "qcom,coresight-tpda", "arm,primecell"; 7123 reg = <0x0 0x10b23000 0x0 0x1000>; 7124 7125 clocks = <&aoss_qmp>; 7126 clock-names = "apb_pclk"; 7127 status = "disabled"; 7128 7129 in-ports { 7130 port { 7131 ddr_lpi_tpda_in: endpoint { 7132 remote-endpoint = <&lpicc_tpdm_out>; 7133 }; 7134 }; 7135 }; 7136 7137 out-ports { 7138 port { 7139 ddr_lpi_tpda_out: endpoint { 7140 remote-endpoint = <&ddr_lpi_funnel_in0>; 7141 }; 7142 }; 7143 }; 7144 }; 7145 7146 funnel@10b24000 { 7147 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 7148 reg = <0x0 0x10b24000 0x0 0x1000>; 7149 7150 clocks = <&aoss_qmp>; 7151 clock-names = "apb_pclk"; 7152 status = "disabled"; 7153 7154 in-ports { 7155 port { 7156 ddr_lpi_funnel_in0: endpoint { 7157 remote-endpoint = <&ddr_lpi_tpda_out>; 7158 }; 7159 }; 7160 }; 7161 7162 out-ports { 7163 port { 7164 ddr_lpi_funnel_out: endpoint { 7165 remote-endpoint = <&aoss_funnel_in3>; 7166 }; 7167 }; 7168 }; 7169 }; 7170 7171 tpdm@10c08000 { 7172 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7173 reg = <0x0 0x10c08000 0x0 0x1000>; 7174 7175 clocks = <&aoss_qmp>; 7176 clock-names = "apb_pclk"; 7177 7178 qcom,dsb-element-bits = <32>; 7179 qcom,dsb-msrs-num = <32>; 7180 7181 out-ports { 7182 port { 7183 mm_tpdm_out: endpoint { 7184 remote-endpoint = <&mm_funnel_in4>; 7185 }; 7186 }; 7187 }; 7188 }; 7189 7190 funnel@10c0b000 { 7191 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 7192 reg = <0x0 0x10c0b000 0x0 0x1000>; 7193 7194 clocks = <&aoss_qmp>; 7195 clock-names = "apb_pclk"; 7196 7197 in-ports { 7198 #address-cells = <1>; 7199 #size-cells = <0>; 7200 7201 port@4 { 7202 reg = <4>; 7203 7204 mm_funnel_in4: endpoint { 7205 remote-endpoint = <&mm_tpdm_out>; 7206 }; 7207 }; 7208 }; 7209 7210 out-ports { 7211 port { 7212 mm_funnel_out: endpoint { 7213 remote-endpoint = <&dlct2_tpda_in4>; 7214 }; 7215 }; 7216 }; 7217 }; 7218 7219 tpdm@10c28000 { 7220 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7221 reg = <0x0 0x10c28000 0x0 0x1000>; 7222 7223 clocks = <&aoss_qmp>; 7224 clock-names = "apb_pclk"; 7225 7226 qcom,dsb-element-bits = <32>; 7227 qcom,dsb-msrs-num = <32>; 7228 7229 out-ports { 7230 port { 7231 dlct1_tpdm_out: endpoint { 7232 remote-endpoint = <&dlct1_tpda_in26>; 7233 }; 7234 }; 7235 }; 7236 }; 7237 7238 tpdm@10c29000 { 7239 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7240 reg = <0x0 0x10c29000 0x0 0x1000>; 7241 7242 clocks = <&aoss_qmp>; 7243 clock-names = "apb_pclk"; 7244 7245 qcom,cmb-element-bits = <64>; 7246 qcom,cmb-msrs-num = <32>; 7247 7248 out-ports { 7249 port { 7250 ipcc_tpdm_out: endpoint { 7251 remote-endpoint = <&dlct1_tpda_in27>; 7252 }; 7253 }; 7254 }; 7255 }; 7256 7257 tpda@10c2b000 { 7258 compatible = "qcom,coresight-tpda", "arm,primecell"; 7259 reg = <0x0 0x10c2b000 0x0 0x1000>; 7260 7261 clocks = <&aoss_qmp>; 7262 clock-names = "apb_pclk"; 7263 7264 in-ports { 7265 #address-cells = <1>; 7266 #size-cells = <0>; 7267 7268 port@4 { 7269 reg = <4>; 7270 7271 dlct1_tpda_in4: endpoint { 7272 remote-endpoint = <&lpass_cx_funnel_out>; 7273 }; 7274 }; 7275 7276 port@13 { 7277 reg = <19>; 7278 7279 dlct1_tpda_in19: endpoint { 7280 remote-endpoint = <&prng_tpdm_out>; 7281 }; 7282 }; 7283 7284 port@14 { 7285 reg = <20>; 7286 7287 dlct1_tpda_in20: endpoint { 7288 remote-endpoint = <&qm_tpdm_out>; 7289 }; 7290 }; 7291 7292 port@15 { 7293 reg = <21>; 7294 7295 dlct1_tpda_in21: endpoint { 7296 remote-endpoint = <&gcc_tpdm_out>; 7297 }; 7298 }; 7299 7300 port@1a { 7301 reg = <26>; 7302 7303 dlct1_tpda_in26: endpoint { 7304 remote-endpoint = <&dlct1_tpdm_out>; 7305 }; 7306 }; 7307 7308 port@1b { 7309 reg = <27>; 7310 7311 dlct1_tpda_in27: endpoint { 7312 remote-endpoint = <&ipcc_tpdm_out>; 7313 }; 7314 }; 7315 }; 7316 7317 out-ports { 7318 port { 7319 dlct1_tpda_out: endpoint { 7320 remote-endpoint = <&dlct1_funnel_in0>; 7321 }; 7322 }; 7323 }; 7324 }; 7325 7326 funnel@10c2c000 { 7327 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 7328 reg = <0x0 0x10c2c000 0x0 0x1000>; 7329 7330 clocks = <&aoss_qmp>; 7331 clock-names = "apb_pclk"; 7332 7333 in-ports { 7334 #address-cells = <1>; 7335 #size-cells = <0>; 7336 7337 port@0 { 7338 reg = <0>; 7339 7340 dlct1_funnel_in0: endpoint { 7341 remote-endpoint = <&dlct1_tpda_out>; 7342 }; 7343 }; 7344 7345 port@4 { 7346 reg = <4>; 7347 7348 dlct1_funnel_in4: endpoint { 7349 remote-endpoint = <&dlct2_funnel_out>; 7350 }; 7351 }; 7352 7353 port@5 { 7354 reg = <5>; 7355 7356 dlct1_funnel_in5: endpoint { 7357 remote-endpoint = <&ddr_funnel0_out>; 7358 }; 7359 }; 7360 }; 7361 7362 out-ports { 7363 port { 7364 dlct1_funnel_out: endpoint { 7365 remote-endpoint = <&funnel1_in6>; 7366 }; 7367 }; 7368 }; 7369 }; 7370 7371 tpdm@10c38000 { 7372 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7373 reg = <0x0 0x10c38000 0x0 0x1000>; 7374 7375 clocks = <&aoss_qmp>; 7376 clock-names = "apb_pclk"; 7377 7378 qcom,cmb-element-bits = <64>; 7379 qcom,cmb-msrs-num = <32>; 7380 7381 out-ports { 7382 port { 7383 dlct2_tpdm0_out: endpoint { 7384 remote-endpoint = <&dlct2_tpda_in16>; 7385 }; 7386 }; 7387 }; 7388 }; 7389 7390 tpdm@10c39000 { 7391 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7392 reg = <0x0 0x10c39000 0x0 0x1000>; 7393 7394 clocks = <&aoss_qmp>; 7395 clock-names = "apb_pclk"; 7396 7397 qcom,cmb-element-bits = <64>; 7398 qcom,cmb-msrs-num = <32>; 7399 7400 out-ports { 7401 port { 7402 dlct2_tpdm1_out: endpoint { 7403 remote-endpoint = <&dlct2_tpda_in17>; 7404 }; 7405 }; 7406 }; 7407 }; 7408 7409 tpda@10c3c000 { 7410 compatible = "qcom,coresight-tpda", "arm,primecell"; 7411 reg = <0x0 0x10c3c000 0x0 0x1000>; 7412 7413 clocks = <&aoss_qmp>; 7414 clock-names = "apb_pclk"; 7415 7416 in-ports { 7417 #address-cells = <1>; 7418 #size-cells = <0>; 7419 7420 port@4 { 7421 reg = <4>; 7422 7423 dlct2_tpda_in4: endpoint { 7424 remote-endpoint = <&mm_funnel_out>; 7425 }; 7426 }; 7427 7428 port@f { 7429 reg = <15>; 7430 7431 dlct2_tpda_in15: endpoint { 7432 remote-endpoint = <&mxa_tpdm_out>; 7433 }; 7434 }; 7435 7436 port@10 { 7437 reg = <16>; 7438 7439 dlct2_tpda_in16: endpoint { 7440 remote-endpoint = <&dlct2_tpdm0_out>; 7441 }; 7442 }; 7443 7444 port@11 { 7445 reg = <17>; 7446 7447 dlct2_tpda_in17: endpoint { 7448 remote-endpoint = <&dlct2_tpdm1_out>; 7449 }; 7450 }; 7451 }; 7452 7453 out-ports { 7454 port { 7455 dlct2_tpda_out: endpoint { 7456 remote-endpoint = <&dlct2_funnel_in0>; 7457 }; 7458 }; 7459 }; 7460 }; 7461 7462 funnel@10c3d000 { 7463 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 7464 reg = <0x0 0x10c3d000 0x0 0x1000>; 7465 7466 clocks = <&aoss_qmp>; 7467 clock-names = "apb_pclk"; 7468 7469 in-ports { 7470 port { 7471 dlct2_funnel_in0: endpoint { 7472 remote-endpoint = <&dlct2_tpda_out>; 7473 }; 7474 }; 7475 }; 7476 7477 out-ports { 7478 port { 7479 dlct2_funnel_out: endpoint { 7480 remote-endpoint = <&dlct1_funnel_in4>; 7481 }; 7482 }; 7483 }; 7484 }; 7485 7486 tpdm@10cc1000 { 7487 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7488 reg = <0x0 0x10cc1000 0x0 0x1000>; 7489 7490 clocks = <&aoss_qmp>; 7491 clock-names = "apb_pclk"; 7492 7493 qcom,cmb-element-bits = <64>; 7494 qcom,cmb-msrs-num = <32>; 7495 qcom,dsb-element-bits = <32>; 7496 qcom,dsb-msrs-num = <32>; 7497 status = "disabled"; 7498 7499 out-ports { 7500 port { 7501 tmess_tpdm1_out: endpoint { 7502 remote-endpoint = <&tmess_tpda_in2>; 7503 }; 7504 }; 7505 }; 7506 }; 7507 7508 tpda@10cc4000 { 7509 compatible = "qcom,coresight-tpda", "arm,primecell"; 7510 reg = <0x0 0x10cc4000 0x0 0x1000>; 7511 7512 clocks = <&aoss_qmp>; 7513 clock-names = "apb_pclk"; 7514 7515 in-ports { 7516 #address-cells = <1>; 7517 #size-cells = <0>; 7518 7519 port@2 { 7520 reg = <2>; 7521 7522 tmess_tpda_in2: endpoint { 7523 remote-endpoint = <&tmess_tpdm1_out>; 7524 }; 7525 }; 7526 }; 7527 7528 out-ports { 7529 port { 7530 tmess_tpda_out: endpoint { 7531 remote-endpoint = <&tmess_funnel_in0>; 7532 }; 7533 }; 7534 }; 7535 }; 7536 7537 funnel@10cc5000 { 7538 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 7539 reg = <0x0 0x10cc5000 0x0 0x1000>; 7540 7541 clocks = <&aoss_qmp>; 7542 clock-names = "apb_pclk"; 7543 7544 in-ports { 7545 port { 7546 tmess_funnel_in0: endpoint { 7547 remote-endpoint = <&tmess_tpda_out>; 7548 }; 7549 }; 7550 }; 7551 7552 out-ports { 7553 port { 7554 tmess_funnel_out: endpoint { 7555 remote-endpoint = <&funnel1_in2>; 7556 }; 7557 }; 7558 }; 7559 }; 7560 7561 funnel@10d04000 { 7562 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 7563 reg = <0x0 0x10d04000 0x0 0x1000>; 7564 7565 clocks = <&aoss_qmp>; 7566 clock-names = "apb_pclk"; 7567 7568 in-ports { 7569 #address-cells = <1>; 7570 #size-cells = <0>; 7571 7572 port@6 { 7573 reg = <6>; 7574 7575 ddr_funnel0_in6: endpoint { 7576 remote-endpoint = <&ddr_funnel1_out>; 7577 }; 7578 }; 7579 }; 7580 7581 out-ports { 7582 port { 7583 ddr_funnel0_out: endpoint { 7584 remote-endpoint = <&dlct1_funnel_in5>; 7585 }; 7586 }; 7587 }; 7588 }; 7589 7590 tpdm@10d08000 { 7591 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7592 reg = <0x0 0x10d08000 0x0 0x1000>; 7593 7594 clocks = <&aoss_qmp>; 7595 clock-names = "apb_pclk"; 7596 7597 qcom,cmb-element-bits = <32>; 7598 qcom,cmb-msrs-num = <32>; 7599 7600 out-ports { 7601 port { 7602 llcc0_tpdm_out: endpoint { 7603 remote-endpoint = <&llcc_tpda_in0>; 7604 }; 7605 }; 7606 }; 7607 }; 7608 7609 tpdm@10d09000 { 7610 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7611 reg = <0x0 0x10d09000 0x0 0x1000>; 7612 7613 clocks = <&aoss_qmp>; 7614 clock-names = "apb_pclk"; 7615 7616 qcom,cmb-element-bits = <32>; 7617 qcom,cmb-msrs-num = <32>; 7618 7619 out-ports { 7620 port { 7621 llcc1_tpdm_out: endpoint { 7622 remote-endpoint = <&llcc_tpda_in1>; 7623 }; 7624 }; 7625 }; 7626 }; 7627 7628 tpdm@10d0a000 { 7629 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7630 reg = <0x0 0x10d0a000 0x0 0x1000>; 7631 7632 clocks = <&aoss_qmp>; 7633 clock-names = "apb_pclk"; 7634 7635 qcom,cmb-element-bits = <32>; 7636 qcom,cmb-msrs-num = <32>; 7637 7638 out-ports { 7639 port { 7640 llcc2_tpdm_out: endpoint { 7641 remote-endpoint = <&llcc_tpda_in2>; 7642 }; 7643 }; 7644 }; 7645 }; 7646 7647 tpdm@10d0b000 { 7648 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7649 reg = <0x0 0x10d0b000 0x0 0x1000>; 7650 7651 clocks = <&aoss_qmp>; 7652 clock-names = "apb_pclk"; 7653 7654 qcom,cmb-element-bits = <32>; 7655 qcom,cmb-msrs-num = <32>; 7656 7657 out-ports { 7658 port { 7659 llcc3_tpdm_out: endpoint { 7660 remote-endpoint = <&llcc_tpda_in3>; 7661 }; 7662 }; 7663 }; 7664 }; 7665 7666 tpdm@10d0c000 { 7667 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7668 reg = <0x0 0x10d0c000 0x0 0x1000>; 7669 7670 clocks = <&aoss_qmp>; 7671 clock-names = "apb_pclk"; 7672 7673 qcom,cmb-element-bits = <32>; 7674 qcom,cmb-msrs-num = <32>; 7675 7676 out-ports { 7677 port { 7678 llcc4_tpdm_out: endpoint { 7679 remote-endpoint = <&llcc_tpda_in4>; 7680 }; 7681 }; 7682 }; 7683 }; 7684 7685 tpdm@10d0d000 { 7686 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7687 reg = <0x0 0x10d0d000 0x0 0x1000>; 7688 7689 clocks = <&aoss_qmp>; 7690 clock-names = "apb_pclk"; 7691 7692 qcom,cmb-element-bits = <32>; 7693 qcom,cmb-msrs-num = <32>; 7694 7695 out-ports { 7696 port { 7697 llcc5_tpdm_out: endpoint { 7698 remote-endpoint = <&llcc_tpda_in5>; 7699 }; 7700 }; 7701 }; 7702 }; 7703 7704 tpdm@10d0e000 { 7705 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7706 reg = <0x0 0x10d0e000 0x0 0x1000>; 7707 7708 clocks = <&aoss_qmp>; 7709 clock-names = "apb_pclk"; 7710 7711 qcom,cmb-element-bits = <32>; 7712 qcom,cmb-msrs-num = <32>; 7713 7714 out-ports { 7715 port { 7716 llcc6_tpdm_out: endpoint { 7717 remote-endpoint = <&llcc_tpda_in6>; 7718 }; 7719 }; 7720 }; 7721 }; 7722 7723 tpdm@10d0f000 { 7724 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7725 reg = <0x0 0x10d0f000 0x0 0x1000>; 7726 7727 clocks = <&aoss_qmp>; 7728 clock-names = "apb_pclk"; 7729 7730 qcom,cmb-element-bits = <32>; 7731 qcom,cmb-msrs-num = <32>; 7732 7733 out-ports { 7734 port { 7735 llcc7_tpdm_out: endpoint { 7736 remote-endpoint = <&llcc_tpda_in7>; 7737 }; 7738 }; 7739 }; 7740 }; 7741 7742 tpda@10d12000 { 7743 compatible = "qcom,coresight-tpda", "arm,primecell"; 7744 reg = <0x0 0x10d12000 0x0 0x1000>; 7745 7746 clocks = <&aoss_qmp>; 7747 clock-names = "apb_pclk"; 7748 7749 in-ports { 7750 #address-cells = <1>; 7751 #size-cells = <0>; 7752 7753 port@0 { 7754 reg = <0>; 7755 7756 llcc_tpda_in0: endpoint { 7757 remote-endpoint = <&llcc0_tpdm_out>; 7758 }; 7759 }; 7760 7761 port@1 { 7762 reg = <1>; 7763 7764 llcc_tpda_in1: endpoint { 7765 remote-endpoint = <&llcc1_tpdm_out>; 7766 }; 7767 }; 7768 7769 port@2 { 7770 reg = <2>; 7771 7772 llcc_tpda_in2: endpoint { 7773 remote-endpoint = <&llcc2_tpdm_out>; 7774 }; 7775 }; 7776 7777 port@3 { 7778 reg = <3>; 7779 7780 llcc_tpda_in3: endpoint { 7781 remote-endpoint = <&llcc3_tpdm_out>; 7782 }; 7783 }; 7784 7785 port@4 { 7786 reg = <4>; 7787 7788 llcc_tpda_in4: endpoint { 7789 remote-endpoint = <&llcc4_tpdm_out>; 7790 }; 7791 }; 7792 7793 port@5 { 7794 reg = <5>; 7795 7796 llcc_tpda_in5: endpoint { 7797 remote-endpoint = <&llcc5_tpdm_out>; 7798 }; 7799 }; 7800 7801 port@6 { 7802 reg = <6>; 7803 7804 llcc_tpda_in6: endpoint { 7805 remote-endpoint = <&llcc6_tpdm_out>; 7806 }; 7807 }; 7808 7809 port@7 { 7810 reg = <7>; 7811 7812 llcc_tpda_in7: endpoint { 7813 remote-endpoint = <&llcc7_tpdm_out>; 7814 }; 7815 }; 7816 }; 7817 7818 out-ports { 7819 port { 7820 llcc_tpda_out: endpoint { 7821 remote-endpoint = <&ddr_funnel1_in0>; 7822 }; 7823 }; 7824 }; 7825 }; 7826 7827 funnel@10d13000 { 7828 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 7829 reg = <0x0 0x10d13000 0x0 0x1000>; 7830 7831 clocks = <&aoss_qmp>; 7832 clock-names = "apb_pclk"; 7833 7834 in-ports { 7835 port { 7836 ddr_funnel1_in0: endpoint { 7837 remote-endpoint = <&llcc_tpda_out>; 7838 }; 7839 }; 7840 }; 7841 7842 out-ports { 7843 port { 7844 ddr_funnel1_out: endpoint { 7845 remote-endpoint = <&ddr_funnel0_in6>; 7846 }; 7847 }; 7848 }; 7849 }; 7850 7851 apps_smmu: iommu@15000000 { 7852 compatible = "qcom,x1e80100-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 7853 reg = <0 0x15000000 0 0x100000>; 7854 7855 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 7856 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 7857 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 7858 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 7859 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 7860 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 7861 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 7862 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 7863 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 7864 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 7865 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 7866 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 7867 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 7868 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 7869 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 7870 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 7871 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 7872 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 7873 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 7874 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 7875 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 7876 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 7877 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 7878 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 7879 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 7880 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 7881 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 7882 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 7883 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 7884 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 7885 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 7886 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 7887 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 7888 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 7889 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 7890 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 7891 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 7892 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 7893 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 7894 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 7895 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 7896 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 7897 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 7898 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 7899 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 7900 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 7901 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 7902 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 7903 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 7904 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 7905 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 7906 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 7907 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 7908 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 7909 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 7910 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 7911 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 7912 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 7913 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 7914 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 7915 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 7916 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 7917 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 7918 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 7919 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 7920 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 7921 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 7922 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 7923 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 7924 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 7925 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 7926 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 7927 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 7928 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 7929 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 7930 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 7931 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 7932 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 7933 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 7934 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 7935 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 7936 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 7937 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 7938 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 7939 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 7940 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 7941 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 7942 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 7943 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 7944 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 7945 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 7946 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 7947 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 7948 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 7949 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 7950 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 7951 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>; 7952 7953 #iommu-cells = <2>; 7954 #global-interrupts = <1>; 7955 7956 dma-coherent; 7957 }; 7958 7959 intc: interrupt-controller@17000000 { 7960 compatible = "arm,gic-v3"; 7961 reg = <0 0x17000000 0 0x10000>, /* GICD */ 7962 <0 0x17080000 0 0x300000>; /* GICR * 12 */ 7963 7964 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 7965 7966 #interrupt-cells = <3>; 7967 interrupt-controller; 7968 7969 #redistributor-regions = <1>; 7970 redistributor-stride = <0x0 0x40000>; 7971 7972 #address-cells = <2>; 7973 #size-cells = <2>; 7974 ranges; 7975 7976 gic_its: msi-controller@17040000 { 7977 compatible = "arm,gic-v3-its"; 7978 reg = <0 0x17040000 0 0x40000>; 7979 7980 msi-controller; 7981 #msi-cells = <1>; 7982 }; 7983 }; 7984 7985 apps_rsc: rsc@17500000 { 7986 compatible = "qcom,rpmh-rsc"; 7987 reg = <0 0x17500000 0 0x10000>, 7988 <0 0x17510000 0 0x10000>, 7989 <0 0x17520000 0 0x10000>; 7990 reg-names = "drv-0", "drv-1", "drv-2"; 7991 7992 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 7993 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 7994 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 7995 qcom,tcs-offset = <0xd00>; 7996 qcom,drv-id = <2>; 7997 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, 7998 <WAKE_TCS 2>, <CONTROL_TCS 0>; 7999 8000 label = "apps_rsc"; 8001 power-domains = <&system_pd>; 8002 8003 apps_bcm_voter: bcm-voter { 8004 compatible = "qcom,bcm-voter"; 8005 }; 8006 8007 rpmhcc: clock-controller { 8008 compatible = "qcom,x1e80100-rpmh-clk"; 8009 8010 clocks = <&xo_board>; 8011 clock-names = "xo"; 8012 8013 #clock-cells = <1>; 8014 }; 8015 8016 rpmhpd: power-controller { 8017 compatible = "qcom,x1e80100-rpmhpd"; 8018 8019 operating-points-v2 = <&rpmhpd_opp_table>; 8020 8021 #power-domain-cells = <1>; 8022 8023 rpmhpd_opp_table: opp-table { 8024 compatible = "operating-points-v2"; 8025 8026 rpmhpd_opp_ret: opp-16 { 8027 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 8028 }; 8029 8030 rpmhpd_opp_min_svs: opp-48 { 8031 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 8032 }; 8033 8034 rpmhpd_opp_low_svs_d2: opp-52 { 8035 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; 8036 }; 8037 8038 rpmhpd_opp_low_svs_d1: opp-56 { 8039 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 8040 }; 8041 8042 rpmhpd_opp_low_svs_d0: opp-60 { 8043 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; 8044 }; 8045 8046 rpmhpd_opp_low_svs: opp-64 { 8047 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 8048 }; 8049 8050 rpmhpd_opp_low_svs_l1: opp-80 { 8051 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 8052 }; 8053 8054 rpmhpd_opp_svs: opp-128 { 8055 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 8056 }; 8057 8058 rpmhpd_opp_svs_l0: opp-144 { 8059 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 8060 }; 8061 8062 rpmhpd_opp_svs_l1: opp-192 { 8063 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 8064 }; 8065 8066 rpmhpd_opp_nom: opp-256 { 8067 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 8068 }; 8069 8070 rpmhpd_opp_nom_l1: opp-320 { 8071 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 8072 }; 8073 8074 rpmhpd_opp_nom_l2: opp-336 { 8075 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 8076 }; 8077 8078 rpmhpd_opp_turbo: opp-384 { 8079 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 8080 }; 8081 8082 rpmhpd_opp_turbo_l1: opp-416 { 8083 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 8084 }; 8085 }; 8086 }; 8087 }; 8088 8089 timer@17800000 { 8090 compatible = "arm,armv7-timer-mem"; 8091 reg = <0 0x17800000 0 0x1000>; 8092 8093 #address-cells = <2>; 8094 #size-cells = <1>; 8095 ranges = <0 0 0 0 0x20000000>; 8096 8097 frame@17801000 { 8098 reg = <0 0x17801000 0x1000>, 8099 <0 0x17802000 0x1000>; 8100 8101 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 8102 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 8103 8104 frame-number = <0>; 8105 }; 8106 8107 frame@17803000 { 8108 reg = <0 0x17803000 0x1000>; 8109 8110 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 8111 8112 frame-number = <1>; 8113 8114 status = "disabled"; 8115 }; 8116 8117 frame@17805000 { 8118 reg = <0 0x17805000 0x1000>; 8119 8120 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 8121 8122 frame-number = <2>; 8123 8124 status = "disabled"; 8125 }; 8126 8127 frame@17807000 { 8128 reg = <0 0x17807000 0x1000>; 8129 8130 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 8131 8132 frame-number = <3>; 8133 8134 status = "disabled"; 8135 }; 8136 8137 frame@17809000 { 8138 reg = <0 0x17809000 0x1000>; 8139 8140 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 8141 8142 frame-number = <4>; 8143 8144 status = "disabled"; 8145 }; 8146 8147 frame@1780b000 { 8148 reg = <0 0x1780b000 0x1000>; 8149 8150 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 8151 8152 frame-number = <5>; 8153 8154 status = "disabled"; 8155 }; 8156 8157 frame@1780d000 { 8158 reg = <0 0x1780d000 0x1000>; 8159 8160 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 8161 8162 frame-number = <6>; 8163 8164 status = "disabled"; 8165 }; 8166 }; 8167 8168 pmu@24091000 { 8169 compatible = "qcom,x1e80100-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 8170 reg = <0 0x24091000 0 0x1000>; 8171 8172 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 8173 8174 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 8175 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 8176 8177 operating-points-v2 = <&llcc_bwmon_opp_table>; 8178 8179 llcc_bwmon_opp_table: opp-table { 8180 compatible = "operating-points-v2"; 8181 8182 opp-0 { 8183 opp-peak-kBps = <800000>; 8184 }; 8185 8186 opp-1 { 8187 opp-peak-kBps = <2188000>; 8188 }; 8189 8190 opp-2 { 8191 opp-peak-kBps = <3072000>; 8192 }; 8193 8194 opp-3 { 8195 opp-peak-kBps = <6220800>; 8196 }; 8197 8198 opp-4 { 8199 opp-peak-kBps = <6835200>; 8200 }; 8201 8202 opp-5 { 8203 opp-peak-kBps = <8371200>; 8204 }; 8205 8206 opp-6 { 8207 opp-peak-kBps = <10944000>; 8208 }; 8209 8210 opp-7 { 8211 opp-peak-kBps = <12748800>; 8212 }; 8213 8214 opp-8 { 8215 opp-peak-kBps = <14745600>; 8216 }; 8217 8218 opp-9 { 8219 opp-peak-kBps = <16896000>; 8220 }; 8221 }; 8222 }; 8223 8224 /* cluster0 */ 8225 pmu@240b3400 { 8226 compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon"; 8227 reg = <0 0x240b3400 0 0x600>; 8228 8229 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 8230 8231 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 8232 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 8233 8234 operating-points-v2 = <&cpu_bwmon_opp_table>; 8235 8236 cpu_bwmon_opp_table: opp-table { 8237 compatible = "operating-points-v2"; 8238 8239 opp-0 { 8240 opp-peak-kBps = <4800000>; 8241 }; 8242 8243 opp-1 { 8244 opp-peak-kBps = <7464000>; 8245 }; 8246 8247 opp-2 { 8248 opp-peak-kBps = <9600000>; 8249 }; 8250 8251 opp-3 { 8252 opp-peak-kBps = <12896000>; 8253 }; 8254 8255 opp-4 { 8256 opp-peak-kBps = <14928000>; 8257 }; 8258 8259 opp-5 { 8260 opp-peak-kBps = <17064000>; 8261 }; 8262 }; 8263 }; 8264 8265 /* cluster2 */ 8266 pmu@240b5400 { 8267 compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon"; 8268 reg = <0 0x240b5400 0 0x600>; 8269 8270 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 8271 8272 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 8273 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 8274 8275 operating-points-v2 = <&cpu_bwmon_opp_table>; 8276 }; 8277 8278 /* cluster1 */ 8279 pmu@240b6400 { 8280 compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon"; 8281 reg = <0 0x240b6400 0 0x600>; 8282 8283 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 8284 8285 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 8286 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 8287 8288 operating-points-v2 = <&cpu_bwmon_opp_table>; 8289 }; 8290 8291 system-cache-controller@25000000 { 8292 compatible = "qcom,x1e80100-llcc"; 8293 reg = <0 0x25000000 0 0x200000>, 8294 <0 0x25200000 0 0x200000>, 8295 <0 0x25400000 0 0x200000>, 8296 <0 0x25600000 0 0x200000>, 8297 <0 0x25800000 0 0x200000>, 8298 <0 0x25a00000 0 0x200000>, 8299 <0 0x25c00000 0 0x200000>, 8300 <0 0x25e00000 0 0x200000>, 8301 <0 0x26000000 0 0x200000>, 8302 <0 0x26200000 0 0x200000>; 8303 reg-names = "llcc0_base", 8304 "llcc1_base", 8305 "llcc2_base", 8306 "llcc3_base", 8307 "llcc4_base", 8308 "llcc5_base", 8309 "llcc6_base", 8310 "llcc7_base", 8311 "llcc_broadcast_base", 8312 "llcc_broadcast_and_base"; 8313 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 8314 }; 8315 8316 remoteproc_cdsp: remoteproc@32300000 { 8317 compatible = "qcom,x1e80100-cdsp-pas"; 8318 reg = <0x0 0x32300000 0x0 0x10000>; 8319 8320 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 8321 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 8322 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 8323 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 8324 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 8325 interrupt-names = "wdog", 8326 "fatal", 8327 "ready", 8328 "handover", 8329 "stop-ack"; 8330 8331 clocks = <&rpmhcc RPMH_CXO_CLK>; 8332 clock-names = "xo"; 8333 8334 power-domains = <&rpmhpd RPMHPD_CX>, 8335 <&rpmhpd RPMHPD_MXC>, 8336 <&rpmhpd RPMHPD_NSP>; 8337 power-domain-names = "cx", 8338 "mxc", 8339 "nsp"; 8340 8341 interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS 8342 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 8343 8344 memory-region = <&cdsp_mem>, 8345 <&q6_cdsp_dtb_mem>; 8346 8347 qcom,qmp = <&aoss_qmp>; 8348 8349 qcom,smem-states = <&smp2p_cdsp_out 0>; 8350 qcom,smem-state-names = "stop"; 8351 8352 status = "disabled"; 8353 8354 glink-edge { 8355 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 8356 IPCC_MPROC_SIGNAL_GLINK_QMP 8357 IRQ_TYPE_EDGE_RISING>; 8358 mboxes = <&ipcc IPCC_CLIENT_CDSP 8359 IPCC_MPROC_SIGNAL_GLINK_QMP>; 8360 8361 label = "cdsp"; 8362 qcom,remote-pid = <5>; 8363 8364 fastrpc { 8365 compatible = "qcom,fastrpc"; 8366 qcom,glink-channels = "fastrpcglink-apps-dsp"; 8367 label = "cdsp"; 8368 qcom,non-secure-domain; 8369 #address-cells = <1>; 8370 #size-cells = <0>; 8371 8372 compute-cb@1 { 8373 compatible = "qcom,fastrpc-compute-cb"; 8374 reg = <1>; 8375 iommus = <&apps_smmu 0x0c01 0x20>; 8376 dma-coherent; 8377 }; 8378 8379 compute-cb@2 { 8380 compatible = "qcom,fastrpc-compute-cb"; 8381 reg = <2>; 8382 iommus = <&apps_smmu 0x0c02 0x20>; 8383 dma-coherent; 8384 }; 8385 8386 compute-cb@3 { 8387 compatible = "qcom,fastrpc-compute-cb"; 8388 reg = <3>; 8389 iommus = <&apps_smmu 0x0c03 0x20>; 8390 dma-coherent; 8391 }; 8392 8393 compute-cb@4 { 8394 compatible = "qcom,fastrpc-compute-cb"; 8395 reg = <4>; 8396 iommus = <&apps_smmu 0x0c04 0x20>; 8397 dma-coherent; 8398 }; 8399 8400 compute-cb@5 { 8401 compatible = "qcom,fastrpc-compute-cb"; 8402 reg = <5>; 8403 iommus = <&apps_smmu 0x0c05 0x20>; 8404 dma-coherent; 8405 }; 8406 8407 compute-cb@6 { 8408 compatible = "qcom,fastrpc-compute-cb"; 8409 reg = <6>; 8410 iommus = <&apps_smmu 0x0c06 0x20>; 8411 dma-coherent; 8412 }; 8413 8414 compute-cb@7 { 8415 compatible = "qcom,fastrpc-compute-cb"; 8416 reg = <7>; 8417 iommus = <&apps_smmu 0x0c07 0x20>; 8418 dma-coherent; 8419 }; 8420 8421 compute-cb@8 { 8422 compatible = "qcom,fastrpc-compute-cb"; 8423 reg = <8>; 8424 iommus = <&apps_smmu 0x0c08 0x20>; 8425 dma-coherent; 8426 }; 8427 8428 /* note: compute-cb@9 is secure */ 8429 8430 compute-cb@10 { 8431 compatible = "qcom,fastrpc-compute-cb"; 8432 reg = <10>; 8433 iommus = <&apps_smmu 0x0c0c 0x20>; 8434 dma-coherent; 8435 }; 8436 8437 compute-cb@11 { 8438 compatible = "qcom,fastrpc-compute-cb"; 8439 reg = <11>; 8440 iommus = <&apps_smmu 0x0c0d 0x20>; 8441 dma-coherent; 8442 }; 8443 8444 compute-cb@12 { 8445 compatible = "qcom,fastrpc-compute-cb"; 8446 reg = <12>; 8447 iommus = <&apps_smmu 0x0c0e 0x20>; 8448 dma-coherent; 8449 }; 8450 8451 compute-cb@13 { 8452 compatible = "qcom,fastrpc-compute-cb"; 8453 reg = <13>; 8454 iommus = <&apps_smmu 0x0c0f 0x20>; 8455 dma-coherent; 8456 }; 8457 }; 8458 }; 8459 }; 8460 }; 8461 8462 timer { 8463 compatible = "arm,armv8-timer"; 8464 8465 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 8466 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 8467 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 8468 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 8469 }; 8470 8471 thermal-zones { 8472 aoss0-thermal { 8473 thermal-sensors = <&tsens0 0>; 8474 8475 trips { 8476 trip-point0 { 8477 temperature = <90000>; 8478 hysteresis = <2000>; 8479 type = "hot"; 8480 }; 8481 8482 aoss0-critical { 8483 temperature = <125000>; 8484 hysteresis = <0>; 8485 type = "critical"; 8486 }; 8487 }; 8488 }; 8489 8490 cpu0-0-top-thermal { 8491 polling-delay-passive = <250>; 8492 8493 thermal-sensors = <&tsens0 1>; 8494 8495 trips { 8496 trip-point0 { 8497 temperature = <90000>; 8498 hysteresis = <2000>; 8499 type = "passive"; 8500 }; 8501 8502 trip-point1 { 8503 temperature = <95000>; 8504 hysteresis = <2000>; 8505 type = "passive"; 8506 }; 8507 8508 cpu-critical { 8509 temperature = <110000>; 8510 hysteresis = <1000>; 8511 type = "critical"; 8512 }; 8513 }; 8514 }; 8515 8516 cpu0-0-btm-thermal { 8517 polling-delay-passive = <250>; 8518 8519 thermal-sensors = <&tsens0 2>; 8520 8521 trips { 8522 trip-point0 { 8523 temperature = <90000>; 8524 hysteresis = <2000>; 8525 type = "passive"; 8526 }; 8527 8528 trip-point1 { 8529 temperature = <95000>; 8530 hysteresis = <2000>; 8531 type = "passive"; 8532 }; 8533 8534 cpu-critical { 8535 temperature = <110000>; 8536 hysteresis = <1000>; 8537 type = "critical"; 8538 }; 8539 }; 8540 }; 8541 8542 cpu0-1-top-thermal { 8543 polling-delay-passive = <250>; 8544 8545 thermal-sensors = <&tsens0 3>; 8546 8547 trips { 8548 trip-point0 { 8549 temperature = <90000>; 8550 hysteresis = <2000>; 8551 type = "passive"; 8552 }; 8553 8554 trip-point1 { 8555 temperature = <95000>; 8556 hysteresis = <2000>; 8557 type = "passive"; 8558 }; 8559 8560 cpu-critical { 8561 temperature = <110000>; 8562 hysteresis = <1000>; 8563 type = "critical"; 8564 }; 8565 }; 8566 }; 8567 8568 cpu0-1-btm-thermal { 8569 polling-delay-passive = <250>; 8570 8571 thermal-sensors = <&tsens0 4>; 8572 8573 trips { 8574 trip-point0 { 8575 temperature = <90000>; 8576 hysteresis = <2000>; 8577 type = "passive"; 8578 }; 8579 8580 trip-point1 { 8581 temperature = <95000>; 8582 hysteresis = <2000>; 8583 type = "passive"; 8584 }; 8585 8586 cpu-critical { 8587 temperature = <110000>; 8588 hysteresis = <1000>; 8589 type = "critical"; 8590 }; 8591 }; 8592 }; 8593 8594 cpu0-2-top-thermal { 8595 polling-delay-passive = <250>; 8596 8597 thermal-sensors = <&tsens0 5>; 8598 8599 trips { 8600 trip-point0 { 8601 temperature = <90000>; 8602 hysteresis = <2000>; 8603 type = "passive"; 8604 }; 8605 8606 trip-point1 { 8607 temperature = <95000>; 8608 hysteresis = <2000>; 8609 type = "passive"; 8610 }; 8611 8612 cpu-critical { 8613 temperature = <110000>; 8614 hysteresis = <1000>; 8615 type = "critical"; 8616 }; 8617 }; 8618 }; 8619 8620 cpu0-2-btm-thermal { 8621 polling-delay-passive = <250>; 8622 8623 thermal-sensors = <&tsens0 6>; 8624 8625 trips { 8626 trip-point0 { 8627 temperature = <90000>; 8628 hysteresis = <2000>; 8629 type = "passive"; 8630 }; 8631 8632 trip-point1 { 8633 temperature = <95000>; 8634 hysteresis = <2000>; 8635 type = "passive"; 8636 }; 8637 8638 cpu-critical { 8639 temperature = <110000>; 8640 hysteresis = <1000>; 8641 type = "critical"; 8642 }; 8643 }; 8644 }; 8645 8646 cpu0-3-top-thermal { 8647 polling-delay-passive = <250>; 8648 8649 thermal-sensors = <&tsens0 7>; 8650 8651 trips { 8652 trip-point0 { 8653 temperature = <90000>; 8654 hysteresis = <2000>; 8655 type = "passive"; 8656 }; 8657 8658 trip-point1 { 8659 temperature = <95000>; 8660 hysteresis = <2000>; 8661 type = "passive"; 8662 }; 8663 8664 cpu-critical { 8665 temperature = <110000>; 8666 hysteresis = <1000>; 8667 type = "critical"; 8668 }; 8669 }; 8670 }; 8671 8672 cpu0-3-btm-thermal { 8673 polling-delay-passive = <250>; 8674 8675 thermal-sensors = <&tsens0 8>; 8676 8677 trips { 8678 trip-point0 { 8679 temperature = <90000>; 8680 hysteresis = <2000>; 8681 type = "passive"; 8682 }; 8683 8684 trip-point1 { 8685 temperature = <95000>; 8686 hysteresis = <2000>; 8687 type = "passive"; 8688 }; 8689 8690 cpu-critical { 8691 temperature = <110000>; 8692 hysteresis = <1000>; 8693 type = "critical"; 8694 }; 8695 }; 8696 }; 8697 8698 cpuss0-top-thermal { 8699 thermal-sensors = <&tsens0 9>; 8700 8701 trips { 8702 trip-point0 { 8703 temperature = <90000>; 8704 hysteresis = <2000>; 8705 type = "hot"; 8706 }; 8707 8708 cpuss2-critical { 8709 temperature = <125000>; 8710 hysteresis = <0>; 8711 type = "critical"; 8712 }; 8713 }; 8714 }; 8715 8716 cpuss0-btm-thermal { 8717 thermal-sensors = <&tsens0 10>; 8718 8719 trips { 8720 trip-point0 { 8721 temperature = <90000>; 8722 hysteresis = <2000>; 8723 type = "hot"; 8724 }; 8725 8726 cpuss2-critical { 8727 temperature = <125000>; 8728 hysteresis = <0>; 8729 type = "critical"; 8730 }; 8731 }; 8732 }; 8733 8734 mem-thermal { 8735 thermal-sensors = <&tsens0 11>; 8736 8737 trips { 8738 trip-point0 { 8739 temperature = <90000>; 8740 hysteresis = <2000>; 8741 type = "hot"; 8742 }; 8743 8744 mem-critical { 8745 temperature = <125000>; 8746 hysteresis = <0>; 8747 type = "critical"; 8748 }; 8749 }; 8750 }; 8751 8752 video-thermal { 8753 polling-delay-passive = <250>; 8754 8755 thermal-sensors = <&tsens0 12>; 8756 8757 trips { 8758 trip-point0 { 8759 temperature = <125000>; 8760 hysteresis = <1000>; 8761 type = "passive"; 8762 }; 8763 }; 8764 }; 8765 8766 aoss1-thermal { 8767 thermal-sensors = <&tsens1 0>; 8768 8769 trips { 8770 trip-point0 { 8771 temperature = <90000>; 8772 hysteresis = <2000>; 8773 type = "hot"; 8774 }; 8775 8776 aoss0-critical { 8777 temperature = <125000>; 8778 hysteresis = <0>; 8779 type = "critical"; 8780 }; 8781 }; 8782 }; 8783 8784 cpu1-0-top-thermal { 8785 polling-delay-passive = <250>; 8786 8787 thermal-sensors = <&tsens1 1>; 8788 8789 trips { 8790 trip-point0 { 8791 temperature = <90000>; 8792 hysteresis = <2000>; 8793 type = "passive"; 8794 }; 8795 8796 trip-point1 { 8797 temperature = <95000>; 8798 hysteresis = <2000>; 8799 type = "passive"; 8800 }; 8801 8802 cpu-critical { 8803 temperature = <110000>; 8804 hysteresis = <1000>; 8805 type = "critical"; 8806 }; 8807 }; 8808 }; 8809 8810 cpu1-0-btm-thermal { 8811 polling-delay-passive = <250>; 8812 8813 thermal-sensors = <&tsens1 2>; 8814 8815 trips { 8816 trip-point0 { 8817 temperature = <90000>; 8818 hysteresis = <2000>; 8819 type = "passive"; 8820 }; 8821 8822 trip-point1 { 8823 temperature = <95000>; 8824 hysteresis = <2000>; 8825 type = "passive"; 8826 }; 8827 8828 cpu-critical { 8829 temperature = <110000>; 8830 hysteresis = <1000>; 8831 type = "critical"; 8832 }; 8833 }; 8834 }; 8835 8836 cpu1-1-top-thermal { 8837 polling-delay-passive = <250>; 8838 8839 thermal-sensors = <&tsens1 3>; 8840 8841 trips { 8842 trip-point0 { 8843 temperature = <90000>; 8844 hysteresis = <2000>; 8845 type = "passive"; 8846 }; 8847 8848 trip-point1 { 8849 temperature = <95000>; 8850 hysteresis = <2000>; 8851 type = "passive"; 8852 }; 8853 8854 cpu-critical { 8855 temperature = <110000>; 8856 hysteresis = <1000>; 8857 type = "critical"; 8858 }; 8859 }; 8860 }; 8861 8862 cpu1-1-btm-thermal { 8863 polling-delay-passive = <250>; 8864 8865 thermal-sensors = <&tsens1 4>; 8866 8867 trips { 8868 trip-point0 { 8869 temperature = <90000>; 8870 hysteresis = <2000>; 8871 type = "passive"; 8872 }; 8873 8874 trip-point1 { 8875 temperature = <95000>; 8876 hysteresis = <2000>; 8877 type = "passive"; 8878 }; 8879 8880 cpu-critical { 8881 temperature = <110000>; 8882 hysteresis = <1000>; 8883 type = "critical"; 8884 }; 8885 }; 8886 }; 8887 8888 cpu1-2-top-thermal { 8889 polling-delay-passive = <250>; 8890 8891 thermal-sensors = <&tsens1 5>; 8892 8893 trips { 8894 trip-point0 { 8895 temperature = <90000>; 8896 hysteresis = <2000>; 8897 type = "passive"; 8898 }; 8899 8900 trip-point1 { 8901 temperature = <95000>; 8902 hysteresis = <2000>; 8903 type = "passive"; 8904 }; 8905 8906 cpu-critical { 8907 temperature = <110000>; 8908 hysteresis = <1000>; 8909 type = "critical"; 8910 }; 8911 }; 8912 }; 8913 8914 cpu1-2-btm-thermal { 8915 polling-delay-passive = <250>; 8916 8917 thermal-sensors = <&tsens1 6>; 8918 8919 trips { 8920 trip-point0 { 8921 temperature = <90000>; 8922 hysteresis = <2000>; 8923 type = "passive"; 8924 }; 8925 8926 trip-point1 { 8927 temperature = <95000>; 8928 hysteresis = <2000>; 8929 type = "passive"; 8930 }; 8931 8932 cpu-critical { 8933 temperature = <110000>; 8934 hysteresis = <1000>; 8935 type = "critical"; 8936 }; 8937 }; 8938 }; 8939 8940 cpu1-3-top-thermal { 8941 polling-delay-passive = <250>; 8942 8943 thermal-sensors = <&tsens1 7>; 8944 8945 trips { 8946 trip-point0 { 8947 temperature = <90000>; 8948 hysteresis = <2000>; 8949 type = "passive"; 8950 }; 8951 8952 trip-point1 { 8953 temperature = <95000>; 8954 hysteresis = <2000>; 8955 type = "passive"; 8956 }; 8957 8958 cpu-critical { 8959 temperature = <110000>; 8960 hysteresis = <1000>; 8961 type = "critical"; 8962 }; 8963 }; 8964 }; 8965 8966 cpu1-3-btm-thermal { 8967 polling-delay-passive = <250>; 8968 8969 thermal-sensors = <&tsens1 8>; 8970 8971 trips { 8972 trip-point0 { 8973 temperature = <90000>; 8974 hysteresis = <2000>; 8975 type = "passive"; 8976 }; 8977 8978 trip-point1 { 8979 temperature = <95000>; 8980 hysteresis = <2000>; 8981 type = "passive"; 8982 }; 8983 8984 cpu-critical { 8985 temperature = <110000>; 8986 hysteresis = <1000>; 8987 type = "critical"; 8988 }; 8989 }; 8990 }; 8991 8992 cpuss1-top-thermal { 8993 thermal-sensors = <&tsens1 9>; 8994 8995 trips { 8996 trip-point0 { 8997 temperature = <90000>; 8998 hysteresis = <2000>; 8999 type = "hot"; 9000 }; 9001 9002 cpuss2-critical { 9003 temperature = <125000>; 9004 hysteresis = <0>; 9005 type = "critical"; 9006 }; 9007 }; 9008 }; 9009 9010 cpuss1-btm-thermal { 9011 thermal-sensors = <&tsens1 10>; 9012 9013 trips { 9014 trip-point0 { 9015 temperature = <90000>; 9016 hysteresis = <2000>; 9017 type = "hot"; 9018 }; 9019 9020 cpuss2-critical { 9021 temperature = <125000>; 9022 hysteresis = <0>; 9023 type = "critical"; 9024 }; 9025 }; 9026 }; 9027 9028 aoss2-thermal { 9029 thermal-sensors = <&tsens2 0>; 9030 9031 trips { 9032 trip-point0 { 9033 temperature = <90000>; 9034 hysteresis = <2000>; 9035 type = "hot"; 9036 }; 9037 9038 aoss0-critical { 9039 temperature = <125000>; 9040 hysteresis = <0>; 9041 type = "critical"; 9042 }; 9043 }; 9044 }; 9045 9046 cpu2-0-top-thermal { 9047 polling-delay-passive = <250>; 9048 9049 thermal-sensors = <&tsens2 1>; 9050 9051 trips { 9052 trip-point0 { 9053 temperature = <90000>; 9054 hysteresis = <2000>; 9055 type = "passive"; 9056 }; 9057 9058 trip-point1 { 9059 temperature = <95000>; 9060 hysteresis = <2000>; 9061 type = "passive"; 9062 }; 9063 9064 cpu-critical { 9065 temperature = <110000>; 9066 hysteresis = <1000>; 9067 type = "critical"; 9068 }; 9069 }; 9070 }; 9071 9072 cpu2-0-btm-thermal { 9073 polling-delay-passive = <250>; 9074 9075 thermal-sensors = <&tsens2 2>; 9076 9077 trips { 9078 trip-point0 { 9079 temperature = <90000>; 9080 hysteresis = <2000>; 9081 type = "passive"; 9082 }; 9083 9084 trip-point1 { 9085 temperature = <95000>; 9086 hysteresis = <2000>; 9087 type = "passive"; 9088 }; 9089 9090 cpu-critical { 9091 temperature = <110000>; 9092 hysteresis = <1000>; 9093 type = "critical"; 9094 }; 9095 }; 9096 }; 9097 9098 cpu2-1-top-thermal { 9099 polling-delay-passive = <250>; 9100 9101 thermal-sensors = <&tsens2 3>; 9102 9103 trips { 9104 trip-point0 { 9105 temperature = <90000>; 9106 hysteresis = <2000>; 9107 type = "passive"; 9108 }; 9109 9110 trip-point1 { 9111 temperature = <95000>; 9112 hysteresis = <2000>; 9113 type = "passive"; 9114 }; 9115 9116 cpu-critical { 9117 temperature = <110000>; 9118 hysteresis = <1000>; 9119 type = "critical"; 9120 }; 9121 }; 9122 }; 9123 9124 cpu2-1-btm-thermal { 9125 polling-delay-passive = <250>; 9126 9127 thermal-sensors = <&tsens2 4>; 9128 9129 trips { 9130 trip-point0 { 9131 temperature = <90000>; 9132 hysteresis = <2000>; 9133 type = "passive"; 9134 }; 9135 9136 trip-point1 { 9137 temperature = <95000>; 9138 hysteresis = <2000>; 9139 type = "passive"; 9140 }; 9141 9142 cpu-critical { 9143 temperature = <110000>; 9144 hysteresis = <1000>; 9145 type = "critical"; 9146 }; 9147 }; 9148 }; 9149 9150 cpu2-2-top-thermal { 9151 polling-delay-passive = <250>; 9152 9153 thermal-sensors = <&tsens2 5>; 9154 9155 trips { 9156 trip-point0 { 9157 temperature = <90000>; 9158 hysteresis = <2000>; 9159 type = "passive"; 9160 }; 9161 9162 trip-point1 { 9163 temperature = <95000>; 9164 hysteresis = <2000>; 9165 type = "passive"; 9166 }; 9167 9168 cpu-critical { 9169 temperature = <110000>; 9170 hysteresis = <1000>; 9171 type = "critical"; 9172 }; 9173 }; 9174 }; 9175 9176 cpu2-2-btm-thermal { 9177 polling-delay-passive = <250>; 9178 9179 thermal-sensors = <&tsens2 6>; 9180 9181 trips { 9182 trip-point0 { 9183 temperature = <90000>; 9184 hysteresis = <2000>; 9185 type = "passive"; 9186 }; 9187 9188 trip-point1 { 9189 temperature = <95000>; 9190 hysteresis = <2000>; 9191 type = "passive"; 9192 }; 9193 9194 cpu-critical { 9195 temperature = <110000>; 9196 hysteresis = <1000>; 9197 type = "critical"; 9198 }; 9199 }; 9200 }; 9201 9202 cpu2-3-top-thermal { 9203 polling-delay-passive = <250>; 9204 9205 thermal-sensors = <&tsens2 7>; 9206 9207 trips { 9208 trip-point0 { 9209 temperature = <90000>; 9210 hysteresis = <2000>; 9211 type = "passive"; 9212 }; 9213 9214 trip-point1 { 9215 temperature = <95000>; 9216 hysteresis = <2000>; 9217 type = "passive"; 9218 }; 9219 9220 cpu-critical { 9221 temperature = <110000>; 9222 hysteresis = <1000>; 9223 type = "critical"; 9224 }; 9225 }; 9226 }; 9227 9228 cpu2-3-btm-thermal { 9229 polling-delay-passive = <250>; 9230 9231 thermal-sensors = <&tsens2 8>; 9232 9233 trips { 9234 trip-point0 { 9235 temperature = <90000>; 9236 hysteresis = <2000>; 9237 type = "passive"; 9238 }; 9239 9240 trip-point1 { 9241 temperature = <95000>; 9242 hysteresis = <2000>; 9243 type = "passive"; 9244 }; 9245 9246 cpu-critical { 9247 temperature = <110000>; 9248 hysteresis = <1000>; 9249 type = "critical"; 9250 }; 9251 }; 9252 }; 9253 9254 cpuss2-top-thermal { 9255 thermal-sensors = <&tsens2 9>; 9256 9257 trips { 9258 trip-point0 { 9259 temperature = <90000>; 9260 hysteresis = <2000>; 9261 type = "hot"; 9262 }; 9263 9264 cpuss2-critical { 9265 temperature = <125000>; 9266 hysteresis = <0>; 9267 type = "critical"; 9268 }; 9269 }; 9270 }; 9271 9272 cpuss2-btm-thermal { 9273 thermal-sensors = <&tsens2 10>; 9274 9275 trips { 9276 trip-point0 { 9277 temperature = <90000>; 9278 hysteresis = <2000>; 9279 type = "hot"; 9280 }; 9281 9282 cpuss2-critical { 9283 temperature = <125000>; 9284 hysteresis = <0>; 9285 type = "critical"; 9286 }; 9287 }; 9288 }; 9289 9290 aoss3-thermal { 9291 thermal-sensors = <&tsens3 0>; 9292 9293 trips { 9294 trip-point0 { 9295 temperature = <90000>; 9296 hysteresis = <2000>; 9297 type = "hot"; 9298 }; 9299 9300 aoss0-critical { 9301 temperature = <125000>; 9302 hysteresis = <0>; 9303 type = "critical"; 9304 }; 9305 }; 9306 }; 9307 9308 nsp0-thermal { 9309 thermal-sensors = <&tsens3 1>; 9310 9311 trips { 9312 trip-point0 { 9313 temperature = <90000>; 9314 hysteresis = <2000>; 9315 type = "hot"; 9316 }; 9317 9318 nsp0-critical { 9319 temperature = <125000>; 9320 hysteresis = <0>; 9321 type = "critical"; 9322 }; 9323 }; 9324 }; 9325 9326 nsp1-thermal { 9327 thermal-sensors = <&tsens3 2>; 9328 9329 trips { 9330 trip-point0 { 9331 temperature = <90000>; 9332 hysteresis = <2000>; 9333 type = "hot"; 9334 }; 9335 9336 nsp1-critical { 9337 temperature = <125000>; 9338 hysteresis = <0>; 9339 type = "critical"; 9340 }; 9341 }; 9342 }; 9343 9344 nsp2-thermal { 9345 thermal-sensors = <&tsens3 3>; 9346 9347 trips { 9348 trip-point0 { 9349 temperature = <90000>; 9350 hysteresis = <2000>; 9351 type = "hot"; 9352 }; 9353 9354 nsp2-critical { 9355 temperature = <125000>; 9356 hysteresis = <0>; 9357 type = "critical"; 9358 }; 9359 }; 9360 }; 9361 9362 nsp3-thermal { 9363 thermal-sensors = <&tsens3 4>; 9364 9365 trips { 9366 trip-point0 { 9367 temperature = <90000>; 9368 hysteresis = <2000>; 9369 type = "hot"; 9370 }; 9371 9372 nsp3-critical { 9373 temperature = <125000>; 9374 hysteresis = <0>; 9375 type = "critical"; 9376 }; 9377 }; 9378 }; 9379 9380 gpuss-0-thermal { 9381 polling-delay-passive = <10>; 9382 9383 thermal-sensors = <&tsens3 5>; 9384 9385 trips { 9386 trip-point0 { 9387 temperature = <85000>; 9388 hysteresis = <1000>; 9389 type = "passive"; 9390 }; 9391 9392 trip-point1 { 9393 temperature = <90000>; 9394 hysteresis = <1000>; 9395 type = "hot"; 9396 }; 9397 9398 trip-point2 { 9399 temperature = <125000>; 9400 hysteresis = <1000>; 9401 type = "critical"; 9402 }; 9403 }; 9404 }; 9405 9406 gpuss-1-thermal { 9407 polling-delay-passive = <10>; 9408 9409 thermal-sensors = <&tsens3 6>; 9410 9411 trips { 9412 trip-point0 { 9413 temperature = <85000>; 9414 hysteresis = <1000>; 9415 type = "passive"; 9416 }; 9417 9418 trip-point1 { 9419 temperature = <90000>; 9420 hysteresis = <1000>; 9421 type = "hot"; 9422 }; 9423 9424 trip-point2 { 9425 temperature = <125000>; 9426 hysteresis = <1000>; 9427 type = "critical"; 9428 }; 9429 }; 9430 }; 9431 9432 gpuss-2-thermal { 9433 polling-delay-passive = <10>; 9434 9435 thermal-sensors = <&tsens3 7>; 9436 9437 trips { 9438 trip-point0 { 9439 temperature = <85000>; 9440 hysteresis = <1000>; 9441 type = "passive"; 9442 }; 9443 9444 trip-point1 { 9445 temperature = <90000>; 9446 hysteresis = <1000>; 9447 type = "hot"; 9448 }; 9449 9450 trip-point2 { 9451 temperature = <125000>; 9452 hysteresis = <1000>; 9453 type = "critical"; 9454 }; 9455 }; 9456 }; 9457 9458 gpuss-3-thermal { 9459 polling-delay-passive = <10>; 9460 9461 thermal-sensors = <&tsens3 8>; 9462 9463 trips { 9464 trip-point0 { 9465 temperature = <85000>; 9466 hysteresis = <1000>; 9467 type = "passive"; 9468 }; 9469 9470 trip-point1 { 9471 temperature = <90000>; 9472 hysteresis = <1000>; 9473 type = "hot"; 9474 }; 9475 9476 trip-point2 { 9477 temperature = <125000>; 9478 hysteresis = <1000>; 9479 type = "critical"; 9480 }; 9481 }; 9482 }; 9483 9484 gpuss-4-thermal { 9485 polling-delay-passive = <10>; 9486 9487 thermal-sensors = <&tsens3 9>; 9488 9489 trips { 9490 trip-point0 { 9491 temperature = <85000>; 9492 hysteresis = <1000>; 9493 type = "passive"; 9494 }; 9495 9496 trip-point1 { 9497 temperature = <90000>; 9498 hysteresis = <1000>; 9499 type = "hot"; 9500 }; 9501 9502 trip-point2 { 9503 temperature = <125000>; 9504 hysteresis = <1000>; 9505 type = "critical"; 9506 }; 9507 }; 9508 }; 9509 9510 gpuss-5-thermal { 9511 polling-delay-passive = <10>; 9512 9513 thermal-sensors = <&tsens3 10>; 9514 9515 trips { 9516 trip-point0 { 9517 temperature = <85000>; 9518 hysteresis = <1000>; 9519 type = "passive"; 9520 }; 9521 9522 trip-point1 { 9523 temperature = <90000>; 9524 hysteresis = <1000>; 9525 type = "hot"; 9526 }; 9527 9528 trip-point2 { 9529 temperature = <125000>; 9530 hysteresis = <1000>; 9531 type = "critical"; 9532 }; 9533 }; 9534 }; 9535 9536 gpuss-6-thermal { 9537 polling-delay-passive = <10>; 9538 9539 thermal-sensors = <&tsens3 11>; 9540 9541 trips { 9542 trip-point0 { 9543 temperature = <85000>; 9544 hysteresis = <1000>; 9545 type = "passive"; 9546 }; 9547 9548 trip-point1 { 9549 temperature = <90000>; 9550 hysteresis = <1000>; 9551 type = "hot"; 9552 }; 9553 9554 trip-point2 { 9555 temperature = <125000>; 9556 hysteresis = <1000>; 9557 type = "critical"; 9558 }; 9559 }; 9560 }; 9561 9562 gpuss-7-thermal { 9563 polling-delay-passive = <10>; 9564 9565 thermal-sensors = <&tsens3 12>; 9566 9567 trips { 9568 trip-point0 { 9569 temperature = <85000>; 9570 hysteresis = <1000>; 9571 type = "passive"; 9572 }; 9573 9574 trip-point1 { 9575 temperature = <90000>; 9576 hysteresis = <1000>; 9577 type = "hot"; 9578 }; 9579 9580 trip-point2 { 9581 temperature = <125000>; 9582 hysteresis = <1000>; 9583 type = "critical"; 9584 }; 9585 }; 9586 }; 9587 9588 camera0-thermal { 9589 thermal-sensors = <&tsens3 13>; 9590 9591 trips { 9592 trip-point0 { 9593 temperature = <90000>; 9594 hysteresis = <2000>; 9595 type = "hot"; 9596 }; 9597 9598 camera0-critical { 9599 temperature = <115000>; 9600 hysteresis = <0>; 9601 type = "critical"; 9602 }; 9603 }; 9604 }; 9605 9606 camera1-thermal { 9607 thermal-sensors = <&tsens3 14>; 9608 9609 trips { 9610 trip-point0 { 9611 temperature = <90000>; 9612 hysteresis = <2000>; 9613 type = "hot"; 9614 }; 9615 9616 camera0-critical { 9617 temperature = <115000>; 9618 hysteresis = <0>; 9619 type = "critical"; 9620 }; 9621 }; 9622 }; 9623 }; 9624}; 9625