1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * ARMv7 Cortex-A8 and Cortex-A9 Performance Events handling code. 4 * 5 * ARMv7 support: Jean Pihet <jpihet@mvista.com> 6 * 2010 (c) MontaVista Software, LLC. 7 * 8 * Copied from ARMv6 code, with the low level code inspired 9 * by the ARMv7 Oprofile code. 10 * 11 * Cortex-A8 has up to 4 configurable performance counters and 12 * a single cycle counter. 13 * Cortex-A9 has up to 31 configurable performance counters and 14 * a single cycle counter. 15 * 16 * All counters can be enabled/disabled and IRQ masked separately. The cycle 17 * counter and all 4 performance counters together can be reset separately. 18 */ 19 20 #include <asm/cp15.h> 21 #include <asm/cputype.h> 22 #include <asm/irq_regs.h> 23 #include <asm/vfp.h> 24 #include "../vfp/vfpinstr.h" 25 26 #include <linux/of.h> 27 #include <linux/perf/arm_pmu.h> 28 #include <linux/platform_device.h> 29 30 /* 31 * Common ARMv7 event types 32 * 33 * Note: An implementation may not be able to count all of these events 34 * but the encodings are considered to be `reserved' in the case that 35 * they are not available. 36 */ 37 #define ARMV7_PERFCTR_PMNC_SW_INCR 0x00 38 #define ARMV7_PERFCTR_L1_ICACHE_REFILL 0x01 39 #define ARMV7_PERFCTR_ITLB_REFILL 0x02 40 #define ARMV7_PERFCTR_L1_DCACHE_REFILL 0x03 41 #define ARMV7_PERFCTR_L1_DCACHE_ACCESS 0x04 42 #define ARMV7_PERFCTR_DTLB_REFILL 0x05 43 #define ARMV7_PERFCTR_MEM_READ 0x06 44 #define ARMV7_PERFCTR_MEM_WRITE 0x07 45 #define ARMV7_PERFCTR_INSTR_EXECUTED 0x08 46 #define ARMV7_PERFCTR_EXC_TAKEN 0x09 47 #define ARMV7_PERFCTR_EXC_EXECUTED 0x0A 48 #define ARMV7_PERFCTR_CID_WRITE 0x0B 49 50 /* 51 * ARMV7_PERFCTR_PC_WRITE is equivalent to HW_BRANCH_INSTRUCTIONS. 52 * It counts: 53 * - all (taken) branch instructions, 54 * - instructions that explicitly write the PC, 55 * - exception generating instructions. 56 */ 57 #define ARMV7_PERFCTR_PC_WRITE 0x0C 58 #define ARMV7_PERFCTR_PC_IMM_BRANCH 0x0D 59 #define ARMV7_PERFCTR_PC_PROC_RETURN 0x0E 60 #define ARMV7_PERFCTR_MEM_UNALIGNED_ACCESS 0x0F 61 #define ARMV7_PERFCTR_PC_BRANCH_MIS_PRED 0x10 62 #define ARMV7_PERFCTR_CLOCK_CYCLES 0x11 63 #define ARMV7_PERFCTR_PC_BRANCH_PRED 0x12 64 65 /* These events are defined by the PMUv2 supplement (ARM DDI 0457A). */ 66 #define ARMV7_PERFCTR_MEM_ACCESS 0x13 67 #define ARMV7_PERFCTR_L1_ICACHE_ACCESS 0x14 68 #define ARMV7_PERFCTR_L1_DCACHE_WB 0x15 69 #define ARMV7_PERFCTR_L2_CACHE_ACCESS 0x16 70 #define ARMV7_PERFCTR_L2_CACHE_REFILL 0x17 71 #define ARMV7_PERFCTR_L2_CACHE_WB 0x18 72 #define ARMV7_PERFCTR_BUS_ACCESS 0x19 73 #define ARMV7_PERFCTR_MEM_ERROR 0x1A 74 #define ARMV7_PERFCTR_INSTR_SPEC 0x1B 75 #define ARMV7_PERFCTR_TTBR_WRITE 0x1C 76 #define ARMV7_PERFCTR_BUS_CYCLES 0x1D 77 78 #define ARMV7_PERFCTR_CPU_CYCLES 0xFF 79 80 /* ARMv7 Cortex-A8 specific event types */ 81 #define ARMV7_A8_PERFCTR_L2_CACHE_ACCESS 0x43 82 #define ARMV7_A8_PERFCTR_L2_CACHE_REFILL 0x44 83 #define ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS 0x50 84 #define ARMV7_A8_PERFCTR_STALL_ISIDE 0x56 85 86 /* ARMv7 Cortex-A9 specific event types */ 87 #define ARMV7_A9_PERFCTR_INSTR_CORE_RENAME 0x68 88 #define ARMV7_A9_PERFCTR_STALL_ICACHE 0x60 89 #define ARMV7_A9_PERFCTR_STALL_DISPATCH 0x66 90 91 /* ARMv7 Cortex-A5 specific event types */ 92 #define ARMV7_A5_PERFCTR_PREFETCH_LINEFILL 0xc2 93 #define ARMV7_A5_PERFCTR_PREFETCH_LINEFILL_DROP 0xc3 94 95 /* ARMv7 Cortex-A15 specific event types */ 96 #define ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_READ 0x40 97 #define ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_WRITE 0x41 98 #define ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_READ 0x42 99 #define ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_WRITE 0x43 100 101 #define ARMV7_A15_PERFCTR_DTLB_REFILL_L1_READ 0x4C 102 #define ARMV7_A15_PERFCTR_DTLB_REFILL_L1_WRITE 0x4D 103 104 #define ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_READ 0x50 105 #define ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_WRITE 0x51 106 #define ARMV7_A15_PERFCTR_L2_CACHE_REFILL_READ 0x52 107 #define ARMV7_A15_PERFCTR_L2_CACHE_REFILL_WRITE 0x53 108 109 #define ARMV7_A15_PERFCTR_PC_WRITE_SPEC 0x76 110 111 /* ARMv7 Cortex-A12 specific event types */ 112 #define ARMV7_A12_PERFCTR_L1_DCACHE_ACCESS_READ 0x40 113 #define ARMV7_A12_PERFCTR_L1_DCACHE_ACCESS_WRITE 0x41 114 115 #define ARMV7_A12_PERFCTR_L2_CACHE_ACCESS_READ 0x50 116 #define ARMV7_A12_PERFCTR_L2_CACHE_ACCESS_WRITE 0x51 117 118 #define ARMV7_A12_PERFCTR_PC_WRITE_SPEC 0x76 119 120 #define ARMV7_A12_PERFCTR_PF_TLB_REFILL 0xe7 121 122 /* ARMv7 Krait specific event types */ 123 #define KRAIT_PMRESR0_GROUP0 0xcc 124 #define KRAIT_PMRESR1_GROUP0 0xd0 125 #define KRAIT_PMRESR2_GROUP0 0xd4 126 #define KRAIT_VPMRESR0_GROUP0 0xd8 127 128 #define KRAIT_PERFCTR_L1_ICACHE_ACCESS 0x10011 129 #define KRAIT_PERFCTR_L1_ICACHE_MISS 0x10010 130 131 #define KRAIT_PERFCTR_L1_ITLB_ACCESS 0x12222 132 #define KRAIT_PERFCTR_L1_DTLB_ACCESS 0x12210 133 134 /* ARMv7 Scorpion specific event types */ 135 #define SCORPION_LPM0_GROUP0 0x4c 136 #define SCORPION_LPM1_GROUP0 0x50 137 #define SCORPION_LPM2_GROUP0 0x54 138 #define SCORPION_L2LPM_GROUP0 0x58 139 #define SCORPION_VLPM_GROUP0 0x5c 140 141 #define SCORPION_ICACHE_ACCESS 0x10053 142 #define SCORPION_ICACHE_MISS 0x10052 143 144 #define SCORPION_DTLB_ACCESS 0x12013 145 #define SCORPION_DTLB_MISS 0x12012 146 147 #define SCORPION_ITLB_MISS 0x12021 148 149 /* 150 * Cortex-A8 HW events mapping 151 * 152 * The hardware events that we support. We do support cache operations but 153 * we have harvard caches and no way to combine instruction and data 154 * accesses/misses in hardware. 155 */ 156 static const unsigned armv7_a8_perf_map[PERF_COUNT_HW_MAX] = { 157 PERF_MAP_ALL_UNSUPPORTED, 158 [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, 159 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED, 160 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 161 [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 162 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE, 163 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 164 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV7_A8_PERFCTR_STALL_ISIDE, 165 }; 166 167 static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 168 [PERF_COUNT_HW_CACHE_OP_MAX] 169 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 170 PERF_CACHE_MAP_ALL_UNSUPPORTED, 171 172 /* 173 * The performance counters don't differentiate between read and write 174 * accesses/misses so this isn't strictly correct, but it's the best we 175 * can do. Writes and reads get combined. 176 */ 177 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 178 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 179 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 180 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 181 182 [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS, 183 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, 184 185 [C(LL)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L2_CACHE_ACCESS, 186 [C(LL)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_A8_PERFCTR_L2_CACHE_REFILL, 187 [C(LL)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L2_CACHE_ACCESS, 188 [C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_A8_PERFCTR_L2_CACHE_REFILL, 189 190 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, 191 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, 192 193 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL, 194 [C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL, 195 196 [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, 197 [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 198 [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, 199 [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 200 }; 201 202 /* 203 * Cortex-A9 HW events mapping 204 */ 205 static const unsigned armv7_a9_perf_map[PERF_COUNT_HW_MAX] = { 206 PERF_MAP_ALL_UNSUPPORTED, 207 [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, 208 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_A9_PERFCTR_INSTR_CORE_RENAME, 209 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 210 [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 211 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE, 212 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 213 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV7_A9_PERFCTR_STALL_ICACHE, 214 [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = ARMV7_A9_PERFCTR_STALL_DISPATCH, 215 }; 216 217 static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 218 [PERF_COUNT_HW_CACHE_OP_MAX] 219 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 220 PERF_CACHE_MAP_ALL_UNSUPPORTED, 221 222 /* 223 * The performance counters don't differentiate between read and write 224 * accesses/misses so this isn't strictly correct, but it's the best we 225 * can do. Writes and reads get combined. 226 */ 227 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 228 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 229 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 230 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 231 232 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, 233 234 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, 235 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, 236 237 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL, 238 [C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL, 239 240 [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, 241 [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 242 [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, 243 [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 244 }; 245 246 /* 247 * Cortex-A5 HW events mapping 248 */ 249 static const unsigned armv7_a5_perf_map[PERF_COUNT_HW_MAX] = { 250 PERF_MAP_ALL_UNSUPPORTED, 251 [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, 252 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED, 253 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 254 [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 255 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE, 256 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 257 }; 258 259 static const unsigned armv7_a5_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 260 [PERF_COUNT_HW_CACHE_OP_MAX] 261 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 262 PERF_CACHE_MAP_ALL_UNSUPPORTED, 263 264 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 265 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 266 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 267 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 268 [C(L1D)][C(OP_PREFETCH)][C(RESULT_ACCESS)] = ARMV7_A5_PERFCTR_PREFETCH_LINEFILL, 269 [C(L1D)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV7_A5_PERFCTR_PREFETCH_LINEFILL_DROP, 270 271 [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS, 272 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, 273 /* 274 * The prefetch counters don't differentiate between the I side and the 275 * D side. 276 */ 277 [C(L1I)][C(OP_PREFETCH)][C(RESULT_ACCESS)] = ARMV7_A5_PERFCTR_PREFETCH_LINEFILL, 278 [C(L1I)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV7_A5_PERFCTR_PREFETCH_LINEFILL_DROP, 279 280 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, 281 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, 282 283 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL, 284 [C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL, 285 286 [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, 287 [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 288 [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, 289 [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 290 }; 291 292 /* 293 * Cortex-A15 HW events mapping 294 */ 295 static const unsigned armv7_a15_perf_map[PERF_COUNT_HW_MAX] = { 296 PERF_MAP_ALL_UNSUPPORTED, 297 [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, 298 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED, 299 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 300 [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 301 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_A15_PERFCTR_PC_WRITE_SPEC, 302 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 303 [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_BUS_CYCLES, 304 }; 305 306 static const unsigned armv7_a15_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 307 [PERF_COUNT_HW_CACHE_OP_MAX] 308 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 309 PERF_CACHE_MAP_ALL_UNSUPPORTED, 310 311 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_READ, 312 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_READ, 313 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_WRITE, 314 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_WRITE, 315 316 /* 317 * Not all performance counters differentiate between read and write 318 * accesses/misses so we're not always strictly correct, but it's the 319 * best we can do. Writes and reads get combined in these cases. 320 */ 321 [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS, 322 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, 323 324 [C(LL)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_READ, 325 [C(LL)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_A15_PERFCTR_L2_CACHE_REFILL_READ, 326 [C(LL)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_WRITE, 327 [C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_A15_PERFCTR_L2_CACHE_REFILL_WRITE, 328 329 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_A15_PERFCTR_DTLB_REFILL_L1_READ, 330 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_A15_PERFCTR_DTLB_REFILL_L1_WRITE, 331 332 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL, 333 [C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL, 334 335 [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, 336 [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 337 [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, 338 [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 339 }; 340 341 /* 342 * Cortex-A7 HW events mapping 343 */ 344 static const unsigned armv7_a7_perf_map[PERF_COUNT_HW_MAX] = { 345 PERF_MAP_ALL_UNSUPPORTED, 346 [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, 347 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED, 348 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 349 [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 350 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE, 351 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 352 [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_BUS_CYCLES, 353 }; 354 355 static const unsigned armv7_a7_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 356 [PERF_COUNT_HW_CACHE_OP_MAX] 357 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 358 PERF_CACHE_MAP_ALL_UNSUPPORTED, 359 360 /* 361 * The performance counters don't differentiate between read and write 362 * accesses/misses so this isn't strictly correct, but it's the best we 363 * can do. Writes and reads get combined. 364 */ 365 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 366 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 367 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 368 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 369 370 [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS, 371 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, 372 373 [C(LL)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L2_CACHE_ACCESS, 374 [C(LL)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L2_CACHE_REFILL, 375 [C(LL)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L2_CACHE_ACCESS, 376 [C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L2_CACHE_REFILL, 377 378 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, 379 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, 380 381 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL, 382 [C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL, 383 384 [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, 385 [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 386 [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, 387 [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 388 }; 389 390 /* 391 * Cortex-A12 HW events mapping 392 */ 393 static const unsigned armv7_a12_perf_map[PERF_COUNT_HW_MAX] = { 394 PERF_MAP_ALL_UNSUPPORTED, 395 [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, 396 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED, 397 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 398 [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 399 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_A12_PERFCTR_PC_WRITE_SPEC, 400 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 401 [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_BUS_CYCLES, 402 }; 403 404 static const unsigned armv7_a12_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 405 [PERF_COUNT_HW_CACHE_OP_MAX] 406 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 407 PERF_CACHE_MAP_ALL_UNSUPPORTED, 408 409 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_A12_PERFCTR_L1_DCACHE_ACCESS_READ, 410 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 411 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_A12_PERFCTR_L1_DCACHE_ACCESS_WRITE, 412 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 413 414 /* 415 * Not all performance counters differentiate between read and write 416 * accesses/misses so we're not always strictly correct, but it's the 417 * best we can do. Writes and reads get combined in these cases. 418 */ 419 [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS, 420 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, 421 422 [C(LL)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_A12_PERFCTR_L2_CACHE_ACCESS_READ, 423 [C(LL)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L2_CACHE_REFILL, 424 [C(LL)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_A12_PERFCTR_L2_CACHE_ACCESS_WRITE, 425 [C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L2_CACHE_REFILL, 426 427 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, 428 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, 429 [C(DTLB)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV7_A12_PERFCTR_PF_TLB_REFILL, 430 431 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL, 432 [C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL, 433 434 [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, 435 [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 436 [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, 437 [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 438 }; 439 440 /* 441 * Krait HW events mapping 442 */ 443 static const unsigned krait_perf_map[PERF_COUNT_HW_MAX] = { 444 PERF_MAP_ALL_UNSUPPORTED, 445 [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, 446 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED, 447 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE, 448 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 449 [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_CLOCK_CYCLES, 450 }; 451 452 static const unsigned krait_perf_map_no_branch[PERF_COUNT_HW_MAX] = { 453 PERF_MAP_ALL_UNSUPPORTED, 454 [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, 455 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED, 456 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 457 [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_CLOCK_CYCLES, 458 }; 459 460 static const unsigned krait_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 461 [PERF_COUNT_HW_CACHE_OP_MAX] 462 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 463 PERF_CACHE_MAP_ALL_UNSUPPORTED, 464 465 /* 466 * The performance counters don't differentiate between read and write 467 * accesses/misses so this isn't strictly correct, but it's the best we 468 * can do. Writes and reads get combined. 469 */ 470 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 471 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 472 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 473 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 474 475 [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = KRAIT_PERFCTR_L1_ICACHE_ACCESS, 476 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = KRAIT_PERFCTR_L1_ICACHE_MISS, 477 478 [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = KRAIT_PERFCTR_L1_DTLB_ACCESS, 479 [C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = KRAIT_PERFCTR_L1_DTLB_ACCESS, 480 481 [C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = KRAIT_PERFCTR_L1_ITLB_ACCESS, 482 [C(ITLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = KRAIT_PERFCTR_L1_ITLB_ACCESS, 483 484 [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, 485 [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 486 [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, 487 [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 488 }; 489 490 /* 491 * Scorpion HW events mapping 492 */ 493 static const unsigned scorpion_perf_map[PERF_COUNT_HW_MAX] = { 494 PERF_MAP_ALL_UNSUPPORTED, 495 [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, 496 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED, 497 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE, 498 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 499 [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_CLOCK_CYCLES, 500 }; 501 502 static const unsigned scorpion_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 503 [PERF_COUNT_HW_CACHE_OP_MAX] 504 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 505 PERF_CACHE_MAP_ALL_UNSUPPORTED, 506 /* 507 * The performance counters don't differentiate between read and write 508 * accesses/misses so this isn't strictly correct, but it's the best we 509 * can do. Writes and reads get combined. 510 */ 511 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 512 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 513 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 514 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 515 [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = SCORPION_ICACHE_ACCESS, 516 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = SCORPION_ICACHE_MISS, 517 /* 518 * Only ITLB misses and DTLB refills are supported. If users want the 519 * DTLB refills misses a raw counter must be used. 520 */ 521 [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = SCORPION_DTLB_ACCESS, 522 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = SCORPION_DTLB_MISS, 523 [C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = SCORPION_DTLB_ACCESS, 524 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = SCORPION_DTLB_MISS, 525 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = SCORPION_ITLB_MISS, 526 [C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = SCORPION_ITLB_MISS, 527 [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, 528 [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 529 [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, 530 [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 531 }; 532 533 PMU_FORMAT_ATTR(event, "config:0-7"); 534 535 static struct attribute *armv7_pmu_format_attrs[] = { 536 &format_attr_event.attr, 537 NULL, 538 }; 539 540 static struct attribute_group armv7_pmu_format_attr_group = { 541 .name = "format", 542 .attrs = armv7_pmu_format_attrs, 543 }; 544 545 #define ARMV7_EVENT_ATTR_RESOLVE(m) #m 546 #define ARMV7_EVENT_ATTR(name, config) \ 547 PMU_EVENT_ATTR_STRING(name, armv7_event_attr_##name, \ 548 "event=" ARMV7_EVENT_ATTR_RESOLVE(config)) 549 550 ARMV7_EVENT_ATTR(sw_incr, ARMV7_PERFCTR_PMNC_SW_INCR); 551 ARMV7_EVENT_ATTR(l1i_cache_refill, ARMV7_PERFCTR_L1_ICACHE_REFILL); 552 ARMV7_EVENT_ATTR(l1i_tlb_refill, ARMV7_PERFCTR_ITLB_REFILL); 553 ARMV7_EVENT_ATTR(l1d_cache_refill, ARMV7_PERFCTR_L1_DCACHE_REFILL); 554 ARMV7_EVENT_ATTR(l1d_cache, ARMV7_PERFCTR_L1_DCACHE_ACCESS); 555 ARMV7_EVENT_ATTR(l1d_tlb_refill, ARMV7_PERFCTR_DTLB_REFILL); 556 ARMV7_EVENT_ATTR(ld_retired, ARMV7_PERFCTR_MEM_READ); 557 ARMV7_EVENT_ATTR(st_retired, ARMV7_PERFCTR_MEM_WRITE); 558 ARMV7_EVENT_ATTR(inst_retired, ARMV7_PERFCTR_INSTR_EXECUTED); 559 ARMV7_EVENT_ATTR(exc_taken, ARMV7_PERFCTR_EXC_TAKEN); 560 ARMV7_EVENT_ATTR(exc_return, ARMV7_PERFCTR_EXC_EXECUTED); 561 ARMV7_EVENT_ATTR(cid_write_retired, ARMV7_PERFCTR_CID_WRITE); 562 ARMV7_EVENT_ATTR(pc_write_retired, ARMV7_PERFCTR_PC_WRITE); 563 ARMV7_EVENT_ATTR(br_immed_retired, ARMV7_PERFCTR_PC_IMM_BRANCH); 564 ARMV7_EVENT_ATTR(br_return_retired, ARMV7_PERFCTR_PC_PROC_RETURN); 565 ARMV7_EVENT_ATTR(unaligned_ldst_retired, ARMV7_PERFCTR_MEM_UNALIGNED_ACCESS); 566 ARMV7_EVENT_ATTR(br_mis_pred, ARMV7_PERFCTR_PC_BRANCH_MIS_PRED); 567 ARMV7_EVENT_ATTR(cpu_cycles, ARMV7_PERFCTR_CLOCK_CYCLES); 568 ARMV7_EVENT_ATTR(br_pred, ARMV7_PERFCTR_PC_BRANCH_PRED); 569 570 static struct attribute *armv7_pmuv1_event_attrs[] = { 571 &armv7_event_attr_sw_incr.attr.attr, 572 &armv7_event_attr_l1i_cache_refill.attr.attr, 573 &armv7_event_attr_l1i_tlb_refill.attr.attr, 574 &armv7_event_attr_l1d_cache_refill.attr.attr, 575 &armv7_event_attr_l1d_cache.attr.attr, 576 &armv7_event_attr_l1d_tlb_refill.attr.attr, 577 &armv7_event_attr_ld_retired.attr.attr, 578 &armv7_event_attr_st_retired.attr.attr, 579 &armv7_event_attr_inst_retired.attr.attr, 580 &armv7_event_attr_exc_taken.attr.attr, 581 &armv7_event_attr_exc_return.attr.attr, 582 &armv7_event_attr_cid_write_retired.attr.attr, 583 &armv7_event_attr_pc_write_retired.attr.attr, 584 &armv7_event_attr_br_immed_retired.attr.attr, 585 &armv7_event_attr_br_return_retired.attr.attr, 586 &armv7_event_attr_unaligned_ldst_retired.attr.attr, 587 &armv7_event_attr_br_mis_pred.attr.attr, 588 &armv7_event_attr_cpu_cycles.attr.attr, 589 &armv7_event_attr_br_pred.attr.attr, 590 NULL, 591 }; 592 593 static struct attribute_group armv7_pmuv1_events_attr_group = { 594 .name = "events", 595 .attrs = armv7_pmuv1_event_attrs, 596 }; 597 598 ARMV7_EVENT_ATTR(mem_access, ARMV7_PERFCTR_MEM_ACCESS); 599 ARMV7_EVENT_ATTR(l1i_cache, ARMV7_PERFCTR_L1_ICACHE_ACCESS); 600 ARMV7_EVENT_ATTR(l1d_cache_wb, ARMV7_PERFCTR_L1_DCACHE_WB); 601 ARMV7_EVENT_ATTR(l2d_cache, ARMV7_PERFCTR_L2_CACHE_ACCESS); 602 ARMV7_EVENT_ATTR(l2d_cache_refill, ARMV7_PERFCTR_L2_CACHE_REFILL); 603 ARMV7_EVENT_ATTR(l2d_cache_wb, ARMV7_PERFCTR_L2_CACHE_WB); 604 ARMV7_EVENT_ATTR(bus_access, ARMV7_PERFCTR_BUS_ACCESS); 605 ARMV7_EVENT_ATTR(memory_error, ARMV7_PERFCTR_MEM_ERROR); 606 ARMV7_EVENT_ATTR(inst_spec, ARMV7_PERFCTR_INSTR_SPEC); 607 ARMV7_EVENT_ATTR(ttbr_write_retired, ARMV7_PERFCTR_TTBR_WRITE); 608 ARMV7_EVENT_ATTR(bus_cycles, ARMV7_PERFCTR_BUS_CYCLES); 609 610 static struct attribute *armv7_pmuv2_event_attrs[] = { 611 &armv7_event_attr_sw_incr.attr.attr, 612 &armv7_event_attr_l1i_cache_refill.attr.attr, 613 &armv7_event_attr_l1i_tlb_refill.attr.attr, 614 &armv7_event_attr_l1d_cache_refill.attr.attr, 615 &armv7_event_attr_l1d_cache.attr.attr, 616 &armv7_event_attr_l1d_tlb_refill.attr.attr, 617 &armv7_event_attr_ld_retired.attr.attr, 618 &armv7_event_attr_st_retired.attr.attr, 619 &armv7_event_attr_inst_retired.attr.attr, 620 &armv7_event_attr_exc_taken.attr.attr, 621 &armv7_event_attr_exc_return.attr.attr, 622 &armv7_event_attr_cid_write_retired.attr.attr, 623 &armv7_event_attr_pc_write_retired.attr.attr, 624 &armv7_event_attr_br_immed_retired.attr.attr, 625 &armv7_event_attr_br_return_retired.attr.attr, 626 &armv7_event_attr_unaligned_ldst_retired.attr.attr, 627 &armv7_event_attr_br_mis_pred.attr.attr, 628 &armv7_event_attr_cpu_cycles.attr.attr, 629 &armv7_event_attr_br_pred.attr.attr, 630 &armv7_event_attr_mem_access.attr.attr, 631 &armv7_event_attr_l1i_cache.attr.attr, 632 &armv7_event_attr_l1d_cache_wb.attr.attr, 633 &armv7_event_attr_l2d_cache.attr.attr, 634 &armv7_event_attr_l2d_cache_refill.attr.attr, 635 &armv7_event_attr_l2d_cache_wb.attr.attr, 636 &armv7_event_attr_bus_access.attr.attr, 637 &armv7_event_attr_memory_error.attr.attr, 638 &armv7_event_attr_inst_spec.attr.attr, 639 &armv7_event_attr_ttbr_write_retired.attr.attr, 640 &armv7_event_attr_bus_cycles.attr.attr, 641 NULL, 642 }; 643 644 static struct attribute_group armv7_pmuv2_events_attr_group = { 645 .name = "events", 646 .attrs = armv7_pmuv2_event_attrs, 647 }; 648 649 /* 650 * Perf Events' indices 651 */ 652 #define ARMV7_IDX_CYCLE_COUNTER 0 653 #define ARMV7_IDX_COUNTER0 1 654 #define ARMV7_IDX_COUNTER_LAST(cpu_pmu) \ 655 (ARMV7_IDX_CYCLE_COUNTER + cpu_pmu->num_events - 1) 656 657 #define ARMV7_MAX_COUNTERS 32 658 #define ARMV7_COUNTER_MASK (ARMV7_MAX_COUNTERS - 1) 659 660 /* 661 * ARMv7 low level PMNC access 662 */ 663 664 /* 665 * Perf Event to low level counters mapping 666 */ 667 #define ARMV7_IDX_TO_COUNTER(x) \ 668 (((x) - ARMV7_IDX_COUNTER0) & ARMV7_COUNTER_MASK) 669 670 /* 671 * Per-CPU PMNC: config reg 672 */ 673 #define ARMV7_PMNC_E (1 << 0) /* Enable all counters */ 674 #define ARMV7_PMNC_P (1 << 1) /* Reset all counters */ 675 #define ARMV7_PMNC_C (1 << 2) /* Cycle counter reset */ 676 #define ARMV7_PMNC_D (1 << 3) /* CCNT counts every 64th cpu cycle */ 677 #define ARMV7_PMNC_X (1 << 4) /* Export to ETM */ 678 #define ARMV7_PMNC_DP (1 << 5) /* Disable CCNT if non-invasive debug*/ 679 #define ARMV7_PMNC_N_SHIFT 11 /* Number of counters supported */ 680 #define ARMV7_PMNC_N_MASK 0x1f 681 #define ARMV7_PMNC_MASK 0x3f /* Mask for writable bits */ 682 683 /* 684 * FLAG: counters overflow flag status reg 685 */ 686 #define ARMV7_FLAG_MASK 0xffffffff /* Mask for writable bits */ 687 #define ARMV7_OVERFLOWED_MASK ARMV7_FLAG_MASK 688 689 /* 690 * PMXEVTYPER: Event selection reg 691 */ 692 #define ARMV7_EVTYPE_MASK 0xc80000ff /* Mask for writable bits */ 693 #define ARMV7_EVTYPE_EVENT 0xff /* Mask for EVENT bits */ 694 695 /* 696 * Event filters for PMUv2 697 */ 698 #define ARMV7_EXCLUDE_PL1 BIT(31) 699 #define ARMV7_EXCLUDE_USER BIT(30) 700 #define ARMV7_INCLUDE_HYP BIT(27) 701 702 /* 703 * Secure debug enable reg 704 */ 705 #define ARMV7_SDER_SUNIDEN BIT(1) /* Permit non-invasive debug */ 706 707 static inline u32 armv7_pmnc_read(void) 708 { 709 u32 val; 710 asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r"(val)); 711 return val; 712 } 713 714 static inline void armv7_pmnc_write(u32 val) 715 { 716 val &= ARMV7_PMNC_MASK; 717 isb(); 718 asm volatile("mcr p15, 0, %0, c9, c12, 0" : : "r"(val)); 719 } 720 721 static inline int armv7_pmnc_has_overflowed(u32 pmnc) 722 { 723 return pmnc & ARMV7_OVERFLOWED_MASK; 724 } 725 726 static inline int armv7_pmnc_counter_valid(struct arm_pmu *cpu_pmu, int idx) 727 { 728 return idx >= ARMV7_IDX_CYCLE_COUNTER && 729 idx <= ARMV7_IDX_COUNTER_LAST(cpu_pmu); 730 } 731 732 static inline int armv7_pmnc_counter_has_overflowed(u32 pmnc, int idx) 733 { 734 return pmnc & BIT(ARMV7_IDX_TO_COUNTER(idx)); 735 } 736 737 static inline void armv7_pmnc_select_counter(int idx) 738 { 739 u32 counter = ARMV7_IDX_TO_COUNTER(idx); 740 asm volatile("mcr p15, 0, %0, c9, c12, 5" : : "r" (counter)); 741 isb(); 742 } 743 744 static inline u64 armv7pmu_read_counter(struct perf_event *event) 745 { 746 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu); 747 struct hw_perf_event *hwc = &event->hw; 748 int idx = hwc->idx; 749 u32 value = 0; 750 751 if (!armv7_pmnc_counter_valid(cpu_pmu, idx)) { 752 pr_err("CPU%u reading wrong counter %d\n", 753 smp_processor_id(), idx); 754 } else if (idx == ARMV7_IDX_CYCLE_COUNTER) { 755 asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (value)); 756 } else { 757 armv7_pmnc_select_counter(idx); 758 asm volatile("mrc p15, 0, %0, c9, c13, 2" : "=r" (value)); 759 } 760 761 return value; 762 } 763 764 static inline void armv7pmu_write_counter(struct perf_event *event, u64 value) 765 { 766 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu); 767 struct hw_perf_event *hwc = &event->hw; 768 int idx = hwc->idx; 769 770 if (!armv7_pmnc_counter_valid(cpu_pmu, idx)) { 771 pr_err("CPU%u writing wrong counter %d\n", 772 smp_processor_id(), idx); 773 } else if (idx == ARMV7_IDX_CYCLE_COUNTER) { 774 asm volatile("mcr p15, 0, %0, c9, c13, 0" : : "r" ((u32)value)); 775 } else { 776 armv7_pmnc_select_counter(idx); 777 asm volatile("mcr p15, 0, %0, c9, c13, 2" : : "r" ((u32)value)); 778 } 779 } 780 781 static inline void armv7_pmnc_write_evtsel(int idx, u32 val) 782 { 783 armv7_pmnc_select_counter(idx); 784 val &= ARMV7_EVTYPE_MASK; 785 asm volatile("mcr p15, 0, %0, c9, c13, 1" : : "r" (val)); 786 } 787 788 static inline void armv7_pmnc_enable_counter(int idx) 789 { 790 u32 counter = ARMV7_IDX_TO_COUNTER(idx); 791 asm volatile("mcr p15, 0, %0, c9, c12, 1" : : "r" (BIT(counter))); 792 } 793 794 static inline void armv7_pmnc_disable_counter(int idx) 795 { 796 u32 counter = ARMV7_IDX_TO_COUNTER(idx); 797 asm volatile("mcr p15, 0, %0, c9, c12, 2" : : "r" (BIT(counter))); 798 } 799 800 static inline void armv7_pmnc_enable_intens(int idx) 801 { 802 u32 counter = ARMV7_IDX_TO_COUNTER(idx); 803 asm volatile("mcr p15, 0, %0, c9, c14, 1" : : "r" (BIT(counter))); 804 } 805 806 static inline void armv7_pmnc_disable_intens(int idx) 807 { 808 u32 counter = ARMV7_IDX_TO_COUNTER(idx); 809 asm volatile("mcr p15, 0, %0, c9, c14, 2" : : "r" (BIT(counter))); 810 isb(); 811 /* Clear the overflow flag in case an interrupt is pending. */ 812 asm volatile("mcr p15, 0, %0, c9, c12, 3" : : "r" (BIT(counter))); 813 isb(); 814 } 815 816 static inline u32 armv7_pmnc_getreset_flags(void) 817 { 818 u32 val; 819 820 /* Read */ 821 asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (val)); 822 823 /* Write to clear flags */ 824 val &= ARMV7_FLAG_MASK; 825 asm volatile("mcr p15, 0, %0, c9, c12, 3" : : "r" (val)); 826 827 return val; 828 } 829 830 #ifdef DEBUG 831 static void armv7_pmnc_dump_regs(struct arm_pmu *cpu_pmu) 832 { 833 u32 val; 834 unsigned int cnt; 835 836 pr_info("PMNC registers dump:\n"); 837 838 asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r" (val)); 839 pr_info("PMNC =0x%08x\n", val); 840 841 asm volatile("mrc p15, 0, %0, c9, c12, 1" : "=r" (val)); 842 pr_info("CNTENS=0x%08x\n", val); 843 844 asm volatile("mrc p15, 0, %0, c9, c14, 1" : "=r" (val)); 845 pr_info("INTENS=0x%08x\n", val); 846 847 asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (val)); 848 pr_info("FLAGS =0x%08x\n", val); 849 850 asm volatile("mrc p15, 0, %0, c9, c12, 5" : "=r" (val)); 851 pr_info("SELECT=0x%08x\n", val); 852 853 asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (val)); 854 pr_info("CCNT =0x%08x\n", val); 855 856 for (cnt = ARMV7_IDX_COUNTER0; 857 cnt <= ARMV7_IDX_COUNTER_LAST(cpu_pmu); cnt++) { 858 armv7_pmnc_select_counter(cnt); 859 asm volatile("mrc p15, 0, %0, c9, c13, 2" : "=r" (val)); 860 pr_info("CNT[%d] count =0x%08x\n", 861 ARMV7_IDX_TO_COUNTER(cnt), val); 862 asm volatile("mrc p15, 0, %0, c9, c13, 1" : "=r" (val)); 863 pr_info("CNT[%d] evtsel=0x%08x\n", 864 ARMV7_IDX_TO_COUNTER(cnt), val); 865 } 866 } 867 #endif 868 869 static void armv7pmu_enable_event(struct perf_event *event) 870 { 871 struct hw_perf_event *hwc = &event->hw; 872 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu); 873 int idx = hwc->idx; 874 875 if (!armv7_pmnc_counter_valid(cpu_pmu, idx)) { 876 pr_err("CPU%u enabling wrong PMNC counter IRQ enable %d\n", 877 smp_processor_id(), idx); 878 return; 879 } 880 881 /* 882 * Enable counter and interrupt, and set the counter to count 883 * the event that we're interested in. 884 */ 885 886 /* 887 * Disable counter 888 */ 889 armv7_pmnc_disable_counter(idx); 890 891 /* 892 * Set event (if destined for PMNx counters) 893 * We only need to set the event for the cycle counter if we 894 * have the ability to perform event filtering. 895 */ 896 if (cpu_pmu->set_event_filter || idx != ARMV7_IDX_CYCLE_COUNTER) 897 armv7_pmnc_write_evtsel(idx, hwc->config_base); 898 899 /* 900 * Enable interrupt for this counter 901 */ 902 armv7_pmnc_enable_intens(idx); 903 904 /* 905 * Enable counter 906 */ 907 armv7_pmnc_enable_counter(idx); 908 } 909 910 static void armv7pmu_disable_event(struct perf_event *event) 911 { 912 struct hw_perf_event *hwc = &event->hw; 913 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu); 914 int idx = hwc->idx; 915 916 if (!armv7_pmnc_counter_valid(cpu_pmu, idx)) { 917 pr_err("CPU%u disabling wrong PMNC counter IRQ enable %d\n", 918 smp_processor_id(), idx); 919 return; 920 } 921 922 /* 923 * Disable counter and interrupt 924 */ 925 926 /* 927 * Disable counter 928 */ 929 armv7_pmnc_disable_counter(idx); 930 931 /* 932 * Disable interrupt for this counter 933 */ 934 armv7_pmnc_disable_intens(idx); 935 } 936 937 static irqreturn_t armv7pmu_handle_irq(struct arm_pmu *cpu_pmu) 938 { 939 u32 pmnc; 940 struct perf_sample_data data; 941 struct pmu_hw_events *cpuc = this_cpu_ptr(cpu_pmu->hw_events); 942 struct pt_regs *regs; 943 int idx; 944 945 /* 946 * Get and reset the IRQ flags 947 */ 948 pmnc = armv7_pmnc_getreset_flags(); 949 950 /* 951 * Did an overflow occur? 952 */ 953 if (!armv7_pmnc_has_overflowed(pmnc)) 954 return IRQ_NONE; 955 956 /* 957 * Handle the counter(s) overflow(s) 958 */ 959 regs = get_irq_regs(); 960 961 for (idx = 0; idx < cpu_pmu->num_events; ++idx) { 962 struct perf_event *event = cpuc->events[idx]; 963 struct hw_perf_event *hwc; 964 965 /* Ignore if we don't have an event. */ 966 if (!event) 967 continue; 968 969 /* 970 * We have a single interrupt for all counters. Check that 971 * each counter has overflowed before we process it. 972 */ 973 if (!armv7_pmnc_counter_has_overflowed(pmnc, idx)) 974 continue; 975 976 hwc = &event->hw; 977 armpmu_event_update(event); 978 perf_sample_data_init(&data, 0, hwc->last_period); 979 if (!armpmu_event_set_period(event)) 980 continue; 981 982 if (perf_event_overflow(event, &data, regs)) 983 cpu_pmu->disable(event); 984 } 985 986 /* 987 * Handle the pending perf events. 988 * 989 * Note: this call *must* be run with interrupts disabled. For 990 * platforms that can have the PMU interrupts raised as an NMI, this 991 * will not work. 992 */ 993 irq_work_run(); 994 995 return IRQ_HANDLED; 996 } 997 998 static void armv7pmu_start(struct arm_pmu *cpu_pmu) 999 { 1000 /* Enable all counters */ 1001 armv7_pmnc_write(armv7_pmnc_read() | ARMV7_PMNC_E); 1002 } 1003 1004 static void armv7pmu_stop(struct arm_pmu *cpu_pmu) 1005 { 1006 /* Disable all counters */ 1007 armv7_pmnc_write(armv7_pmnc_read() & ~ARMV7_PMNC_E); 1008 } 1009 1010 static int armv7pmu_get_event_idx(struct pmu_hw_events *cpuc, 1011 struct perf_event *event) 1012 { 1013 int idx; 1014 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu); 1015 struct hw_perf_event *hwc = &event->hw; 1016 unsigned long evtype = hwc->config_base & ARMV7_EVTYPE_EVENT; 1017 1018 /* Always place a cycle counter into the cycle counter. */ 1019 if (evtype == ARMV7_PERFCTR_CPU_CYCLES) { 1020 if (test_and_set_bit(ARMV7_IDX_CYCLE_COUNTER, cpuc->used_mask)) 1021 return -EAGAIN; 1022 1023 return ARMV7_IDX_CYCLE_COUNTER; 1024 } 1025 1026 /* 1027 * For anything other than a cycle counter, try and use 1028 * the events counters 1029 */ 1030 for (idx = ARMV7_IDX_COUNTER0; idx < cpu_pmu->num_events; ++idx) { 1031 if (!test_and_set_bit(idx, cpuc->used_mask)) 1032 return idx; 1033 } 1034 1035 /* The counters are all in use. */ 1036 return -EAGAIN; 1037 } 1038 1039 static void armv7pmu_clear_event_idx(struct pmu_hw_events *cpuc, 1040 struct perf_event *event) 1041 { 1042 clear_bit(event->hw.idx, cpuc->used_mask); 1043 } 1044 1045 /* 1046 * Add an event filter to a given event. This will only work for PMUv2 PMUs. 1047 */ 1048 static int armv7pmu_set_event_filter(struct hw_perf_event *event, 1049 struct perf_event_attr *attr) 1050 { 1051 unsigned long config_base = 0; 1052 1053 if (attr->exclude_idle) { 1054 pr_debug("ARM performance counters do not support mode exclusion\n"); 1055 return -EOPNOTSUPP; 1056 } 1057 if (attr->exclude_user) 1058 config_base |= ARMV7_EXCLUDE_USER; 1059 if (attr->exclude_kernel) 1060 config_base |= ARMV7_EXCLUDE_PL1; 1061 if (!attr->exclude_hv) 1062 config_base |= ARMV7_INCLUDE_HYP; 1063 1064 /* 1065 * Install the filter into config_base as this is used to 1066 * construct the event type. 1067 */ 1068 event->config_base = config_base; 1069 1070 return 0; 1071 } 1072 1073 static void armv7pmu_reset(void *info) 1074 { 1075 struct arm_pmu *cpu_pmu = (struct arm_pmu *)info; 1076 u32 idx, nb_cnt = cpu_pmu->num_events, val; 1077 1078 if (cpu_pmu->secure_access) { 1079 asm volatile("mrc p15, 0, %0, c1, c1, 1" : "=r" (val)); 1080 val |= ARMV7_SDER_SUNIDEN; 1081 asm volatile("mcr p15, 0, %0, c1, c1, 1" : : "r" (val)); 1082 } 1083 1084 /* The counter and interrupt enable registers are unknown at reset. */ 1085 for (idx = ARMV7_IDX_CYCLE_COUNTER; idx < nb_cnt; ++idx) { 1086 armv7_pmnc_disable_counter(idx); 1087 armv7_pmnc_disable_intens(idx); 1088 } 1089 1090 /* Initialize & Reset PMNC: C and P bits */ 1091 armv7_pmnc_write(ARMV7_PMNC_P | ARMV7_PMNC_C); 1092 } 1093 1094 static int armv7_a8_map_event(struct perf_event *event) 1095 { 1096 return armpmu_map_event(event, &armv7_a8_perf_map, 1097 &armv7_a8_perf_cache_map, 0xFF); 1098 } 1099 1100 static int armv7_a9_map_event(struct perf_event *event) 1101 { 1102 return armpmu_map_event(event, &armv7_a9_perf_map, 1103 &armv7_a9_perf_cache_map, 0xFF); 1104 } 1105 1106 static int armv7_a5_map_event(struct perf_event *event) 1107 { 1108 return armpmu_map_event(event, &armv7_a5_perf_map, 1109 &armv7_a5_perf_cache_map, 0xFF); 1110 } 1111 1112 static int armv7_a15_map_event(struct perf_event *event) 1113 { 1114 return armpmu_map_event(event, &armv7_a15_perf_map, 1115 &armv7_a15_perf_cache_map, 0xFF); 1116 } 1117 1118 static int armv7_a7_map_event(struct perf_event *event) 1119 { 1120 return armpmu_map_event(event, &armv7_a7_perf_map, 1121 &armv7_a7_perf_cache_map, 0xFF); 1122 } 1123 1124 static int armv7_a12_map_event(struct perf_event *event) 1125 { 1126 return armpmu_map_event(event, &armv7_a12_perf_map, 1127 &armv7_a12_perf_cache_map, 0xFF); 1128 } 1129 1130 static int krait_map_event(struct perf_event *event) 1131 { 1132 return armpmu_map_event(event, &krait_perf_map, 1133 &krait_perf_cache_map, 0xFFFFF); 1134 } 1135 1136 static int krait_map_event_no_branch(struct perf_event *event) 1137 { 1138 return armpmu_map_event(event, &krait_perf_map_no_branch, 1139 &krait_perf_cache_map, 0xFFFFF); 1140 } 1141 1142 static int scorpion_map_event(struct perf_event *event) 1143 { 1144 return armpmu_map_event(event, &scorpion_perf_map, 1145 &scorpion_perf_cache_map, 0xFFFFF); 1146 } 1147 1148 static void armv7pmu_init(struct arm_pmu *cpu_pmu) 1149 { 1150 cpu_pmu->handle_irq = armv7pmu_handle_irq; 1151 cpu_pmu->enable = armv7pmu_enable_event; 1152 cpu_pmu->disable = armv7pmu_disable_event; 1153 cpu_pmu->read_counter = armv7pmu_read_counter; 1154 cpu_pmu->write_counter = armv7pmu_write_counter; 1155 cpu_pmu->get_event_idx = armv7pmu_get_event_idx; 1156 cpu_pmu->clear_event_idx = armv7pmu_clear_event_idx; 1157 cpu_pmu->start = armv7pmu_start; 1158 cpu_pmu->stop = armv7pmu_stop; 1159 cpu_pmu->reset = armv7pmu_reset; 1160 }; 1161 1162 static void armv7_read_num_pmnc_events(void *info) 1163 { 1164 int *nb_cnt = info; 1165 1166 /* Read the nb of CNTx counters supported from PMNC */ 1167 *nb_cnt = (armv7_pmnc_read() >> ARMV7_PMNC_N_SHIFT) & ARMV7_PMNC_N_MASK; 1168 1169 /* Add the CPU cycles counter */ 1170 *nb_cnt += 1; 1171 } 1172 1173 static int armv7_probe_num_events(struct arm_pmu *arm_pmu) 1174 { 1175 return smp_call_function_any(&arm_pmu->supported_cpus, 1176 armv7_read_num_pmnc_events, 1177 &arm_pmu->num_events, 1); 1178 } 1179 1180 static int armv7_a8_pmu_init(struct arm_pmu *cpu_pmu) 1181 { 1182 armv7pmu_init(cpu_pmu); 1183 cpu_pmu->name = "armv7_cortex_a8"; 1184 cpu_pmu->map_event = armv7_a8_map_event; 1185 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = 1186 &armv7_pmuv1_events_attr_group; 1187 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] = 1188 &armv7_pmu_format_attr_group; 1189 return armv7_probe_num_events(cpu_pmu); 1190 } 1191 1192 static int armv7_a9_pmu_init(struct arm_pmu *cpu_pmu) 1193 { 1194 armv7pmu_init(cpu_pmu); 1195 cpu_pmu->name = "armv7_cortex_a9"; 1196 cpu_pmu->map_event = armv7_a9_map_event; 1197 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = 1198 &armv7_pmuv1_events_attr_group; 1199 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] = 1200 &armv7_pmu_format_attr_group; 1201 return armv7_probe_num_events(cpu_pmu); 1202 } 1203 1204 static int armv7_a5_pmu_init(struct arm_pmu *cpu_pmu) 1205 { 1206 armv7pmu_init(cpu_pmu); 1207 cpu_pmu->name = "armv7_cortex_a5"; 1208 cpu_pmu->map_event = armv7_a5_map_event; 1209 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = 1210 &armv7_pmuv1_events_attr_group; 1211 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] = 1212 &armv7_pmu_format_attr_group; 1213 return armv7_probe_num_events(cpu_pmu); 1214 } 1215 1216 static int armv7_a15_pmu_init(struct arm_pmu *cpu_pmu) 1217 { 1218 armv7pmu_init(cpu_pmu); 1219 cpu_pmu->name = "armv7_cortex_a15"; 1220 cpu_pmu->map_event = armv7_a15_map_event; 1221 cpu_pmu->set_event_filter = armv7pmu_set_event_filter; 1222 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = 1223 &armv7_pmuv2_events_attr_group; 1224 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] = 1225 &armv7_pmu_format_attr_group; 1226 return armv7_probe_num_events(cpu_pmu); 1227 } 1228 1229 static int armv7_a7_pmu_init(struct arm_pmu *cpu_pmu) 1230 { 1231 armv7pmu_init(cpu_pmu); 1232 cpu_pmu->name = "armv7_cortex_a7"; 1233 cpu_pmu->map_event = armv7_a7_map_event; 1234 cpu_pmu->set_event_filter = armv7pmu_set_event_filter; 1235 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = 1236 &armv7_pmuv2_events_attr_group; 1237 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] = 1238 &armv7_pmu_format_attr_group; 1239 return armv7_probe_num_events(cpu_pmu); 1240 } 1241 1242 static int armv7_a12_pmu_init(struct arm_pmu *cpu_pmu) 1243 { 1244 armv7pmu_init(cpu_pmu); 1245 cpu_pmu->name = "armv7_cortex_a12"; 1246 cpu_pmu->map_event = armv7_a12_map_event; 1247 cpu_pmu->set_event_filter = armv7pmu_set_event_filter; 1248 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = 1249 &armv7_pmuv2_events_attr_group; 1250 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] = 1251 &armv7_pmu_format_attr_group; 1252 return armv7_probe_num_events(cpu_pmu); 1253 } 1254 1255 static int armv7_a17_pmu_init(struct arm_pmu *cpu_pmu) 1256 { 1257 int ret = armv7_a12_pmu_init(cpu_pmu); 1258 cpu_pmu->name = "armv7_cortex_a17"; 1259 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = 1260 &armv7_pmuv2_events_attr_group; 1261 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] = 1262 &armv7_pmu_format_attr_group; 1263 return ret; 1264 } 1265 1266 /* 1267 * Krait Performance Monitor Region Event Selection Register (PMRESRn) 1268 * 1269 * 31 30 24 16 8 0 1270 * +--------------------------------+ 1271 * PMRESR0 | EN | CC | CC | CC | CC | N = 1, R = 0 1272 * +--------------------------------+ 1273 * PMRESR1 | EN | CC | CC | CC | CC | N = 1, R = 1 1274 * +--------------------------------+ 1275 * PMRESR2 | EN | CC | CC | CC | CC | N = 1, R = 2 1276 * +--------------------------------+ 1277 * VPMRESR0 | EN | CC | CC | CC | CC | N = 2, R = ? 1278 * +--------------------------------+ 1279 * EN | G=3 | G=2 | G=1 | G=0 1280 * 1281 * Event Encoding: 1282 * 1283 * hwc->config_base = 0xNRCCG 1284 * 1285 * N = prefix, 1 for Krait CPU (PMRESRn), 2 for Venum VFP (VPMRESR) 1286 * R = region register 1287 * CC = class of events the group G is choosing from 1288 * G = group or particular event 1289 * 1290 * Example: 0x12021 is a Krait CPU event in PMRESR2's group 1 with code 2 1291 * 1292 * A region (R) corresponds to a piece of the CPU (execution unit, instruction 1293 * unit, etc.) while the event code (CC) corresponds to a particular class of 1294 * events (interrupts for example). An event code is broken down into 1295 * groups (G) that can be mapped into the PMU (irq, fiqs, and irq+fiqs for 1296 * example). 1297 */ 1298 1299 #define KRAIT_EVENT (1 << 16) 1300 #define VENUM_EVENT (2 << 16) 1301 #define KRAIT_EVENT_MASK (KRAIT_EVENT | VENUM_EVENT) 1302 #define PMRESRn_EN BIT(31) 1303 1304 #define EVENT_REGION(event) (((event) >> 12) & 0xf) /* R */ 1305 #define EVENT_GROUP(event) ((event) & 0xf) /* G */ 1306 #define EVENT_CODE(event) (((event) >> 4) & 0xff) /* CC */ 1307 #define EVENT_VENUM(event) (!!(event & VENUM_EVENT)) /* N=2 */ 1308 #define EVENT_CPU(event) (!!(event & KRAIT_EVENT)) /* N=1 */ 1309 1310 static u32 krait_read_pmresrn(int n) 1311 { 1312 u32 val; 1313 1314 switch (n) { 1315 case 0: 1316 asm volatile("mrc p15, 1, %0, c9, c15, 0" : "=r" (val)); 1317 break; 1318 case 1: 1319 asm volatile("mrc p15, 1, %0, c9, c15, 1" : "=r" (val)); 1320 break; 1321 case 2: 1322 asm volatile("mrc p15, 1, %0, c9, c15, 2" : "=r" (val)); 1323 break; 1324 default: 1325 BUG(); /* Should be validated in krait_pmu_get_event_idx() */ 1326 } 1327 1328 return val; 1329 } 1330 1331 static void krait_write_pmresrn(int n, u32 val) 1332 { 1333 switch (n) { 1334 case 0: 1335 asm volatile("mcr p15, 1, %0, c9, c15, 0" : : "r" (val)); 1336 break; 1337 case 1: 1338 asm volatile("mcr p15, 1, %0, c9, c15, 1" : : "r" (val)); 1339 break; 1340 case 2: 1341 asm volatile("mcr p15, 1, %0, c9, c15, 2" : : "r" (val)); 1342 break; 1343 default: 1344 BUG(); /* Should be validated in krait_pmu_get_event_idx() */ 1345 } 1346 } 1347 1348 static u32 venum_read_pmresr(void) 1349 { 1350 u32 val; 1351 asm volatile("mrc p10, 7, %0, c11, c0, 0" : "=r" (val)); 1352 return val; 1353 } 1354 1355 static void venum_write_pmresr(u32 val) 1356 { 1357 asm volatile("mcr p10, 7, %0, c11, c0, 0" : : "r" (val)); 1358 } 1359 1360 static void venum_pre_pmresr(u32 *venum_orig_val, u32 *fp_orig_val) 1361 { 1362 u32 venum_new_val; 1363 u32 fp_new_val; 1364 1365 BUG_ON(preemptible()); 1366 /* CPACR Enable CP10 and CP11 access */ 1367 *venum_orig_val = get_copro_access(); 1368 venum_new_val = *venum_orig_val | CPACC_SVC(10) | CPACC_SVC(11); 1369 set_copro_access(venum_new_val); 1370 1371 /* Enable FPEXC */ 1372 *fp_orig_val = fmrx(FPEXC); 1373 fp_new_val = *fp_orig_val | FPEXC_EN; 1374 fmxr(FPEXC, fp_new_val); 1375 } 1376 1377 static void venum_post_pmresr(u32 venum_orig_val, u32 fp_orig_val) 1378 { 1379 BUG_ON(preemptible()); 1380 /* Restore FPEXC */ 1381 fmxr(FPEXC, fp_orig_val); 1382 isb(); 1383 /* Restore CPACR */ 1384 set_copro_access(venum_orig_val); 1385 } 1386 1387 static u32 krait_get_pmresrn_event(unsigned int region) 1388 { 1389 static const u32 pmresrn_table[] = { KRAIT_PMRESR0_GROUP0, 1390 KRAIT_PMRESR1_GROUP0, 1391 KRAIT_PMRESR2_GROUP0 }; 1392 return pmresrn_table[region]; 1393 } 1394 1395 static void krait_evt_setup(int idx, u32 config_base) 1396 { 1397 u32 val; 1398 u32 mask; 1399 u32 vval, fval; 1400 unsigned int region = EVENT_REGION(config_base); 1401 unsigned int group = EVENT_GROUP(config_base); 1402 unsigned int code = EVENT_CODE(config_base); 1403 unsigned int group_shift; 1404 bool venum_event = EVENT_VENUM(config_base); 1405 1406 group_shift = group * 8; 1407 mask = 0xff << group_shift; 1408 1409 /* Configure evtsel for the region and group */ 1410 if (venum_event) 1411 val = KRAIT_VPMRESR0_GROUP0; 1412 else 1413 val = krait_get_pmresrn_event(region); 1414 val += group; 1415 /* Mix in mode-exclusion bits */ 1416 val |= config_base & (ARMV7_EXCLUDE_USER | ARMV7_EXCLUDE_PL1); 1417 armv7_pmnc_write_evtsel(idx, val); 1418 1419 if (venum_event) { 1420 venum_pre_pmresr(&vval, &fval); 1421 val = venum_read_pmresr(); 1422 val &= ~mask; 1423 val |= code << group_shift; 1424 val |= PMRESRn_EN; 1425 venum_write_pmresr(val); 1426 venum_post_pmresr(vval, fval); 1427 } else { 1428 val = krait_read_pmresrn(region); 1429 val &= ~mask; 1430 val |= code << group_shift; 1431 val |= PMRESRn_EN; 1432 krait_write_pmresrn(region, val); 1433 } 1434 } 1435 1436 static u32 clear_pmresrn_group(u32 val, int group) 1437 { 1438 u32 mask; 1439 int group_shift; 1440 1441 group_shift = group * 8; 1442 mask = 0xff << group_shift; 1443 val &= ~mask; 1444 1445 /* Don't clear enable bit if entire region isn't disabled */ 1446 if (val & ~PMRESRn_EN) 1447 return val |= PMRESRn_EN; 1448 1449 return 0; 1450 } 1451 1452 static void krait_clearpmu(u32 config_base) 1453 { 1454 u32 val; 1455 u32 vval, fval; 1456 unsigned int region = EVENT_REGION(config_base); 1457 unsigned int group = EVENT_GROUP(config_base); 1458 bool venum_event = EVENT_VENUM(config_base); 1459 1460 if (venum_event) { 1461 venum_pre_pmresr(&vval, &fval); 1462 val = venum_read_pmresr(); 1463 val = clear_pmresrn_group(val, group); 1464 venum_write_pmresr(val); 1465 venum_post_pmresr(vval, fval); 1466 } else { 1467 val = krait_read_pmresrn(region); 1468 val = clear_pmresrn_group(val, group); 1469 krait_write_pmresrn(region, val); 1470 } 1471 } 1472 1473 static void krait_pmu_disable_event(struct perf_event *event) 1474 { 1475 struct hw_perf_event *hwc = &event->hw; 1476 int idx = hwc->idx; 1477 1478 /* Disable counter and interrupt */ 1479 1480 /* Disable counter */ 1481 armv7_pmnc_disable_counter(idx); 1482 1483 /* 1484 * Clear pmresr code (if destined for PMNx counters) 1485 */ 1486 if (hwc->config_base & KRAIT_EVENT_MASK) 1487 krait_clearpmu(hwc->config_base); 1488 1489 /* Disable interrupt for this counter */ 1490 armv7_pmnc_disable_intens(idx); 1491 } 1492 1493 static void krait_pmu_enable_event(struct perf_event *event) 1494 { 1495 struct hw_perf_event *hwc = &event->hw; 1496 int idx = hwc->idx; 1497 1498 /* 1499 * Enable counter and interrupt, and set the counter to count 1500 * the event that we're interested in. 1501 */ 1502 1503 /* Disable counter */ 1504 armv7_pmnc_disable_counter(idx); 1505 1506 /* 1507 * Set event (if destined for PMNx counters) 1508 * We set the event for the cycle counter because we 1509 * have the ability to perform event filtering. 1510 */ 1511 if (hwc->config_base & KRAIT_EVENT_MASK) 1512 krait_evt_setup(idx, hwc->config_base); 1513 else 1514 armv7_pmnc_write_evtsel(idx, hwc->config_base); 1515 1516 /* Enable interrupt for this counter */ 1517 armv7_pmnc_enable_intens(idx); 1518 1519 /* Enable counter */ 1520 armv7_pmnc_enable_counter(idx); 1521 } 1522 1523 static void krait_pmu_reset(void *info) 1524 { 1525 u32 vval, fval; 1526 struct arm_pmu *cpu_pmu = info; 1527 u32 idx, nb_cnt = cpu_pmu->num_events; 1528 1529 armv7pmu_reset(info); 1530 1531 /* Clear all pmresrs */ 1532 krait_write_pmresrn(0, 0); 1533 krait_write_pmresrn(1, 0); 1534 krait_write_pmresrn(2, 0); 1535 1536 venum_pre_pmresr(&vval, &fval); 1537 venum_write_pmresr(0); 1538 venum_post_pmresr(vval, fval); 1539 1540 /* Reset PMxEVNCTCR to sane default */ 1541 for (idx = ARMV7_IDX_CYCLE_COUNTER; idx < nb_cnt; ++idx) { 1542 armv7_pmnc_select_counter(idx); 1543 asm volatile("mcr p15, 0, %0, c9, c15, 0" : : "r" (0)); 1544 } 1545 1546 } 1547 1548 static int krait_event_to_bit(struct perf_event *event, unsigned int region, 1549 unsigned int group) 1550 { 1551 int bit; 1552 struct hw_perf_event *hwc = &event->hw; 1553 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu); 1554 1555 if (hwc->config_base & VENUM_EVENT) 1556 bit = KRAIT_VPMRESR0_GROUP0; 1557 else 1558 bit = krait_get_pmresrn_event(region); 1559 bit -= krait_get_pmresrn_event(0); 1560 bit += group; 1561 /* 1562 * Lower bits are reserved for use by the counters (see 1563 * armv7pmu_get_event_idx() for more info) 1564 */ 1565 bit += ARMV7_IDX_COUNTER_LAST(cpu_pmu) + 1; 1566 1567 return bit; 1568 } 1569 1570 /* 1571 * We check for column exclusion constraints here. 1572 * Two events cant use the same group within a pmresr register. 1573 */ 1574 static int krait_pmu_get_event_idx(struct pmu_hw_events *cpuc, 1575 struct perf_event *event) 1576 { 1577 int idx; 1578 int bit = -1; 1579 struct hw_perf_event *hwc = &event->hw; 1580 unsigned int region = EVENT_REGION(hwc->config_base); 1581 unsigned int code = EVENT_CODE(hwc->config_base); 1582 unsigned int group = EVENT_GROUP(hwc->config_base); 1583 bool venum_event = EVENT_VENUM(hwc->config_base); 1584 bool krait_event = EVENT_CPU(hwc->config_base); 1585 1586 if (venum_event || krait_event) { 1587 /* Ignore invalid events */ 1588 if (group > 3 || region > 2) 1589 return -EINVAL; 1590 if (venum_event && (code & 0xe0)) 1591 return -EINVAL; 1592 1593 bit = krait_event_to_bit(event, region, group); 1594 if (test_and_set_bit(bit, cpuc->used_mask)) 1595 return -EAGAIN; 1596 } 1597 1598 idx = armv7pmu_get_event_idx(cpuc, event); 1599 if (idx < 0 && bit >= 0) 1600 clear_bit(bit, cpuc->used_mask); 1601 1602 return idx; 1603 } 1604 1605 static void krait_pmu_clear_event_idx(struct pmu_hw_events *cpuc, 1606 struct perf_event *event) 1607 { 1608 int bit; 1609 struct hw_perf_event *hwc = &event->hw; 1610 unsigned int region = EVENT_REGION(hwc->config_base); 1611 unsigned int group = EVENT_GROUP(hwc->config_base); 1612 bool venum_event = EVENT_VENUM(hwc->config_base); 1613 bool krait_event = EVENT_CPU(hwc->config_base); 1614 1615 armv7pmu_clear_event_idx(cpuc, event); 1616 if (venum_event || krait_event) { 1617 bit = krait_event_to_bit(event, region, group); 1618 clear_bit(bit, cpuc->used_mask); 1619 } 1620 } 1621 1622 static int krait_pmu_init(struct arm_pmu *cpu_pmu) 1623 { 1624 armv7pmu_init(cpu_pmu); 1625 cpu_pmu->name = "armv7_krait"; 1626 /* Some early versions of Krait don't support PC write events */ 1627 if (of_property_read_bool(cpu_pmu->plat_device->dev.of_node, 1628 "qcom,no-pc-write")) 1629 cpu_pmu->map_event = krait_map_event_no_branch; 1630 else 1631 cpu_pmu->map_event = krait_map_event; 1632 cpu_pmu->set_event_filter = armv7pmu_set_event_filter; 1633 cpu_pmu->reset = krait_pmu_reset; 1634 cpu_pmu->enable = krait_pmu_enable_event; 1635 cpu_pmu->disable = krait_pmu_disable_event; 1636 cpu_pmu->get_event_idx = krait_pmu_get_event_idx; 1637 cpu_pmu->clear_event_idx = krait_pmu_clear_event_idx; 1638 return armv7_probe_num_events(cpu_pmu); 1639 } 1640 1641 /* 1642 * Scorpion Local Performance Monitor Register (LPMn) 1643 * 1644 * 31 30 24 16 8 0 1645 * +--------------------------------+ 1646 * LPM0 | EN | CC | CC | CC | CC | N = 1, R = 0 1647 * +--------------------------------+ 1648 * LPM1 | EN | CC | CC | CC | CC | N = 1, R = 1 1649 * +--------------------------------+ 1650 * LPM2 | EN | CC | CC | CC | CC | N = 1, R = 2 1651 * +--------------------------------+ 1652 * L2LPM | EN | CC | CC | CC | CC | N = 1, R = 3 1653 * +--------------------------------+ 1654 * VLPM | EN | CC | CC | CC | CC | N = 2, R = ? 1655 * +--------------------------------+ 1656 * EN | G=3 | G=2 | G=1 | G=0 1657 * 1658 * 1659 * Event Encoding: 1660 * 1661 * hwc->config_base = 0xNRCCG 1662 * 1663 * N = prefix, 1 for Scorpion CPU (LPMn/L2LPM), 2 for Venum VFP (VLPM) 1664 * R = region register 1665 * CC = class of events the group G is choosing from 1666 * G = group or particular event 1667 * 1668 * Example: 0x12021 is a Scorpion CPU event in LPM2's group 1 with code 2 1669 * 1670 * A region (R) corresponds to a piece of the CPU (execution unit, instruction 1671 * unit, etc.) while the event code (CC) corresponds to a particular class of 1672 * events (interrupts for example). An event code is broken down into 1673 * groups (G) that can be mapped into the PMU (irq, fiqs, and irq+fiqs for 1674 * example). 1675 */ 1676 1677 static u32 scorpion_read_pmresrn(int n) 1678 { 1679 u32 val; 1680 1681 switch (n) { 1682 case 0: 1683 asm volatile("mrc p15, 0, %0, c15, c0, 0" : "=r" (val)); 1684 break; 1685 case 1: 1686 asm volatile("mrc p15, 1, %0, c15, c0, 0" : "=r" (val)); 1687 break; 1688 case 2: 1689 asm volatile("mrc p15, 2, %0, c15, c0, 0" : "=r" (val)); 1690 break; 1691 case 3: 1692 asm volatile("mrc p15, 3, %0, c15, c2, 0" : "=r" (val)); 1693 break; 1694 default: 1695 BUG(); /* Should be validated in scorpion_pmu_get_event_idx() */ 1696 } 1697 1698 return val; 1699 } 1700 1701 static void scorpion_write_pmresrn(int n, u32 val) 1702 { 1703 switch (n) { 1704 case 0: 1705 asm volatile("mcr p15, 0, %0, c15, c0, 0" : : "r" (val)); 1706 break; 1707 case 1: 1708 asm volatile("mcr p15, 1, %0, c15, c0, 0" : : "r" (val)); 1709 break; 1710 case 2: 1711 asm volatile("mcr p15, 2, %0, c15, c0, 0" : : "r" (val)); 1712 break; 1713 case 3: 1714 asm volatile("mcr p15, 3, %0, c15, c2, 0" : : "r" (val)); 1715 break; 1716 default: 1717 BUG(); /* Should be validated in scorpion_pmu_get_event_idx() */ 1718 } 1719 } 1720 1721 static u32 scorpion_get_pmresrn_event(unsigned int region) 1722 { 1723 static const u32 pmresrn_table[] = { SCORPION_LPM0_GROUP0, 1724 SCORPION_LPM1_GROUP0, 1725 SCORPION_LPM2_GROUP0, 1726 SCORPION_L2LPM_GROUP0 }; 1727 return pmresrn_table[region]; 1728 } 1729 1730 static void scorpion_evt_setup(int idx, u32 config_base) 1731 { 1732 u32 val; 1733 u32 mask; 1734 u32 vval, fval; 1735 unsigned int region = EVENT_REGION(config_base); 1736 unsigned int group = EVENT_GROUP(config_base); 1737 unsigned int code = EVENT_CODE(config_base); 1738 unsigned int group_shift; 1739 bool venum_event = EVENT_VENUM(config_base); 1740 1741 group_shift = group * 8; 1742 mask = 0xff << group_shift; 1743 1744 /* Configure evtsel for the region and group */ 1745 if (venum_event) 1746 val = SCORPION_VLPM_GROUP0; 1747 else 1748 val = scorpion_get_pmresrn_event(region); 1749 val += group; 1750 /* Mix in mode-exclusion bits */ 1751 val |= config_base & (ARMV7_EXCLUDE_USER | ARMV7_EXCLUDE_PL1); 1752 armv7_pmnc_write_evtsel(idx, val); 1753 1754 asm volatile("mcr p15, 0, %0, c9, c15, 0" : : "r" (0)); 1755 1756 if (venum_event) { 1757 venum_pre_pmresr(&vval, &fval); 1758 val = venum_read_pmresr(); 1759 val &= ~mask; 1760 val |= code << group_shift; 1761 val |= PMRESRn_EN; 1762 venum_write_pmresr(val); 1763 venum_post_pmresr(vval, fval); 1764 } else { 1765 val = scorpion_read_pmresrn(region); 1766 val &= ~mask; 1767 val |= code << group_shift; 1768 val |= PMRESRn_EN; 1769 scorpion_write_pmresrn(region, val); 1770 } 1771 } 1772 1773 static void scorpion_clearpmu(u32 config_base) 1774 { 1775 u32 val; 1776 u32 vval, fval; 1777 unsigned int region = EVENT_REGION(config_base); 1778 unsigned int group = EVENT_GROUP(config_base); 1779 bool venum_event = EVENT_VENUM(config_base); 1780 1781 if (venum_event) { 1782 venum_pre_pmresr(&vval, &fval); 1783 val = venum_read_pmresr(); 1784 val = clear_pmresrn_group(val, group); 1785 venum_write_pmresr(val); 1786 venum_post_pmresr(vval, fval); 1787 } else { 1788 val = scorpion_read_pmresrn(region); 1789 val = clear_pmresrn_group(val, group); 1790 scorpion_write_pmresrn(region, val); 1791 } 1792 } 1793 1794 static void scorpion_pmu_disable_event(struct perf_event *event) 1795 { 1796 struct hw_perf_event *hwc = &event->hw; 1797 int idx = hwc->idx; 1798 1799 /* Disable counter and interrupt */ 1800 1801 /* Disable counter */ 1802 armv7_pmnc_disable_counter(idx); 1803 1804 /* 1805 * Clear pmresr code (if destined for PMNx counters) 1806 */ 1807 if (hwc->config_base & KRAIT_EVENT_MASK) 1808 scorpion_clearpmu(hwc->config_base); 1809 1810 /* Disable interrupt for this counter */ 1811 armv7_pmnc_disable_intens(idx); 1812 } 1813 1814 static void scorpion_pmu_enable_event(struct perf_event *event) 1815 { 1816 struct hw_perf_event *hwc = &event->hw; 1817 int idx = hwc->idx; 1818 1819 /* 1820 * Enable counter and interrupt, and set the counter to count 1821 * the event that we're interested in. 1822 */ 1823 1824 /* Disable counter */ 1825 armv7_pmnc_disable_counter(idx); 1826 1827 /* 1828 * Set event (if destined for PMNx counters) 1829 * We don't set the event for the cycle counter because we 1830 * don't have the ability to perform event filtering. 1831 */ 1832 if (hwc->config_base & KRAIT_EVENT_MASK) 1833 scorpion_evt_setup(idx, hwc->config_base); 1834 else if (idx != ARMV7_IDX_CYCLE_COUNTER) 1835 armv7_pmnc_write_evtsel(idx, hwc->config_base); 1836 1837 /* Enable interrupt for this counter */ 1838 armv7_pmnc_enable_intens(idx); 1839 1840 /* Enable counter */ 1841 armv7_pmnc_enable_counter(idx); 1842 } 1843 1844 static void scorpion_pmu_reset(void *info) 1845 { 1846 u32 vval, fval; 1847 struct arm_pmu *cpu_pmu = info; 1848 u32 idx, nb_cnt = cpu_pmu->num_events; 1849 1850 armv7pmu_reset(info); 1851 1852 /* Clear all pmresrs */ 1853 scorpion_write_pmresrn(0, 0); 1854 scorpion_write_pmresrn(1, 0); 1855 scorpion_write_pmresrn(2, 0); 1856 scorpion_write_pmresrn(3, 0); 1857 1858 venum_pre_pmresr(&vval, &fval); 1859 venum_write_pmresr(0); 1860 venum_post_pmresr(vval, fval); 1861 1862 /* Reset PMxEVNCTCR to sane default */ 1863 for (idx = ARMV7_IDX_CYCLE_COUNTER; idx < nb_cnt; ++idx) { 1864 armv7_pmnc_select_counter(idx); 1865 asm volatile("mcr p15, 0, %0, c9, c15, 0" : : "r" (0)); 1866 } 1867 } 1868 1869 static int scorpion_event_to_bit(struct perf_event *event, unsigned int region, 1870 unsigned int group) 1871 { 1872 int bit; 1873 struct hw_perf_event *hwc = &event->hw; 1874 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu); 1875 1876 if (hwc->config_base & VENUM_EVENT) 1877 bit = SCORPION_VLPM_GROUP0; 1878 else 1879 bit = scorpion_get_pmresrn_event(region); 1880 bit -= scorpion_get_pmresrn_event(0); 1881 bit += group; 1882 /* 1883 * Lower bits are reserved for use by the counters (see 1884 * armv7pmu_get_event_idx() for more info) 1885 */ 1886 bit += ARMV7_IDX_COUNTER_LAST(cpu_pmu) + 1; 1887 1888 return bit; 1889 } 1890 1891 /* 1892 * We check for column exclusion constraints here. 1893 * Two events cant use the same group within a pmresr register. 1894 */ 1895 static int scorpion_pmu_get_event_idx(struct pmu_hw_events *cpuc, 1896 struct perf_event *event) 1897 { 1898 int idx; 1899 int bit = -1; 1900 struct hw_perf_event *hwc = &event->hw; 1901 unsigned int region = EVENT_REGION(hwc->config_base); 1902 unsigned int group = EVENT_GROUP(hwc->config_base); 1903 bool venum_event = EVENT_VENUM(hwc->config_base); 1904 bool scorpion_event = EVENT_CPU(hwc->config_base); 1905 1906 if (venum_event || scorpion_event) { 1907 /* Ignore invalid events */ 1908 if (group > 3 || region > 3) 1909 return -EINVAL; 1910 1911 bit = scorpion_event_to_bit(event, region, group); 1912 if (test_and_set_bit(bit, cpuc->used_mask)) 1913 return -EAGAIN; 1914 } 1915 1916 idx = armv7pmu_get_event_idx(cpuc, event); 1917 if (idx < 0 && bit >= 0) 1918 clear_bit(bit, cpuc->used_mask); 1919 1920 return idx; 1921 } 1922 1923 static void scorpion_pmu_clear_event_idx(struct pmu_hw_events *cpuc, 1924 struct perf_event *event) 1925 { 1926 int bit; 1927 struct hw_perf_event *hwc = &event->hw; 1928 unsigned int region = EVENT_REGION(hwc->config_base); 1929 unsigned int group = EVENT_GROUP(hwc->config_base); 1930 bool venum_event = EVENT_VENUM(hwc->config_base); 1931 bool scorpion_event = EVENT_CPU(hwc->config_base); 1932 1933 armv7pmu_clear_event_idx(cpuc, event); 1934 if (venum_event || scorpion_event) { 1935 bit = scorpion_event_to_bit(event, region, group); 1936 clear_bit(bit, cpuc->used_mask); 1937 } 1938 } 1939 1940 static int scorpion_pmu_init(struct arm_pmu *cpu_pmu) 1941 { 1942 armv7pmu_init(cpu_pmu); 1943 cpu_pmu->name = "armv7_scorpion"; 1944 cpu_pmu->map_event = scorpion_map_event; 1945 cpu_pmu->reset = scorpion_pmu_reset; 1946 cpu_pmu->enable = scorpion_pmu_enable_event; 1947 cpu_pmu->disable = scorpion_pmu_disable_event; 1948 cpu_pmu->get_event_idx = scorpion_pmu_get_event_idx; 1949 cpu_pmu->clear_event_idx = scorpion_pmu_clear_event_idx; 1950 return armv7_probe_num_events(cpu_pmu); 1951 } 1952 1953 static int scorpion_mp_pmu_init(struct arm_pmu *cpu_pmu) 1954 { 1955 armv7pmu_init(cpu_pmu); 1956 cpu_pmu->name = "armv7_scorpion_mp"; 1957 cpu_pmu->map_event = scorpion_map_event; 1958 cpu_pmu->reset = scorpion_pmu_reset; 1959 cpu_pmu->enable = scorpion_pmu_enable_event; 1960 cpu_pmu->disable = scorpion_pmu_disable_event; 1961 cpu_pmu->get_event_idx = scorpion_pmu_get_event_idx; 1962 cpu_pmu->clear_event_idx = scorpion_pmu_clear_event_idx; 1963 return armv7_probe_num_events(cpu_pmu); 1964 } 1965 1966 static const struct of_device_id armv7_pmu_of_device_ids[] = { 1967 {.compatible = "arm,cortex-a17-pmu", .data = armv7_a17_pmu_init}, 1968 {.compatible = "arm,cortex-a15-pmu", .data = armv7_a15_pmu_init}, 1969 {.compatible = "arm,cortex-a12-pmu", .data = armv7_a12_pmu_init}, 1970 {.compatible = "arm,cortex-a9-pmu", .data = armv7_a9_pmu_init}, 1971 {.compatible = "arm,cortex-a8-pmu", .data = armv7_a8_pmu_init}, 1972 {.compatible = "arm,cortex-a7-pmu", .data = armv7_a7_pmu_init}, 1973 {.compatible = "arm,cortex-a5-pmu", .data = armv7_a5_pmu_init}, 1974 {.compatible = "qcom,krait-pmu", .data = krait_pmu_init}, 1975 {.compatible = "qcom,scorpion-pmu", .data = scorpion_pmu_init}, 1976 {.compatible = "qcom,scorpion-mp-pmu", .data = scorpion_mp_pmu_init}, 1977 {}, 1978 }; 1979 1980 static int armv7_pmu_device_probe(struct platform_device *pdev) 1981 { 1982 return arm_pmu_device_probe(pdev, armv7_pmu_of_device_ids, NULL); 1983 } 1984 1985 static struct platform_driver armv7_pmu_driver = { 1986 .driver = { 1987 .name = "armv7-pmu", 1988 .of_match_table = armv7_pmu_of_device_ids, 1989 .suppress_bind_attrs = true, 1990 }, 1991 .probe = armv7_pmu_device_probe, 1992 }; 1993 1994 builtin_platform_driver(armv7_pmu_driver); 1995