| /freebsd/sys/contrib/device-tree/Bindings/memory-controllers/ |
| H A D | arm,pl172.txt | 5 - compatible: Must be "arm,primecell" and exactly one from
8 - reg: Must contains offset/length value for controller.
10 - #address-cells: Must be 2. The partition number has to be encoded in the
11 first address cell and it may accept values 0..N-1
12 (N - total number of partitions). The second cell is the
15 - #size-cells: Must be set to 1.
17 - ranges: Must contain one or more chip select memory regions.
19 - clocks: Must contain references to controller clocks.
21 - clock-names: Must contain "mpmcclk" and "apb_pclk".
23 - clock-ranges: Empty property indicating that child nodes can inherit
[all …]
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| H A D | st,stm32-fmc2-ebi-props.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/st,stm32-fmc2-ebi-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Christophe Kerello <christophe.kerello@foss.st.com>
11 - Marek Vasut <marex@denx.de>
14 st,fmc2-ebi-cs-transaction-type:
25 8: Synchronous read synchronous write PSRAM.
26 9: Synchronous read asynchronous write PSRAM.
27 10: Synchronous read synchronous write NOR.
[all …]
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| H A D | ti-aemif.txt | 4 provide a glue-less interface to a variety of asynchronous memory devices like
11 Davinci DM646x - http://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf
12 OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
13 Kestone - http://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf
17 - compatible: "ti,davinci-aemif"
18 "ti,keystone-aemif"
19 "ti,da850-aemif"
21 - reg: contains offset/length value for AEMIF control registers
24 - #address-cells: Must be 2. The partition number has to be encoded in the
25 first address cell and it may accept values 0..N-1
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/arm/ |
| H A D | l2c2x0.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
16 models (Note 1). Some of the properties that are just prefixed "cache-*" are
22 cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These
28 - $ref: /schemas/cache-controller.yaml#
33 - enum:
34 - arm,pl310-cache
35 - arm,l220-cache
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/cache/ |
| H A D | l2c2x0.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
16 models (Note 1). Some of the properties that are just prefixed "cache-*" are
22 cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These
28 - $ref: /schemas/cache-controller.yaml#
33 - enum:
34 - arm,pl310-cache
35 - arm,l220-cache
[all …]
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| /freebsd/sys/contrib/alpine-hal/ |
| H A D | al_hal_nb_regs.h | 1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
101 /* [0x6c] Read-only that reflects CPU Cluster Local GIC base high address */
103 /* [0x70] Read-only that reflects CPU Cluster Local GIC base low address */
105 /* [0x74] Read-only that reflects the device's IOGIC base high address. */
107 /* [0x78] Read-only that reflects IOGIC base low address */
454 /* Enable broadcast of inner shareable transactions from CPUs.
460 /* Enable broadcast of outer shareable transactions from CPUs.
474 0 Enable the GIC CPU interface logic.
480 /* Value read in the Cluster ID Affinity Level-1 field, bits[15:8], of the Multiprocessor Affinity
[all …]
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| H A D | al_hal_udma_config.h | 9 found at http://www.gnu.org/licenses/gpl-2.0.html
53 /* *INDENT-OFF* */
57 /* *INDENT-ON* */
70 al_bool swap_8_bytes; /* enable 8 bytes swap instead of 4 bytes */
162 al_bool q_promotion; /* enable promotion */
164 al_bool en_pref_prediction; /* enable prefetch prediction */
177 /** S2M Data write configuration */
180 * data write FIFO, defined based on
184 * data write FIFO,defined based on
188 uint32_t desc_wait_timer; /* waiting time for the host to write
[all …]
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| H A D | al_hal_udma_regs_s2m.h | 1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
59 /* [0x0] Data write master configuration */
61 /* [0x4] Data write master configuration */
67 /* [0x10] Completion write master configuration */
69 /* [0x14] Completion write master configuration */
71 /* [0x18] Data write master configuration */
75 /* [0x20] Completion descriptors write master configuration */
79 /* [0x28] AXI outstanding write configuration */
86 * 00 - No pending tasks
[all …]
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| H A D | al_hal_udma_regs_gen.h | 9 found at http://www.gnu.org/licenses/gpl-2.0.html
100 /* [0x0] Target-ID control */
102 /* [0x4] TX queue 0/1 Target-ID */
104 /* [0x8] TX queue 2/3 Target-ID */
106 /* [0xc] RX queue 0/1 Target-ID */
108 /* [0x10] RX queue 2/3 Target-ID */
112 /* [0x0] TX queue 0/1 Target-Address */
114 /* [0x4] TX queue 2/3 Target-Address */
116 /* [0x8] RX queue 0/1 Target-Address */
118 /* [0xc] RX queue 2/3 Target-Address */
[all …]
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| H A D | al_hal_unit_adapter_regs.h | 1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
45 #define AL_PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
46 #define AL_PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
47 #define AL_PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
87 #define AL_PCI_EXP_DEVCAP_RBER 0x8000 /* Role-Based Error Reporting */
93 #define AL_PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Error Reporting Enable */
94 #define AL_PCI_EXP_DEVCTL_FERE 0x0004 /* Fatal Error Reporting Enable */
96 #define AL_PCI_EXP_DEVCTL_RELAX_EN 0x0010 /* Enable relaxed ordering */
98 #define AL_PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Extended Tag Field Enable */
[all …]
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| /freebsd/usr.sbin/mfiutil/ |
| H A D | mfiutil.8 | 270 .Bl -tag -width indent
294 .Bl -tag -width indent
347 The fifth group of commands are used to manage controller-wide operations.
350 .Bl -tag -width indent
382 .Bl -tag -width indent
386 Periodic progress updates for long-running operations such as background
421 the controller for each low-level request.
433 .Bl -tag -width indent
462 .Bl -tag -width indent
496 Abort an in-progress rebuild operation on
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/c6x/ |
| H A D | dscr.txt | 2 ------------------------------------
12 enable (and disable in some cases) SoC pin drivers, select peripheral clock
14 write once or the individual bits are write once. In addition to device config,
19 For device state control (enable/disable), each device control is assigned an
24 - compatible: must be "ti,c64x+dscr"
25 - reg: register area base and size
34 - ti,dscr-devstat
37 - ti,dscr-silicon-rev
40 - ti,dscr-rmii-resets
44 - ti,dscr-locked-regs
[all …]
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| /freebsd/sys/dev/sound/pci/ |
| H A D | es137x.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
55 #define DAC2_SRTODIV(x) (((1411200 + (x) / 2) / (x) - 2) & 0x1fff)
76 #define CTRL_DAC1_EN 0x00000040 /* enable DAC1 */
77 #define CTRL_DAC2_EN 0x00000020 /* enable DAC2 */
78 #define CTRL_ADC_EN 0x00000010 /* enable ADC */
79 #define CTRL_UART_EN 0x00000008 /* enable MIDI uart */
80 #define CTRL_JYSTK_EN 0x00000004 /* enable Joystick port (presumably
82 #define CTRL_CDC_EN 0x00000002 /* enable serial (CODEC) interface */
94 #define SCTRL_R1INTEN 0x00000400 /* enable interrupt */
[all …]
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| H A D | envy24.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
29 /* -------------------------------------------------------------------- */
40 #define PCIR_MT 0x1c /* Professional Multi-Track I/O Base Address */
48 #define PCIM_LAC_MPU401 0x0008 /* MPU-401 I/O enable */
49 #define PCIM_LAC_GAME 0x0004 /* Game Port enable (200h) */
50 #define PCIM_LAC_FM 0x0002 /* FM I/O enable (AdLib 388h base) */
51 #define PCIM_LAC_SB 0x0001 /* SB I/O enable */
55 #define PCIM_LCC_SVIDRW 0x0080 /* SVID read/write enable */
56 #define PCIM_LCC_SNPSB 0x0040 /* snoop SB 22C/24Ch I/O write cycle */
[all …]
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| /freebsd/sys/dev/ixgbe/ |
| H A D | ixgbe_api.c | 2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
61 * ixgbe_dcb_get_rtrup2tc - read rtrup2tc reg
69 if (hw->mac.ops.get_rtrup2tc) in ixgbe_dcb_get_rtrup2tc()
70 hw->mac.ops.get_rtrup2tc(hw, map); in ixgbe_dcb_get_rtrup2tc()
74 * ixgbe_init_shared_code - Initialize the shared code
96 switch (hw->mac.type) { in ixgbe_init_shared_code()
130 hw->mac.max_link_up_time = IXGBE_LINK_UP_TIME; in ixgbe_init_shared_code()
136 * ixgbe_set_mac_type - Sets MAC type
148 if (hw->vendor_id != IXGBE_INTEL_VENDOR_ID) { in ixgbe_set_mac_type()
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/bus/ |
| H A D | qcom,ebi2.txt | 4 external memory (such as NAND or other memory-mapped peripherals) whereas
9 data lines (16 bits), OE (output enable), ADV (address valid, used on some
10 NOR flash memories), WE (write enable). This on top of 6 different chip selects
18 Also CS1 and CS2 has -A and -B signals. Why they have that is unclear to me.
24 CS0 GPIO134 0x1a800000-0x1b000000 (8MB)
25 CS1 GPIO39 (A) / GPIO123 (B) 0x1b000000-0x1b800000 (8MB)
26 CS2 GPIO40 (A) / GPIO124 (B) 0x1b800000-0x1c000000 (8MB)
27 CS3 GPIO133 0x1d000000-0x25000000 (128 MB)
28 CS4 GPIO132 0x1c800000-0x1d000000 (8MB)
29 CS5 GPIO131 0x1c000000-0x1c800000 (8MB)
[all …]
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| H A D | qcom,ebi2.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 external memory (such as NAND or other memory-mapped peripherals) whereas
16 data lines (16 bits), OE (output enable), ADV (address valid, used on some
17 NOR flash memories), WE (write enable). This on top of 6 different chip selects
25 Also CS1 and CS2 has -A and -B signals. Why they have that is unclear to me.
31 CS0 GPIO134 0x1a800000-0x1b000000 (8MB)
32 CS1 GPIO39 (A) / GPIO123 (B) 0x1b000000-0x1b800000 (8MB)
33 CS2 GPIO40 (A) / GPIO124 (B) 0x1b800000-0x1c000000 (8MB)
[all …]
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| /freebsd/share/man/man7/ |
| H A D | mitigations.7 | 1 .\"-
2 .\" SPDX-License-Identifer: BSD-2-Clause
42 Some of these mitigations have run-time controls to enable them on a global
43 or per-process basis, some are optionally enabled or disabled at compile time,
48 .Bl -bullet -compac
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| /freebsd/sbin/camcontrol/ |
| H A D | camcontrol.8 | 145 .Bk -words
171 .Op Fl a Ar enable|disable
172 .Op Fl A Ar enable|disable
173 .Op Fl s Ar enable|disable
174 .Op Fl S Ar enable|disable
208 .Op Fl D Ar enable|disable
213 .Op Fl T Ar enable|disable
402 .Bl -tag -width 14n
419 function-specific arguments.
437 .Bl -tag -width 14n
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| /freebsd/share/man/man4/ |
| H A D | ada.4 | 47 concurrently, often re-ordering them to reduce the number and length of
62 Many direct access devices are equipped with read and/or write caches.
68 The read cache is used to store data from device-initiated read ahead
75 The write cache can greatly decrease the latency of write operations
80 lose power while its cache contains uncommitted write operations, these
82 The effect of a loss of write transactions on
83 a file system is non-deterministic and can cause corruption.
85 devices age write transactions to limit the vulnerability to a few transactions
87 systems with write cache enabled devices reside on an Uninterruptible
101 .Bl -tag -width 12
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| H A D | da.4 | 43 The direct access class includes disk, magneto-optical,
44 and solid-state devices.
54 Many direct access devices are equipped with read and/or write caches.
61 The read cache is used to store data from device-initiated read ahead
71 The write cache can greatly decrease the latency of write operations
76 lose power while its cache contains uncommitted write operations, these
78 The effect of a loss of write transactions on
79 a file system is non-deterministic and can cause corruption.
81 devices age write transactions to limit vulnerability to a few transactions
82 recently reported as complete, but it is none-the-less recommended that
[all …]
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| /freebsd/sys/contrib/device-tree/src/arm/intel/ixp/ |
| H A D | intel-ixp42x-arcom-vulcan.dts | 1 // SPDX-License-Identifier: ISC
8 /dts-v1/;
10 #include "intel-ixp42x.dtsi"
11 #include <dt-bindings/input/input.h>
16 #address-cells = <1>;
17 #size-cells = <1>;
27 stdout-path = "uart0:115200n8";
35 compatible = "w1-gpio";
42 compatible = "intel,ixp4xx-flash", "cfi-flash";
43 bank-width = <2>;
[all …]
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| /freebsd/contrib/byacc/test/yacc/ |
| H A D | big_b.error | 1 YACC: w - -B flag unsupported, reconfigure with --enable-btyacc
5 -b file_prefix set filename prefix (default "y.")
6 -B create a backtracking parser
7 -d write definitions (.tab.h)
8 -h print this help-message
9 -H defines_file write definitions to defines_file
10 -i write interface (y.tab.i)
11 -g write a graphical description
12 -l suppress #line directives
13 -L enable position processing, e.g., "%locations"
[all …]
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| H A D | big_l.error | 1 YACC: w - -L flag unsupported, reconfigure with --enable-btyacc
5 -b file_prefix set filename prefix (default "y.")
6 -B create a backtracking parser
7 -d write definitions (.tab.h)
8 -h print this help-message
9 -H defines_file write definitions to defines_file
10 -i write interface (y.tab.i)
11 -g write a graphical description
12 -l suppress #line directives
13 -L enable position processing, e.g., "%locations"
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/serio/ |
| H A D | ps2-gpio.txt | 1 Device-Tree binding for ps/2 gpio device
4 - compatible = "ps2-gpio"
5 - data-gpios: the data pin
6 - clk-gpios: the clock pin
7 - interrupts: Should trigger on the falling edge of the clock line.
10 - write-enable: Indicates whether write function is provided
11 to serio device. Possibly providing the write fn will not work, because
17 compatible = "ps2-gpio";
18 interrupt-parent = <&gpio>;
20 data-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
[all …]
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