Lines Matching +full:write +full:- +full:enable
1 /* SPDX-License-Identifier: GPL-2.0 */
32 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
38 /* Write Register 0 */
69 /* Write Register 1 */
71 #define EXT_INT_ENAB 0x1 /* Ext Int Enable */
72 #define TxINT_ENAB 0x2 /* Tx Int Enable */
83 #define WT_RDY_ENAB 0x80 /* Wait/Ready Enable */
85 /* Write Register #2 (Interrupt Vector) */
87 /* Write Register 3 */
89 #define RxENAB 0x1 /* Rx Enable */
92 #define RxCRC_ENAB 0x8 /* Rx CRC Enable */
101 /* Write Register 4 */
103 #define PAR_ENAB 0x1 /* Parity Enable */
106 #define SYNC_ENAB 0 /* Sync Modes Enable */
122 /* Write Register 5 */
124 #define TxCRC_ENAB 0x1 /* Tx CRC Enable */
126 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
127 #define TxENAB 0x8 /* Tx Enable */
136 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
138 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
140 /* Write Register 8 (transmit buffer) */
142 /* Write Register 9 (Master interrupt control) */
146 #define MIE 8 /* Master Interrupt Enable */
148 #define NORESET 0 /* No reset on write to R9 */
153 /* Write Register 10 (misc control bits) */
165 /* Write Register 11 (Clock Mode control) */
181 /* Write Register 12 (lower byte of baud rate generator time constant) */
183 /* Write Register 13 (upper byte of baud rate generator time constant) */
185 /* Write Register 14 (Misc control bits) */
186 #define BRENAB 1 /* Baud rate generator enable */
199 /* Write Register 15 (external/status interrupt control) */
235 /* Read Register 2 (channel b only) - Interrupt vector */
269 #define ZS_CLEARERR(channel) do { writeb(ERR_RES, &channel->control); \
272 #define ZS_CLEARSTAT(channel) do { writeb(RES_EXT_INT, &channel->control); \
275 #define ZS_CLEARFIFO(channel) do { readb(&channel->data); \
277 readb(&channel->data); \
279 readb(&channel->data); \