Lines Matching +full:write +full:- +full:enable
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2009 - Maxim Levitsky
15 byte write/read does one cycle on nand data lines.
16 dword write/read does 4 cycles
19 If write was done two dword reads read generated ecc checksums
26 #define R852_CTL_DATA 0x02 /* read/write data (#ALE)*/
30 #define R852_CTL_CARDENABLE 0x10 /* probably (#CE) - always set*/
31 #define R852_CTL_ECC_ENABLE 0x20 /* enable ecc engine */
32 #define R852_CTL_ECC_ACCESS 0x40 /* read/write ecc via reg #0*/
42 #define R852_CARD_STA_BUSY 0x80 /* card is busy - (#R/B) */
44 /* card detection irq status & enable*/
46 #define R852_CARD_IRQ_ENABLE 0x07 /* IRQ enable */
52 #define R852_CARD_IRQ_GENABLE 0x80 /* general enable */
57 /* hardware enable */
71 /* physical DMA address - 32 bit value*/
77 #define R852_DMA_MEMORY 0x01 /* (memory <-> internal hw buffer) */
78 #define R852_DMA_READ 0x02 /* 0 = write, 1 = read */
79 #define R852_DMA_INTERNAL 0x04 /* (internal hw buffer <-> card) */
84 /* dma IRQ enable */
87 #define R852_DMA_IRQ_MEMORY 0x01 /* (memory <-> internal hw buffer) */
89 #define R852_DMA_IRQ_INTERNAL 0x04 /* (internal hw buffer <-> card) */
93 /* ECC syndrome format - read from reg #0 will return two copies of these for
97 #define R852_ECC_CORRECT 0x10 /* no errors - (guessed) */
119 int dma_dir; /* 1 = read, 0 = write */
120 int dma_stage; /* 0 - idle, 1 - first step,
121 2 - second step */