Lines Matching +full:write +full:- +full:enable

1 /* SPDX-License-Identifier: GPL-2.0 */
34 	u8		regs[ZS_NUM_REGS];	/* Channel write registers.  */
38  * Per-SCC state for locking and the interrupt handler.
53 #define ZS_BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
59 /* Write Register 0 (Command) */
90 /* Write Register 1 (Tx/Rx/Ext Int Enable and WAIT/DMA Commands) */
91 #define EXT_INT_ENAB	0x1	/* Ext Int Enable */
92 #define TxINT_ENAB	0x2	/* Tx Int Enable */
103 #define WT_RDY_ENAB	0x80	/* Wait/Ready Enable */
105 /* Write Register 2 (Interrupt Vector) */
107 /* Write Register 3 (Receive Parameters and Control) */
108 #define RxENABLE	0x1	/* Rx Enable */
111 #define RxCRC_ENAB	0x8	/* Rx CRC Enable */
120 /* Write Register 4 (Transmit/Receive Miscellaneous Parameters and Modes) */
121 #define PAR_ENA		0x1	/* Parity Enable */
124 #define SYNC_ENAB	0	/* Sync Modes Enable */
141 /* Write Register 5 (Transmit Parameters and Controls) */
142 #define TxCRC_ENAB	0x1	/* Tx CRC Enable */
144 #define SDLC_CRC	0x4	/* SDLC/CRC-16 */
145 #define TxENAB		0x8	/* Tx Enable */
154 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
156 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
158 /* Write Register 8 (Transmit Buffer) */
160 /* Write Register 9 (Master Interrupt Control) */
164 #define MIE		8	/* Master Interrupt Enable */
167 #define NORESET		0	/* No reset on write to R9 */
172 /* Write Register 10 (Miscellaneous Transmitter/Receiver Control Bits) */
184 /* Write Register 11 (Clock Mode Control) */
200 /* Write Register 12 (Lower Byte of Baud Rate Generator Time Constant) */
202 /* Write Register 13 (Upper Byte of Baud Rate Generator Time Constant) */
204 /* Write Register 14 (Miscellaneous Control Bits) */
205 #define BRENABL		1	/* Baud rate generator enable */
218 /* Write Register 15 (External/Status Interrupt Control) */
219 #define WR7P_EN		1	/* WR7 Prime SDLC Feature Enable */
255 /* Read Register 2 (Interrupt Vector (WR2) -- channel A).  */
257 /* Read Register 2 (Modified Interrupt Vector -- channel B).  */
259 /* Read Register 3 (Interrupt Pending Bits -- channel A only).  */