Lines Matching +full:write +full:- +full:enable
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
21 * - IFC version 1.0 implements 4 banks.
22 * - IFC version 1.1 onward implements 8 banks.
35 * CSPR - Chip Select Property Register
47 /* Write Protect */
69 (__ilog2(n) - IFC_AMASK_SHIFT))
74 /* Enable ECC Encoder */
81 /* Enable ECC Decoder */
110 #define CSOR_NAND_PB(n) ((__ilog2(n) - 5) << CSOR_NAND_PB_SHIFT)
111 /* Time for Read Enable High to Output High Impedance */
123 * Chip Select Option Register - NOR Flash Mode
125 /* Enable Address shift Mode */
127 /* Page Read Enable from NOR device */
129 /* AVD Toggle Enable during Burst Program */
138 /* Time for Read Enable High to Output High Impedance */
150 * Chip Select Option Register - GPCM Mode
152 /* GPCM Mode - Normal */
154 /* GPCM Mode - GenericASIC */
158 /* Parity Checking enable/disable */
163 #define CSOR_GPCM_GPTO(n) ((__ilog2(n) - 8) << CSOR_GPCM_GPTO_SHIFT)
166 /* GPCM External Access Termination mode for write access */
175 #define CSOR_GPCM_GAPERRD(n) (((n) - 1) << CSOR_GPCM_GAPERRD_SHIFT)
176 /* Time for Read Enable High to Output High Impedance */
212 * Common Event and Error Enable Register (CM_EVTER_EN)
214 /* Chip select error checking enable */
218 * Common Event and Error Interrupt Enable Register (CM_EVTER_INTR_EN)
220 /* Chip select error interrupt enable */
224 * Common Transfer Error Attribute Register-0 (CM_ERATTR0)
226 /* transaction type of error Read/Write */
240 #define IFC_CCR_CLK_DIV(n) ((n-1) << IFC_CCR_CLK_DIV_SHIFT)
266 /* Addressing Mode-ROW0+n/COL0 */
268 /* Addressing Mode-ROW0+n/COL0+n */
281 /* General purpose FCM flash command bytes CMD0-CMD7 */
310 /* Byte Count for read/Write */
316 /* NAND Machine specific opcodes OP0-OP14*/
350 * in FIR registers- 6bits
422 /* Write Protect Error */
438 /* Small Page 0-15 Done */
439 #define PGRDCMPL_EVT_STAT_SECTION_SP(n) (1 << (31 - (n)))
440 /* Large Page(2K) 0-3 Done */
441 #define PGRDCMPL_EVT_STAT_LP_2K(n) (0xF << (28 - (n)*4))
442 /* Large Page(4K) 0-1 Done */
443 #define PGRDCMPL_EVT_STAT_LP_4K(n) (0xFF << (24 - (n)*8))
446 * NAND Event and Error Enable Register (NAND_EVTER_EN)
448 /* Operation complete event enable */
450 /* Page read complete event enable */
452 /* Flash Timeout error enable */
454 /* Write Protect error enable */
456 /* ECC error logging enable */
460 * NAND Event and Error Interrupt Enable Register (NAND_EVTER_INTR_EN)
462 /* Enable interrupt for operation complete */
464 /* Enable interrupt for Page read complete */
466 /* Enable interrupt for Flash timeout error */
468 /* Enable interrupt for Write protect error */
470 /* Enable interrupt for ECC error*/
474 * NAND Transfer Error Attribute Register-0 (NAND_ERATTR0)
477 /* Error on CS0-3 for NAND */
482 /* Transaction type of error Read/Write */
494 * ECC Error Status Registers (ECCSTAT0-ECCSTAT3)
496 /* Number of ECC errors on sector n (n = 0-15) */
535 #define IFC_NAND_NCR_FTOCNT(n) ((_ilog2(n) - 8) << IFC_NAND_NCR_FTOCNT_SHIFT)
561 /* Write Protect Error */
567 * NOR Event and Error Enable Register (NOR_EVTER_EN)
569 /* NOR Command Seq complete event enable */
571 /* Write Protect Error Checking Enable */
573 /* Timeout Error Enable */
577 * NOR Event and Error Interrupt Enable Register (NOR_EVTER_INTR_EN)
579 /* Enable interrupt for OPC complete */
581 /* Enable interrupt for write protect error */
583 /* Enable interrupt for timeout error */
587 * NOR Transfer Error Attribute Register-0 (NOR_ERATTR0)
598 /* Type of transaction read/write */
602 * NOR Transfer Error Attribute Register-2 (NOR_ERATTR2)
614 #define IFC_NORCR_NUM_PHASE(n) ((n-1) << IFC_NORCR_NUM_PHASE_SHIFT)
618 #define IFC_NORCR_STOCNT(n) ((__ilog2(n) - 8) << IFC_NORCR_STOCNT_SHIFT)
632 * GPCM Event and Error Enable Register (GPCM_EVTER_EN)
634 /* Timeout error enable */
636 /* Parity error enable */
640 * GPCM Event and Error Interrupt Enable Register (GPCM_EVTER_INTR_EN)
642 /* Enable Interrupt for timeout error */
644 /* Enable Interrupt for Parity error */
648 * GPCM Transfer Error Attribute Register-0 (GPCM_ERATTR0)
659 /* Type of transaction read/Write */
663 * GPCM Transfer Error Attribute Register-2 (GPCM_ERATTR2)
857 if (fsl_ifc_ctrl_dev->little_endian) in ifc_in32()
869 if (fsl_ifc_ctrl_dev->little_endian) in ifc_in16()
884 if (fsl_ifc_ctrl_dev->little_endian) in ifc_out32()
892 if (fsl_ifc_ctrl_dev->little_endian) in ifc_out16()