Lines Matching +full:write +full:- +full:enable
1 /* SPDX-License-Identifier: GPL-2.0 */
8 #include "pci-sh7780.h"
10 #include "pci-sh7751.h"
16 #define SH4_PCICR_PREFIX 0xA5000000 /* CR prefix for write */
17 #define SH4_PCICR_FTO 0x00000400 /* TRDY/IRDY Enable */
20 #define SH4_PCICR_PLUP 0x00000080 /* Enable PCI Pullup */
38 #define SH4_PCIINT_TWDP 0x00000020 /* Tgt. Write Parity Error */
40 #define SH4_PCIINT_MTABT 0x00000008 /* Master-Tgt. Abort Error */
41 #define SH4_PCIINT_MMABT 0x00000004 /* Master-Master Abort Error */
42 #define SH4_PCIINT_MWPD 0x00000002 /* Master Write PERR Detect */
45 #define SH4_PCIINTM_TTADIM BIT(14) /* Target-target abort interrupt */
50 #define SH4_PCIINTM_DPEITWM BIT(5) /* Data parity error for target write */
54 #define SH4_PCIINTM_MWPDIM BIT(1) /* Master write data parity error */
72 #define SH4_PCIAINT_WDPE 0x00000001 /* Write Data Parity Error */
81 #define SH4_PCIDMABT_RRBN 0x00000001 /* DMA Arbitor Round-Robin */
109 #define SH4_PCIPAR_CFGEN 0x80000000 /* Configuration Enable */
138 #define SH4_PCIPCTR_P2EN 0x000400000 /* Port 2 Enable */
139 #define SH4_PCIPCTR_P1EN 0x000200000 /* Port 1 Enable */
140 #define SH4_PCIPCTR_P0EN 0x000100000 /* Port 0 Enable */
141 #define SH4_PCIPCTR_P2UP 0x000000020 /* Port2 Pull Up Enable */
142 #define SH4_PCIPCTR_P2IO 0x000000010 /* Port2 Output Enable */
143 #define SH4_PCIPCTR_P1UP 0x000000008 /* Port1 Pull Up Enable */
144 #define SH4_PCIPCTR_P1IO 0x000000004 /* Port1 Output Enable */
145 #define SH4_PCIPCTR_P0UP 0x000000002 /* Port0 Pull Up Enable */
146 #define SH4_PCIPCTR_P0IO 0x000000001 /* Port0 Output Enable */
148 #define SH4_PCIPDTR_PB5 0x000000020 /* Port 5 Enable */
149 #define SH4_PCIPDTR_PB4 0x000000010 /* Port 4 Enable */
150 #define SH4_PCIPDTR_PB3 0x000000008 /* Port 3 Enable */
151 #define SH4_PCIPDTR_PB2 0x000000004 /* Port 2 Enable */
152 #define SH4_PCIPDTR_PB1 0x000000002 /* Port 1 Enable */
153 #define SH4_PCIPDTR_PB0 0x000000001 /* Port 0 Enable */
156 /* arch/sh/kernel/drivers/pci/ops-sh4.c */
173 __raw_writel(val, chan->reg_base + reg); in pci_write_reg()
179 return __raw_readl(chan->reg_base + reg); in pci_read_reg()