18cee26f8SGreg Ungerer /* 28cee26f8SGreg Ungerer * mcfmmu.h -- definitions for the ColdFire v4e MMU 38cee26f8SGreg Ungerer * 48cee26f8SGreg Ungerer * (C) Copyright 2011, Greg Ungerer <gerg@uclinux.org> 58cee26f8SGreg Ungerer * 68cee26f8SGreg Ungerer * This file is subject to the terms and conditions of the GNU General Public 78cee26f8SGreg Ungerer * License. See the file COPYING in the main directory of this archive 88cee26f8SGreg Ungerer * for more details. 98cee26f8SGreg Ungerer */ 108cee26f8SGreg Ungerer 118cee26f8SGreg Ungerer #ifndef MCFMMU_H 128cee26f8SGreg Ungerer #define MCFMMU_H 138cee26f8SGreg Ungerer 148cee26f8SGreg Ungerer /* 158cee26f8SGreg Ungerer * The MMU support registers are mapped into the address space using 168cee26f8SGreg Ungerer * the processor MMUBASE register. We used a fixed address for mapping, 178cee26f8SGreg Ungerer * there doesn't seem any need to make this configurable yet. 188cee26f8SGreg Ungerer */ 198cee26f8SGreg Ungerer #define MMUBASE 0xfe000000 208cee26f8SGreg Ungerer 218cee26f8SGreg Ungerer /* 228cee26f8SGreg Ungerer * The support registers of the MMU. Names are the sames as those 238cee26f8SGreg Ungerer * used in the Freescale v4e documentation. 248cee26f8SGreg Ungerer */ 258cee26f8SGreg Ungerer #define MMUCR (MMUBASE + 0x00) /* Control register */ 268cee26f8SGreg Ungerer #define MMUOR (MMUBASE + 0x04) /* Operation register */ 278cee26f8SGreg Ungerer #define MMUSR (MMUBASE + 0x08) /* Status register */ 288cee26f8SGreg Ungerer #define MMUAR (MMUBASE + 0x10) /* TLB Address register */ 298cee26f8SGreg Ungerer #define MMUTR (MMUBASE + 0x14) /* TLB Tag register */ 308cee26f8SGreg Ungerer #define MMUDR (MMUBASE + 0x18) /* TLB Data register */ 318cee26f8SGreg Ungerer 328cee26f8SGreg Ungerer /* 338cee26f8SGreg Ungerer * MMU Control register bit flags 348cee26f8SGreg Ungerer */ 358cee26f8SGreg Ungerer #define MMUCR_EN 0x00000001 /* Virtual mode enable */ 368cee26f8SGreg Ungerer #define MMUCR_ASM 0x00000002 /* Address space mode */ 378cee26f8SGreg Ungerer 388cee26f8SGreg Ungerer /* 398cee26f8SGreg Ungerer * MMU Operation register. 408cee26f8SGreg Ungerer */ 4186a8280aSAndrea Gelmini #define MMUOR_UAA 0x00000001 /* Update allocation address */ 428cee26f8SGreg Ungerer #define MMUOR_ACC 0x00000002 /* TLB access */ 438cee26f8SGreg Ungerer #define MMUOR_RD 0x00000004 /* TLB access read */ 448cee26f8SGreg Ungerer #define MMUOR_WR 0x00000000 /* TLB access write */ 458cee26f8SGreg Ungerer #define MMUOR_ADR 0x00000008 /* TLB address select */ 468cee26f8SGreg Ungerer #define MMUOR_ITLB 0x00000010 /* ITLB operation */ 478cee26f8SGreg Ungerer #define MMUOR_CAS 0x00000020 /* Clear non-locked ASID TLBs */ 488cee26f8SGreg Ungerer #define MMUOR_CNL 0x00000040 /* Clear non-locked TLBs */ 498cee26f8SGreg Ungerer #define MMUOR_CA 0x00000080 /* Clear all TLBs */ 508cee26f8SGreg Ungerer #define MMUOR_STLB 0x00000100 /* Search TLBs */ 518cee26f8SGreg Ungerer #define MMUOR_AAN 16 /* TLB allocation address */ 528cee26f8SGreg Ungerer #define MMUOR_AAMASK 0xffff0000 /* AA mask */ 538cee26f8SGreg Ungerer 548cee26f8SGreg Ungerer /* 558cee26f8SGreg Ungerer * MMU Status register. 568cee26f8SGreg Ungerer */ 578cee26f8SGreg Ungerer #define MMUSR_HIT 0x00000002 /* Search TLB hit */ 588cee26f8SGreg Ungerer #define MMUSR_WF 0x00000008 /* Write access fault */ 598cee26f8SGreg Ungerer #define MMUSR_RF 0x00000010 /* Read access fault */ 608cee26f8SGreg Ungerer #define MMUSR_SPF 0x00000020 /* Supervisor protect fault */ 618cee26f8SGreg Ungerer 628cee26f8SGreg Ungerer /* 638cee26f8SGreg Ungerer * MMU Read/Write Tag register. 648cee26f8SGreg Ungerer */ 658cee26f8SGreg Ungerer #define MMUTR_V 0x00000001 /* Valid */ 668cee26f8SGreg Ungerer #define MMUTR_SG 0x00000002 /* Shared global */ 678cee26f8SGreg Ungerer #define MMUTR_IDN 2 /* Address Space ID */ 688cee26f8SGreg Ungerer #define MMUTR_IDMASK 0x000003fc /* ASID mask */ 698cee26f8SGreg Ungerer #define MMUTR_VAN 10 /* Virtual Address */ 708cee26f8SGreg Ungerer #define MMUTR_VAMASK 0xfffffc00 /* VA mask */ 718cee26f8SGreg Ungerer 728cee26f8SGreg Ungerer /* 738cee26f8SGreg Ungerer * MMU Read/Write Data register. 748cee26f8SGreg Ungerer */ 758cee26f8SGreg Ungerer #define MMUDR_LK 0x00000002 /* Lock entry */ 768cee26f8SGreg Ungerer #define MMUDR_X 0x00000004 /* Execute access enable */ 778cee26f8SGreg Ungerer #define MMUDR_W 0x00000008 /* Write access enable */ 788cee26f8SGreg Ungerer #define MMUDR_R 0x00000010 /* Read access enable */ 798cee26f8SGreg Ungerer #define MMUDR_SP 0x00000020 /* Supervisor access enable */ 808cee26f8SGreg Ungerer #define MMUDR_CM_CWT 0x00000000 /* Cachable write thru */ 818cee26f8SGreg Ungerer #define MMUDR_CM_CCB 0x00000040 /* Cachable copy back */ 828cee26f8SGreg Ungerer #define MMUDR_CM_NCP 0x00000080 /* Non-cachable precise */ 838cee26f8SGreg Ungerer #define MMUDR_CM_NCI 0x000000c0 /* Non-cachable imprecise */ 848cee26f8SGreg Ungerer #define MMUDR_SZ_1MB 0x00000000 /* 1MB page size */ 858cee26f8SGreg Ungerer #define MMUDR_SZ_4KB 0x00000100 /* 4kB page size */ 868cee26f8SGreg Ungerer #define MMUDR_SZ_8KB 0x00000200 /* 8kB page size */ 878cee26f8SGreg Ungerer #define MMUDR_SZ_1KB 0x00000300 /* 1kB page size */ 888cee26f8SGreg Ungerer #define MMUDR_PAN 10 /* Physical address */ 898cee26f8SGreg Ungerer #define MMUDR_PAMASK 0xfffffc00 /* PA mask */ 908cee26f8SGreg Ungerer 918cee26f8SGreg Ungerer #ifndef __ASSEMBLY__ 928cee26f8SGreg Ungerer 938cee26f8SGreg Ungerer /* 948cee26f8SGreg Ungerer * Simple access functions for the MMU registers. Nothing fancy 958cee26f8SGreg Ungerer * currently required, just simple 32bit access. 968cee26f8SGreg Ungerer */ mmu_read(u32 a)978cee26f8SGreg Ungererstatic inline u32 mmu_read(u32 a) 988cee26f8SGreg Ungerer { 998cee26f8SGreg Ungerer return *((volatile u32 *) a); 1008cee26f8SGreg Ungerer } 1018cee26f8SGreg Ungerer mmu_write(u32 a,u32 v)1028cee26f8SGreg Ungererstatic inline void mmu_write(u32 a, u32 v) 1038cee26f8SGreg Ungerer { 1048cee26f8SGreg Ungerer *((volatile u32 *) a) = v; 1058cee26f8SGreg Ungerer __asm__ __volatile__ ("nop"); 1068cee26f8SGreg Ungerer } 1078cee26f8SGreg Ungerer 108f7116065SGreg Ungerer void cf_bootmem_alloc(void); 109*34fa9b21SGreg Ungerer void cf_mmu_context_init(void); 110066bf87bSGreg Ungerer int cf_tlb_miss(struct pt_regs *regs, int write, int dtlb, int extension_word); 111066bf87bSGreg Ungerer 1128cee26f8SGreg Ungerer #endif 1138cee26f8SGreg Ungerer 1148cee26f8SGreg Ungerer #endif /* MCFMMU_H */ 115