Lines Matching +full:write +full:- +full:enable
1 /* SPDX-License-Identifier: GPL-2.0 */
3 * FILE SA-1100.h
9 * System StrongARM SA-1100
12 * SA-1100 microprocessor (Advanced RISC Machine (ARM)
14 * StrongARM SA-1100 data sheet version 2.2.
21 #error You must include hardware.h not SA-1100.h
81 * Controller (UDC) Control Register (read/write).
83 * Controller (UDC) Address Register (read/write).
86 * (read/write).
89 * (read/write).
91 * Controller (UDC) Control/Status register end-point 0
92 * (read/write).
94 * Controller (UDC) Control/Status register end-point 1
95 * (output, read/write).
97 * Controller (UDC) Control/Status register end-point 2
98 * (input, read/write).
100 * Controller (UDC) Data register end-point 0
101 * (read/write).
103 * Controller (UDC) Write Count register end-point 0
106 * Controller (UDC) Data Register (read/write).
108 * Controller (UDC) Status Register (read/write).
115 #define Ser0UDCCS0 __REG(0x80000010) /* Ser. port 0 UDC Control/Status reg. end-point 0 */
116 #define Ser0UDCCS1 __REG(0x80000014) /* Ser. port 0 UDC Control/Status reg. end-point 1 (output) */
117 #define Ser0UDCCS2 __REG(0x80000018) /* Ser. port 0 UDC Control/Status reg. end-point 2 (input) */
118 #define Ser0UDCD0 __REG(0x8000001C) /* Ser. port 0 UDC Data reg. end-point 0 */
119 #define Ser0UDCWC __REG(0x80000020) /* Ser. port 0 UDC Write Count reg. end-point 0 */
126 #define UDCCR_EIM 0x00000008 /* End-point 0 Interrupt Mask */
139 #define UDCOMP_OUTMAXP Fld (8, 0) /* OUTput MAXimum Packet size - 1 */
143 (((Size) - 1) << FShft (UDCOMP_OUTMAXP))
145 #define UDCIMP_INMAXP Fld (8, 0) /* INput MAXimum Packet size - 1 */
149 (((Size) - 1) << FShft (UDCIMP_INMAXP))
158 /* (write) */
159 #define UDCCS0_SSE 0x00000080 /* Serviced Setup End (write) */
161 #define UDCCS1_RFS 0x00000001 /* Receive FIFO 12-bytes or more */
169 #define UDCCS2_TFS 0x00000001 /* Transmit FIFO 8-bytes or less */
173 #define UDCCS2_TUR 0x00000008 /* Transmit FIFO Under-Run */
179 #define UDCWC_WC Fld (4, 0) /* Write Count */
183 #define UDCSR_EIR 0x00000001 /* End-point 0 Interrupt Request */
197 * (read/write).
200 * (read/write).
203 * (read/write).
206 * (read/write).
209 * (read/write).
212 * (read/write).
218 * (read/write).
221 * (read/write).
224 * (read/write).
227 * (read/write).
230 * (read/write).
233 * (read/write).
236 * (read/write).
242 * (read/write).
245 * (read/write).
248 * (read/write).
251 * (read/write).
254 * (read/write).
257 * (read/write).
267 #define _UTCR0(Nb) __REG(0x80010000 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 0 [1..3] */
268 #define _UTCR1(Nb) __REG(0x80010004 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 1 [1..3] */
269 #define _UTCR2(Nb) __REG(0x80010008 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 2 [1..3] */
270 #define _UTCR3(Nb) __REG(0x8001000C + ((Nb) - 1)*0x00020000) /* UART Control Reg. 3 [1..3] */
271 #define _UTCR4(Nb) __REG(0x80010010 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 4 [2] */
272 #define _UTDR(Nb) __REG(0x80010014 + ((Nb) - 1)*0x00020000) /* UART Data Reg. [1..3] */
273 #define _UTSR0(Nb) __REG(0x8001001C + ((Nb) - 1)*0x00020000) /* UART Status Reg. 0 [1..3] */
274 #define _UTSR1(Nb) __REG(0x80010020 + ((Nb) - 1)*0x00020000) /* UART Status Reg. 1 [1..3] */
315 #define UTCR0_PE 0x00000001 /* Parity Enable */
323 #define UTCR0_7BitData (UTCR0_DSS*0) /* 7-Bit Data */
324 #define UTCR0_8BitData (UTCR0_DSS*1) /* 8-Bit Data */
325 #define UTCR0_SCE 0x00000010 /* Sample Clock Enable */
329 #define UTCR0_RcRsEdg (UTCR0_RCE*0) /* Receive clock Rising-Edge */
330 #define UTCR0_RcFlEdg (UTCR0_RCE*1) /* Receive clock Falling-Edge */
332 #define UTCR0_TrRsEdg (UTCR0_TCE*0) /* Transmit clock Rising-Edge */
333 #define UTCR0_TrFlEdg (UTCR0_TCE*1) /* Transmit clock Falling-Edge */
337 #define UTCR1_BRD Fld (4, 0) /* Baud Rate Divisor/16 - 1 [11:8] */
338 #define UTCR2_BRD Fld (8, 0) /* Baud Rate Divisor/16 - 1 [7:0] */
342 (((Div) - 16)/16 >> FSize (UTCR2_BRD) << \
345 (((Div) - 16)/16 & FAlnMsk (UTCR2_BRD) << \
350 (((Div) - 1)/16 >> FSize (UTCR2_BRD) << \
353 (((Div) - 1)/16 & FAlnMsk (UTCR2_BRD) << \
358 #define UTCR3_RXE 0x00000001 /* Receive Enable */
359 #define UTCR3_TXE 0x00000002 /* Transmit Enable */
361 #define UTCR3_RIE 0x00000008 /* Receive FIFO 1/3-to-2/3-full or */
362 /* more Interrupt Enable */
363 #define UTCR3_TIE 0x00000010 /* Transmit FIFO 1/2-full or less */
364 /* Interrupt Enable */
365 #define UTCR3_LBM 0x00000020 /* Look-Back Mode */
370 #define UTCR4_HSE 0x00000001 /* Hewlett-Packard Serial InfraRed */
371 /* (HP-SIR) modulation Enable */
372 #define UTCR4_NRZ (UTCR4_HSE*0) /* Non-Return to Zero modulation */
373 #define UTCR4_HPSIR (UTCR4_HSE*1) /* HP-SIR modulation */
374 #define UTCR4_LPM 0x00000002 /* Low-Power Mode */
382 #define UTDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */
385 #define UTSR0_TFS 0x00000001 /* Transmit FIFO 1/2-full or less */
387 #define UTSR0_RFS 0x00000002 /* Receive FIFO 1/3-to-2/3-full or */
399 #define UTSR1_ROR 0x00000020 /* Receive FIFO Over-Run (read) */
407 * Control Register 0 (read/write).
409 * Control Register 1 (read/write).
411 * Control Register 2 (read/write).
413 * Control Register 3 (read/write).
415 * Control Register 4 (read/write).
417 * Data Register (read/write).
419 * Status Register 0 (read/write).
421 * Status Register 1 (read/write).
444 #define SDCR0_LBM 0x00000004 /* Look-Back Mode */
447 #define SDCR0_NRZ (SDCR0_BMS*1) /* Non-Return to Zero modulation */
448 #define SDCR0_SCE 0x00000010 /* Sample Clock Enable (GPIO [16]) */
454 #define SDCR0_RcRsEdg (SDCR0_RCE*0) /* Receive clock Rising-Edge */
455 #define SDCR0_RcFlEdg (SDCR0_RCE*1) /* Receive clock Falling-Edge */
457 #define SDCR0_TrRsEdg (SDCR0_TCE*0) /* Transmit clock Rising-Edge */
458 #define SDCR0_TrFlEdg (SDCR0_TCE*1) /* Transmit clock Falling-Edge */
460 #define SDCR1_AAF 0x00000001 /* Abort After Frame enable */
462 #define SDCR1_TXE 0x00000002 /* Transmit Enable */
463 #define SDCR1_RXE 0x00000004 /* Receive Enable */
464 #define SDCR1_RIE 0x00000008 /* Receive FIFO 1/3-to-2/3-full or */
465 /* more Interrupt Enable */
466 #define SDCR1_TIE 0x00000010 /* Transmit FIFO 1/2-full or less */
467 /* Interrupt Enable */
468 #define SDCR1_AME 0x00000020 /* Address Match Enable */
469 #define SDCR1_TUS 0x00000040 /* Transmit FIFO Under-run Select */
470 #define SDCR1_EFrmURn (SDCR1_TUS*0) /* End Frame on Under-Run */
471 #define SDCR1_AbortURn (SDCR1_TUS*1) /* Abort on Under-Run */
472 #define SDCR1_RAE 0x00000080 /* Receive Abort interrupt Enable */
476 #define SDCR3_BRD Fld (4, 0) /* Baud Rate Divisor/16 - 1 [11:8] */
477 #define SDCR4_BRD Fld (8, 0) /* Baud Rate Divisor/16 - 1 [7:0] */
481 (((Div) - 16)/16 >> FSize (SDCR4_BRD) << \
484 (((Div) - 16)/16 & FAlnMsk (SDCR4_BRD) << \
489 (((Div) - 1)/16 >> FSize (SDCR4_BRD) << \
492 (((Div) - 1)/16 & FAlnMsk (SDCR4_BRD) << \
499 #define SDDR_EOF 0x00000100 /* receive End-Of-Frame (read) */
501 #define SDDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */
505 #define SDSR0_TUR 0x00000002 /* Transmit FIFO Under-Run */
507 #define SDSR0_TFS 0x00000008 /* Transmit FIFO 1/2-full or less */
509 #define SDSR0_RFS 0x00000010 /* Receive FIFO 1/3-to-2/3-full or */
517 #define SDSR1_EOF 0x00000020 /* receive End-Of-Frame (read) */
519 #define SDSR1_ROR 0x00000080 /* Receive FIFO Over-Run (read) */
523 * High-Speed Serial to Parallel controller (HSSP) control registers
526 * Ser2HSCR0 Serial port 2 High-Speed Serial to Parallel
527 * controller (HSSP) Control Register 0 (read/write).
528 * Ser2HSCR1 Serial port 2 High-Speed Serial to Parallel
529 * controller (HSSP) Control Register 1 (read/write).
530 * Ser2HSDR Serial port 2 High-Speed Serial to Parallel
531 * controller (HSSP) Data Register (read/write).
532 * Ser2HSSR0 Serial port 2 High-Speed Serial to Parallel
533 * controller (HSSP) Status Register 0 (read/write).
534 * Ser2HSSR1 Serial port 2 High-Speed Serial to Parallel
536 * Ser2HSCR2 Serial port 2 High-Speed Serial to Parallel
537 * controller (HSSP) Control Register 2 (read/write).
540 * SA-1100.]
553 #define HSCR0_LBM 0x00000002 /* Look-Back Mode */
554 #define HSCR0_TUS 0x00000004 /* Transmit FIFO Under-run Select */
555 #define HSCR0_EFrmURn (HSCR0_TUS*0) /* End Frame on Under-Run */
556 #define HSCR0_AbortURn (HSCR0_TUS*1) /* Abort on Under-Run */
557 #define HSCR0_TXE 0x00000008 /* Transmit Enable */
558 #define HSCR0_RXE 0x00000010 /* Receive Enable */
559 #define HSCR0_RIE 0x00000020 /* Receive FIFO 2/5-to-3/5-full or */
560 /* more Interrupt Enable */
561 #define HSCR0_TIE 0x00000040 /* Transmit FIFO 1/2-full or less */
562 /* Interrupt Enable */
563 #define HSCR0_AME 0x00000080 /* Address Match Enable */
569 #define HSDR_EOF 0x00000100 /* receive End-Of-Frame (read) */
571 #define HSDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */
575 #define HSSR0_TUR 0x00000002 /* Transmit FIFO Under-Run */
577 #define HSSR0_TFS 0x00000008 /* Transmit FIFO 1/2-full or less */
579 #define HSSR0_RFS 0x00000010 /* Receive FIFO 2/5-to-3/5-full or */
587 #define HSSR1_EOF 0x00000010 /* receive End-Of-Frame (read) */
589 #define HSSR1_ROR 0x00000040 /* Receive FIFO Over-Run (read) */
595 /* (non-inverted) */
600 /* (non-inverted) */
604 * Multi-media Communications Port (MCP) control registers
607 * Ser4MCCR0 Serial port 4 Multi-media Communications Port (MCP)
608 * Control Register 0 (read/write).
609 * Ser4MCDR0 Serial port 4 Multi-media Communications Port (MCP)
610 * Data Register 0 (audio, read/write).
611 * Ser4MCDR1 Serial port 4 Multi-media Communications Port (MCP)
612 * Data Register 1 (telecom, read/write).
613 * Ser4MCDR2 Serial port 4 Multi-media Communications Port (MCP)
614 * Data Register 2 (CODEC registers, read/write).
615 * Ser4MCSR Serial port 4 Multi-media Communications Port (MCP)
616 * Status Register (read/write).
617 * Ser4MCCR1 Serial port 4 Multi-media Communications Port (MCP)
618 * Control Register 1 (read/write).
621 * SA-1100.]
663 #define MCCR0_MCE 0x00010000 /* MCP Enable */
671 #define MCCR0_TTE 0x00080000 /* Telecom Transmit FIFO 1/2-full */
672 /* or less interrupt Enable */
673 #define MCCR0_TRE 0x00100000 /* Telecom Receive FIFO 1/2-full */
674 /* or more interrupt Enable */
675 #define MCCR0_ATE 0x00200000 /* Audio Transmit FIFO 1/2-full */
676 /* or less interrupt Enable */
677 #define MCCR0_ARE 0x00400000 /* Audio Receive FIFO 1/2-full or */
678 /* more interrupt Enable */
679 #define MCCR0_LBM 0x00800000 /* Look-Back Mode */
680 #define MCCR0_ECP Fld (2, 24) /* External Clock Prescaler - 1 */
682 (((Div) - 1) << FShft (MCCR0_ECP))
693 #define MCDR2_RW 0x00010000 /* reg. Read/Write (transmit) */
695 #define MCDR2_Wr (MCDR2_RW*1) /* reg. Write */
698 #define MCSR_ATS 0x00000001 /* Audio Transmit FIFO 1/2-full */
700 #define MCSR_ARS 0x00000002 /* Audio Receive FIFO 1/2-full or */
702 #define MCSR_TTS 0x00000004 /* Telecom Transmit FIFO 1/2-full */
704 #define MCSR_TRS 0x00000008 /* Telecom Receive FIFO 1/2-full */
706 #define MCSR_ATU 0x00000010 /* Audio Transmit FIFO Under-run */
707 #define MCSR_ARO 0x00000020 /* Audio Receive FIFO Over-run */
708 #define MCSR_TTU 0x00000040 /* Telecom Transmit FIFO Under-run */
709 #define MCSR_TRO 0x00000080 /* Telecom Receive FIFO Over-run */
718 #define MCSR_CWC 0x00001000 /* CODEC register Write Completed */
737 * Register 0 (read/write).
739 * Register 1 (read/write).
741 * (rev. = 8) and higher of the StrongARM SA-1100.]
743 * Register (read/write).
745 * Register (read/write).
758 #define SSCR0_DSS Fld (4, 0) /* Data Size - 1 Select [3..15] */
760 (((Size) - 1) << FShft (SSCR0_DSS))
770 #define SSCR0_SSE 0x00000080 /* SSP Enable */
771 #define SSCR0_SCR Fld (8, 8) /* Serial Clock Rate divisor/2 - 1 */
775 (((Div) - 2)/2 << FShft (SSCR0_SCR))
779 (((Div) - 1)/2 << FShft (SSCR0_SCR))
783 #define SSCR1_RIE 0x00000001 /* Receive FIFO 1/2-full or more */
784 /* Interrupt Enable */
785 #define SSCR1_TIE 0x00000002 /* Transmit FIFO 1/2-full or less */
786 /* Interrupt Enable */
787 #define SSCR1_LBM 0x00000004 /* Look-Back Mode */
805 #define SSSR_TFS 0x00000010 /* Transmit FIFO 1/2-full or less */
807 #define SSSR_RFS 0x00000020 /* Receive FIFO 1/2-full or more */
809 #define SSSR_ROR 0x00000040 /* Receive FIFO Over-Run */
817 * (read/write).
819 * (read/write).
821 * (read/write).
823 * (read/write).
825 * (read/write).
827 * (read/write).
828 * OWER Operating System (OS) timer Watch-dog Enable Register
829 * (read/write).
830 * OIER Operating System (OS) timer Interrupt Enable Register
831 * (read/write).
840 #define OWER io_p2v(0x90000018) /* OS timer Watch-dog Enable Reg. */
841 #define OIER io_p2v(0x9000001C) /* OS timer Interrupt Enable Reg. */
850 #define OWER_WME 0x00000001 /* Watch-dog Match Enable */
853 #define OIER_E(Nb) /* match interrupt Enable [0..3] */ \
855 #define OIER_E0 OIER_E (0) /* match interrupt Enable 0 */
856 #define OIER_E1 OIER_E (1) /* match interrupt Enable 1 */
857 #define OIER_E2 OIER_E (2) /* match interrupt Enable 2 */
858 #define OIER_E3 OIER_E (3) /* match interrupt Enable 3 */
865 * PMCR Power Manager (PM) Control Register (read/write).
866 * PSSR Power Manager (PM) Sleep Status Register (read/write).
867 * PSPR Power Manager (PM) Scratch-Pad Register (read/write).
868 * PWER Power Manager (PM) Wake-up Enable Register
869 * (read/write).
871 * (read/write).
872 * PPCR Power Manager (PM) Phase-Locked Loop (PLL)
873 * Configuration Register (read/write).
874 * PGSR Power Manager (PM) General-Purpose Input/Output (GPIO)
875 * Sleep state Register (read/write, see GPIO pins).
886 #define PSPR __REG(0x90020008) /* PM Scratch-Pad Reg. */
887 #define PWER __REG(0x9002000C) /* PM Wake-up Enable Reg. */
902 #define PWER_GPIO(Nb) GPIO_GPIO (Nb) /* GPIO [0..27] wake-up enable */
903 #define PWER_GPIO0 PWER_GPIO (0) /* GPIO [0] wake-up enable */
904 #define PWER_GPIO1 PWER_GPIO (1) /* GPIO [1] wake-up enable */
905 #define PWER_GPIO2 PWER_GPIO (2) /* GPIO [2] wake-up enable */
906 #define PWER_GPIO3 PWER_GPIO (3) /* GPIO [3] wake-up enable */
907 #define PWER_GPIO4 PWER_GPIO (4) /* GPIO [4] wake-up enable */
908 #define PWER_GPIO5 PWER_GPIO (5) /* GPIO [5] wake-up enable */
909 #define PWER_GPIO6 PWER_GPIO (6) /* GPIO [6] wake-up enable */
910 #define PWER_GPIO7 PWER_GPIO (7) /* GPIO [7] wake-up enable */
911 #define PWER_GPIO8 PWER_GPIO (8) /* GPIO [8] wake-up enable */
912 #define PWER_GPIO9 PWER_GPIO (9) /* GPIO [9] wake-up enable */
913 #define PWER_GPIO10 PWER_GPIO (10) /* GPIO [10] wake-up enable */
914 #define PWER_GPIO11 PWER_GPIO (11) /* GPIO [11] wake-up enable */
915 #define PWER_GPIO12 PWER_GPIO (12) /* GPIO [12] wake-up enable */
916 #define PWER_GPIO13 PWER_GPIO (13) /* GPIO [13] wake-up enable */
917 #define PWER_GPIO14 PWER_GPIO (14) /* GPIO [14] wake-up enable */
918 #define PWER_GPIO15 PWER_GPIO (15) /* GPIO [15] wake-up enable */
919 #define PWER_GPIO16 PWER_GPIO (16) /* GPIO [16] wake-up enable */
920 #define PWER_GPIO17 PWER_GPIO (17) /* GPIO [17] wake-up enable */
921 #define PWER_GPIO18 PWER_GPIO (18) /* GPIO [18] wake-up enable */
922 #define PWER_GPIO19 PWER_GPIO (19) /* GPIO [19] wake-up enable */
923 #define PWER_GPIO20 PWER_GPIO (20) /* GPIO [20] wake-up enable */
924 #define PWER_GPIO21 PWER_GPIO (21) /* GPIO [21] wake-up enable */
925 #define PWER_GPIO22 PWER_GPIO (22) /* GPIO [22] wake-up enable */
926 #define PWER_GPIO23 PWER_GPIO (23) /* GPIO [23] wake-up enable */
927 #define PWER_GPIO24 PWER_GPIO (24) /* GPIO [24] wake-up enable */
928 #define PWER_GPIO25 PWER_GPIO (25) /* GPIO [25] wake-up enable */
929 #define PWER_GPIO26 PWER_GPIO (26) /* GPIO [26] wake-up enable */
930 #define PWER_GPIO27 PWER_GPIO (27) /* GPIO [27] wake-up enable */
931 #define PWER_RTC 0x80000000 /* RTC alarm wake-up enable */
933 #define PCFR_OPDE 0x00000001 /* Oscillator Power-Down Enable */
943 /* (32.768 kHz) enable On */
1021 * (read/write).
1022 * RCSR Reset Controller (RC) Status Register (read/write).
1032 #define RCSR_WDR 0x00000004 /* Watch-Dog Reset */
1033 #define RCSR_SMR 0x00000008 /* Sleep-Mode Reset */
1040 * TUCR Test Unit Control Register (read/write).
1081 * General-Purpose Input/Output (GPIO) control registers
1084 * GPLR General-Purpose Input/Output (GPIO) Pin Level
1086 * GPDR General-Purpose Input/Output (GPIO) Pin Direction
1087 * Register (read/write).
1088 * GPSR General-Purpose Input/Output (GPIO) Pin output Set
1089 * Register (write).
1090 * GPCR General-Purpose Input/Output (GPIO) Pin output Clear
1091 * Register (write).
1092 * GRER General-Purpose Input/Output (GPIO) Rising-Edge
1093 * detect Register (read/write).
1094 * GFER General-Purpose Input/Output (GPIO) Falling-Edge
1095 * detect Register (read/write).
1096 * GEDR General-Purpose Input/Output (GPIO) Edge Detect
1097 * status Register (read/write).
1098 * GAFR General-Purpose Input/Output (GPIO) Alternate
1099 * Function Register (read/write).
1109 #define GRER __REG(0x90040010) /* GPIO Rising-Edge detect Reg. */
1110 #define GFER __REG(0x90040014) /* GPIO Falling-Edge detect Reg. */
1149 GPIO_GPIO ((Nb) - 6)
1195 * ICMR Interrupt Controller (IC) Mask Register (read/write).
1196 * ICLR Interrupt Controller (IC) Level Register (read/write).
1198 * (read/write).
1200 * (rev. = 8) and higher of the StrongARM SA-1100.]
1206 * StrongARM SA-1100, it is active high (non-inverted) in
1259 #define ICCR_DIM 0x00000001 /* Disable Idle-mode interrupt */
1261 #define ICCR_IdleAllInt (ICCR_DIM*0) /* Idle-mode All Interrupt enable */
1263 #define ICCR_IdleMskInt (ICCR_DIM*1) /* Idle-mode non-Masked Interrupt */
1264 /* enable (ICMR used) */
1272 * Register (read/write).
1274 * (read/write).
1276 * Register (read/write).
1277 * PSDR Peripheral Pin Controller (PPC) Sleep-mode pin
1278 * Direction Register (read/write).
1286 #define PSDR __REG(0x9006000C) /* PPC Sleep-mode pin Direction Reg. */
1347 * Dynamic Random-Access Memory (DRAM) control registers
1350 * MDCNFG Memory system: Dynamic Random-Access Memory (DRAM)
1351 * CoNFiGuration register (read/write).
1352 * MDCAS0 Memory system: Dynamic Random-Access Memory (DRAM)
1354 * (read/write).
1355 * MDCAS1 Memory system: Dynamic Random-Access Memory (DRAM)
1357 * (read/write).
1358 * MDCAS2 Memory system: Dynamic Random-Access Memory (DRAM)
1360 * (read/write).
1374 #define MDCNFG_DE(Nb) /* DRAM Enable bank [0..3] */ \
1376 #define MDCNFG_DE0 MDCNFG_DE (0) /* DRAM Enable bank 0 */
1377 #define MDCNFG_DE1 MDCNFG_DE (1) /* DRAM Enable bank 1 */
1378 #define MDCNFG_DE2 MDCNFG_DE (2) /* DRAM Enable bank 2 */
1379 #define MDCNFG_DE3 MDCNFG_DE (3) /* DRAM Enable bank 3 */
1380 #define MDCNFG_DRAC Fld (2, 4) /* DRAM Row Address Count - 9 */
1382 (((Add) - 9) << FShft (MDCNFG_DRAC))
1385 #define MDCNFG_TRP Fld (4, 7) /* Time RAS Pre-charge - 1 [Tmem] */
1386 #define MDCNFG_PrChrg(Tcpu) /* Pre-Charge time [2..32 Tcpu] */ \
1387 (((Tcpu) - 2)/2 << FShft (MDCNFG_TRP))
1389 (((Tcpu) - 1)/2 << FShft (MDCNFG_TRP))
1390 #define MDCNFG_TRASR Fld (4, 11) /* Time RAS Refresh - 1 [Tmem] */
1392 (((Tcpu) - 2)/2 << FShft (MDCNFG_TRASR))
1394 (((Tcpu) - 1)/2 << FShft (MDCNFG_TRASR))
1405 #define MDCNFG_SA1110_DE0 0x00000001 /* DRAM Enable bank 0 */
1406 #define MDCNFG_SA1110_DE1 0x00000002 /* DRAM Enable bank 1 */
1415 #define MDCNFG_SA1110_TWR0 Fld(2, 14) /* SDRAM write recovery 0/1 */
1416 #define MDCNFG_SA1110_DE2 0x00010000 /* DRAM Enable bank 0 */
1417 #define MDCNFG_SA1110_DE3 0x00020000 /* DRAM Enable bank 1 */
1426 #define MDCNFG_SA1110_TWR2 Fld(2, 30) /* SDRAM write recovery 0/1 */
1434 * (read/write).
1436 * (read/write).
1455 #define MSC_NonBrst /* Non-Burst static memory */ \
1457 #define MSC_SRAM /* 32-bit byte-writable SRAM */ \
1459 #define MSC_Brst4 /* Burst-of-4 static memory */ \
1461 #define MSC_Brst8 /* Burst-of-8 static memory */ \
1464 #define MSC_32BitStMem (MSC_RBW*0) /* 32-Bit Static Memory */
1465 #define MSC_16BitStMem (MSC_RBW*1) /* 16-Bit Static Memory */
1467 /* First access - 1(.5) [Tmem] */
1470 ((((Tcpu) - 3)/2) << FShft (MSC_RDF))
1472 ((((Tcpu) - 2)/2) << FShft (MSC_RDF))
1473 #define MSC_RdAcc(Tcpu) /* Read Access time (non-burst */ \
1475 ((((Tcpu) - 2)/2) << FShft (MSC_RDF))
1477 ((((Tcpu) - 1)/2) << FShft (MSC_RDF))
1479 /* Next access - 1 [Tmem] */
1482 ((((Tcpu) - 2)/2) << FShft (MSC_RDN))
1484 ((((Tcpu) - 1)/2) << FShft (MSC_RDN))
1485 #define MSC_WrAcc(Tcpu) /* Write Access time (non-burst */ \
1487 ((((Tcpu) - 2)/2) << FShft (MSC_RDN))
1489 ((((Tcpu) - 1)/2) << FShft (MSC_RDN))
1504 * Configuration Register (read/write).
1520 #define MECR_BSIO Fld (5, 0) /* BCLK Select I/O - 1 [Tmem] */
1522 ((((Tcpu) - 2)/2) << FShft (MECR_BSIO))
1524 ((((Tcpu) - 1)/2) << FShft (MECR_BSIO))
1525 #define MECR_BSA Fld (5, 5) /* BCLK Select Attribute - 1 */
1528 ((((Tcpu) - 2)/2) << FShft (MECR_BSA))
1530 ((((Tcpu) - 1)/2) << FShft (MECR_BSA))
1531 #define MECR_BSM Fld (5, 10) /* BCLK Select Memory - 1 [Tmem] */
1533 ((((Tcpu) - 2)/2) << FShft (MECR_BSM))
1535 ((((Tcpu) - 1)/2) << FShft (MECR_BSM))
1570 * (read/write).
1573 * SA-1100.]
1575 * (read/write).
1577 * and 1.1 (rev. = 2) of the StrongARM SA-1100, it can be
1581 * (DMA) Base Address Register channel 1 (read/write).
1585 * (DMA) Base Address Register channel 2 (read/write).
1589 * (read/write).
1592 * StrongARM SA-1100, it can be written and read in
1595 * (read/write).
1598 * StrongARM SA-1100, it can be written and read in
1601 * (read/write).
1604 * StrongARM SA-1100, it can be written and read in
1607 * the StrongARM SA-1100.]
1618 #define LCD_4BitPSp /* LCD 4-Bit pixel Palette Space */ \
1621 #define LCD_8BitPSp /* LCD 8-Bit pixel Palette Space */ \
1624 #define LCD_12_16BitPSp /* LCD 12/16-Bit pixel */ \
1625 /* dummy-Palette Space [byte] */ \
1633 #define LCD_4Bit /* LCD 4-Bit pixel mode */ \
1635 #define LCD_8Bit /* LCD 8-Bit pixel mode */ \
1637 #define LCD_12_16Bit /* LCD 12/16-Bit pixel mode */ \
1658 #define LCCR0_LEN 0x00000001 /* LCD ENable */
1681 #define LCCR0_4PixMono (LCCR0_DPD*0) /* 4-Pixel/clock Monochrome */
1683 #define LCCR0_8PixMono (LCCR0_DPD*1) /* 8-Pixel/clock Monochrome */
1695 #define LCSR_IOL 0x00000010 /* Input FIFO Over-run Lower */
1697 #define LCSR_IUL 0x00000020 /* Input FIFO Under-run Lower */
1699 #define LCSR_IOU 0x00000040 /* Input FIFO Over-run Upper */
1701 #define LCSR_IUU 0x00000080 /* Input FIFO Under-run Upper */
1703 #define LCSR_OOL 0x00000100 /* Output FIFO Over-run Lower */
1705 #define LCSR_OUL 0x00000200 /* Output FIFO Under-run Lower */
1707 #define LCSR_OOU 0x00000400 /* Output FIFO Over-run Upper */
1709 #define LCSR_OUU 0x00000800 /* Output FIFO Under-run Upper */
1712 #define LCCR1_PPL Fld (6, 4) /* Pixels Per Line/16 - 1 */
1714 (((Pixel) - 16)/16 << FShft (LCCR1_PPL))
1716 /* pulse Width - 1 [Tpix] (L_LCLK) */
1719 (((Tpix) - 1) << FShft (LCCR1_HSW))
1720 #define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait */
1721 /* count - 1 [Tpix] */
1722 #define LCCR1_EndLnDel(Tpix) /* End-of-Line Delay */ \
1724 (((Tpix) - 1) << FShft (LCCR1_ELW))
1725 #define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */
1726 /* Wait count - 1 [Tpix] */
1727 #define LCCR1_BegLnDel(Tpix) /* Beginning-of-Line Delay */ \
1729 (((Tpix) - 1) << FShft (LCCR1_BLW))
1731 #define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */
1733 (((Line) - 1) << FShft (LCCR2_LPP))
1735 /* Width - 1 [Tln] (L_FCLK) */
1738 (((Tln) - 1) << FShft (LCCR2_VSW))
1739 #define LCCR2_EFW Fld (8, 16) /* End-of-Frame line clock Wait */
1741 #define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \
1744 #define LCCR2_BFW Fld (8, 24) /* Beginning-of-Frame line clock */
1746 #define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \
1750 #define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor/2 - 2 */
1755 (((Div) - 4)/2 << FShft (LCCR3_PCD))
1759 (((Div) - 3)/2 << FShft (LCCR3_PCD))
1762 #define LCCR3_ACB Fld (8, 8) /* AC Bias clock half period - 1 */
1765 (((Div) - 2)/2 << FShft (LCCR3_ACB))
1769 (((Div) - 1)/2 << FShft (LCCR3_ACB))
1793 #define LCCR3_PixRsEdg (LCCR3_PCP*0) /* Pixel clock Rising-Edge */
1794 #define LCCR3_PixFlEdg (LCCR3_PCP*1) /* Pixel clock Falling-Edge */
1795 #define LCCR3_OEP 0x00800000 /* Output Enable Polarity (L_BIAS, */
1797 #define LCCR3_OutEnH (LCCR3_OEP*0) /* Output Enable active High */
1798 #define LCCR3_OutEnL (LCCR3_OEP*1) /* Output Enable active Low */