1*b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 2a09e64fbSRussell King /* 3a09e64fbSRussell King * FILE SA-1100.h 4a09e64fbSRussell King * 5a09e64fbSRussell King * Version 1.2 6a09e64fbSRussell King * Author Copyright (c) Marc A. Viredaz, 1998 7a09e64fbSRussell King * DEC Western Research Laboratory, Palo Alto, CA 8a09e64fbSRussell King * Date January 1998 (April 1997) 9a09e64fbSRussell King * System StrongARM SA-1100 10a09e64fbSRussell King * Language C or ARM Assembly 11a09e64fbSRussell King * Purpose Definition of constants related to the StrongARM 12a09e64fbSRussell King * SA-1100 microprocessor (Advanced RISC Machine (ARM) 13a09e64fbSRussell King * architecture version 4). This file is based on the 14a09e64fbSRussell King * StrongARM SA-1100 data sheet version 2.2. 15a09e64fbSRussell King * 16a09e64fbSRussell King */ 17a09e64fbSRussell King 18a09e64fbSRussell King 19a09e64fbSRussell King /* Be sure that virtual mapping is defined right */ 20a09e64fbSRussell King #ifndef __ASM_ARCH_HARDWARE_H 21a09e64fbSRussell King #error You must include hardware.h not SA-1100.h 22a09e64fbSRussell King #endif 23a09e64fbSRussell King 24a09e64fbSRussell King #include "bitfield.h" 25a09e64fbSRussell King 26a09e64fbSRussell King /* 27a09e64fbSRussell King * SA1100 CS line to physical address 28a09e64fbSRussell King */ 29a09e64fbSRussell King 30a09e64fbSRussell King #define SA1100_CS0_PHYS 0x00000000 31a09e64fbSRussell King #define SA1100_CS1_PHYS 0x08000000 32a09e64fbSRussell King #define SA1100_CS2_PHYS 0x10000000 33a09e64fbSRussell King #define SA1100_CS3_PHYS 0x18000000 34a09e64fbSRussell King #define SA1100_CS4_PHYS 0x40000000 35a09e64fbSRussell King #define SA1100_CS5_PHYS 0x48000000 36a09e64fbSRussell King 37a09e64fbSRussell King /* 38a09e64fbSRussell King * Personal Computer Memory Card International Association (PCMCIA) sockets 39a09e64fbSRussell King */ 40a09e64fbSRussell King 41a09e64fbSRussell King #define PCMCIAPrtSp 0x04000000 /* PCMCIA Partition Space [byte] */ 42a09e64fbSRussell King #define PCMCIASp (4*PCMCIAPrtSp) /* PCMCIA Space [byte] */ 43a09e64fbSRussell King #define PCMCIAIOSp PCMCIAPrtSp /* PCMCIA I/O Space [byte] */ 44a09e64fbSRussell King #define PCMCIAAttrSp PCMCIAPrtSp /* PCMCIA Attribute Space [byte] */ 45a09e64fbSRussell King #define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */ 46a09e64fbSRussell King 47a09e64fbSRussell King #define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */ 48a09e64fbSRussell King #define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */ 49a09e64fbSRussell King #define PCMCIA0AttrSp PCMCIAAttrSp /* PCMCIA 0 Attribute Space [byte] */ 50a09e64fbSRussell King #define PCMCIA0MemSp PCMCIAMemSp /* PCMCIA 0 Memory Space [byte] */ 51a09e64fbSRussell King 52a09e64fbSRussell King #define PCMCIA1Sp PCMCIASp /* PCMCIA 1 Space [byte] */ 53a09e64fbSRussell King #define PCMCIA1IOSp PCMCIAIOSp /* PCMCIA 1 I/O Space [byte] */ 54a09e64fbSRussell King #define PCMCIA1AttrSp PCMCIAAttrSp /* PCMCIA 1 Attribute Space [byte] */ 55a09e64fbSRussell King #define PCMCIA1MemSp PCMCIAMemSp /* PCMCIA 1 Memory Space [byte] */ 56a09e64fbSRussell King 57a09e64fbSRussell King #define _PCMCIA(Nb) /* PCMCIA [0..1] */ \ 58a09e64fbSRussell King (0x20000000 + (Nb)*PCMCIASp) 59a09e64fbSRussell King #define _PCMCIAIO(Nb) _PCMCIA (Nb) /* PCMCIA I/O [0..1] */ 60a09e64fbSRussell King #define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \ 61a09e64fbSRussell King (_PCMCIA (Nb) + 2*PCMCIAPrtSp) 62a09e64fbSRussell King #define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \ 63a09e64fbSRussell King (_PCMCIA (Nb) + 3*PCMCIAPrtSp) 64a09e64fbSRussell King 65a09e64fbSRussell King #define _PCMCIA0 _PCMCIA (0) /* PCMCIA 0 */ 66a09e64fbSRussell King #define _PCMCIA0IO _PCMCIAIO (0) /* PCMCIA 0 I/O */ 67a09e64fbSRussell King #define _PCMCIA0Attr _PCMCIAAttr (0) /* PCMCIA 0 Attribute */ 68a09e64fbSRussell King #define _PCMCIA0Mem _PCMCIAMem (0) /* PCMCIA 0 Memory */ 69a09e64fbSRussell King 70a09e64fbSRussell King #define _PCMCIA1 _PCMCIA (1) /* PCMCIA 1 */ 71a09e64fbSRussell King #define _PCMCIA1IO _PCMCIAIO (1) /* PCMCIA 1 I/O */ 72a09e64fbSRussell King #define _PCMCIA1Attr _PCMCIAAttr (1) /* PCMCIA 1 Attribute */ 73a09e64fbSRussell King #define _PCMCIA1Mem _PCMCIAMem (1) /* PCMCIA 1 Memory */ 74a09e64fbSRussell King 75a09e64fbSRussell King 76a09e64fbSRussell King /* 77a09e64fbSRussell King * Universal Serial Bus (USB) Device Controller (UDC) control registers 78a09e64fbSRussell King * 79a09e64fbSRussell King * Registers 80a09e64fbSRussell King * Ser0UDCCR Serial port 0 Universal Serial Bus (USB) Device 81a09e64fbSRussell King * Controller (UDC) Control Register (read/write). 82a09e64fbSRussell King * Ser0UDCAR Serial port 0 Universal Serial Bus (USB) Device 83a09e64fbSRussell King * Controller (UDC) Address Register (read/write). 84a09e64fbSRussell King * Ser0UDCOMP Serial port 0 Universal Serial Bus (USB) Device 85a09e64fbSRussell King * Controller (UDC) Output Maximum Packet size register 86a09e64fbSRussell King * (read/write). 87a09e64fbSRussell King * Ser0UDCIMP Serial port 0 Universal Serial Bus (USB) Device 88a09e64fbSRussell King * Controller (UDC) Input Maximum Packet size register 89a09e64fbSRussell King * (read/write). 90a09e64fbSRussell King * Ser0UDCCS0 Serial port 0 Universal Serial Bus (USB) Device 91a09e64fbSRussell King * Controller (UDC) Control/Status register end-point 0 92a09e64fbSRussell King * (read/write). 93a09e64fbSRussell King * Ser0UDCCS1 Serial port 0 Universal Serial Bus (USB) Device 94a09e64fbSRussell King * Controller (UDC) Control/Status register end-point 1 95a09e64fbSRussell King * (output, read/write). 96a09e64fbSRussell King * Ser0UDCCS2 Serial port 0 Universal Serial Bus (USB) Device 97a09e64fbSRussell King * Controller (UDC) Control/Status register end-point 2 98a09e64fbSRussell King * (input, read/write). 99a09e64fbSRussell King * Ser0UDCD0 Serial port 0 Universal Serial Bus (USB) Device 100a09e64fbSRussell King * Controller (UDC) Data register end-point 0 101a09e64fbSRussell King * (read/write). 102a09e64fbSRussell King * Ser0UDCWC Serial port 0 Universal Serial Bus (USB) Device 103a09e64fbSRussell King * Controller (UDC) Write Count register end-point 0 104a09e64fbSRussell King * (read). 105a09e64fbSRussell King * Ser0UDCDR Serial port 0 Universal Serial Bus (USB) Device 106a09e64fbSRussell King * Controller (UDC) Data Register (read/write). 107a09e64fbSRussell King * Ser0UDCSR Serial port 0 Universal Serial Bus (USB) Device 108a09e64fbSRussell King * Controller (UDC) Status Register (read/write). 109a09e64fbSRussell King */ 110a09e64fbSRussell King 111a09e64fbSRussell King #define Ser0UDCCR __REG(0x80000000) /* Ser. port 0 UDC Control Reg. */ 112a09e64fbSRussell King #define Ser0UDCAR __REG(0x80000004) /* Ser. port 0 UDC Address Reg. */ 113a09e64fbSRussell King #define Ser0UDCOMP __REG(0x80000008) /* Ser. port 0 UDC Output Maximum Packet size reg. */ 114a09e64fbSRussell King #define Ser0UDCIMP __REG(0x8000000C) /* Ser. port 0 UDC Input Maximum Packet size reg. */ 115a09e64fbSRussell King #define Ser0UDCCS0 __REG(0x80000010) /* Ser. port 0 UDC Control/Status reg. end-point 0 */ 116a09e64fbSRussell King #define Ser0UDCCS1 __REG(0x80000014) /* Ser. port 0 UDC Control/Status reg. end-point 1 (output) */ 117a09e64fbSRussell King #define Ser0UDCCS2 __REG(0x80000018) /* Ser. port 0 UDC Control/Status reg. end-point 2 (input) */ 118a09e64fbSRussell King #define Ser0UDCD0 __REG(0x8000001C) /* Ser. port 0 UDC Data reg. end-point 0 */ 119a09e64fbSRussell King #define Ser0UDCWC __REG(0x80000020) /* Ser. port 0 UDC Write Count reg. end-point 0 */ 120a09e64fbSRussell King #define Ser0UDCDR __REG(0x80000028) /* Ser. port 0 UDC Data Reg. */ 121a09e64fbSRussell King #define Ser0UDCSR __REG(0x80000030) /* Ser. port 0 UDC Status Reg. */ 122a09e64fbSRussell King 123a09e64fbSRussell King #define UDCCR_UDD 0x00000001 /* UDC Disable */ 124a09e64fbSRussell King #define UDCCR_UDA 0x00000002 /* UDC Active (read) */ 125a09e64fbSRussell King #define UDCCR_RESIM 0x00000004 /* Resume Interrupt Mask, per errata */ 126a09e64fbSRussell King #define UDCCR_EIM 0x00000008 /* End-point 0 Interrupt Mask */ 127a09e64fbSRussell King /* (disable) */ 128a09e64fbSRussell King #define UDCCR_RIM 0x00000010 /* Receive Interrupt Mask */ 129a09e64fbSRussell King /* (disable) */ 130a09e64fbSRussell King #define UDCCR_TIM 0x00000020 /* Transmit Interrupt Mask */ 131a09e64fbSRussell King /* (disable) */ 132a09e64fbSRussell King #define UDCCR_SRM 0x00000040 /* Suspend/Resume interrupt Mask */ 133a09e64fbSRussell King /* (disable) */ 134a09e64fbSRussell King #define UDCCR_SUSIM UDCCR_SRM /* Per errata, SRM just masks suspend */ 135a09e64fbSRussell King #define UDCCR_REM 0x00000080 /* REset interrupt Mask (disable) */ 136a09e64fbSRussell King 137a09e64fbSRussell King #define UDCAR_ADD Fld (7, 0) /* function ADDress */ 138a09e64fbSRussell King 139a09e64fbSRussell King #define UDCOMP_OUTMAXP Fld (8, 0) /* OUTput MAXimum Packet size - 1 */ 140a09e64fbSRussell King /* [byte] */ 141a09e64fbSRussell King #define UDCOMP_OutMaxPkt(Size) /* Output Maximum Packet size */ \ 142a09e64fbSRussell King /* [1..256 byte] */ \ 143a09e64fbSRussell King (((Size) - 1) << FShft (UDCOMP_OUTMAXP)) 144a09e64fbSRussell King 145a09e64fbSRussell King #define UDCIMP_INMAXP Fld (8, 0) /* INput MAXimum Packet size - 1 */ 146a09e64fbSRussell King /* [byte] */ 147a09e64fbSRussell King #define UDCIMP_InMaxPkt(Size) /* Input Maximum Packet size */ \ 148a09e64fbSRussell King /* [1..256 byte] */ \ 149a09e64fbSRussell King (((Size) - 1) << FShft (UDCIMP_INMAXP)) 150a09e64fbSRussell King 151a09e64fbSRussell King #define UDCCS0_OPR 0x00000001 /* Output Packet Ready (read) */ 152a09e64fbSRussell King #define UDCCS0_IPR 0x00000002 /* Input Packet Ready */ 153a09e64fbSRussell King #define UDCCS0_SST 0x00000004 /* Sent STall */ 154a09e64fbSRussell King #define UDCCS0_FST 0x00000008 /* Force STall */ 155a09e64fbSRussell King #define UDCCS0_DE 0x00000010 /* Data End */ 156a09e64fbSRussell King #define UDCCS0_SE 0x00000020 /* Setup End (read) */ 157a09e64fbSRussell King #define UDCCS0_SO 0x00000040 /* Serviced Output packet ready */ 158a09e64fbSRussell King /* (write) */ 159a09e64fbSRussell King #define UDCCS0_SSE 0x00000080 /* Serviced Setup End (write) */ 160a09e64fbSRussell King 161a09e64fbSRussell King #define UDCCS1_RFS 0x00000001 /* Receive FIFO 12-bytes or more */ 162a09e64fbSRussell King /* Service request (read) */ 163a09e64fbSRussell King #define UDCCS1_RPC 0x00000002 /* Receive Packet Complete */ 164a09e64fbSRussell King #define UDCCS1_RPE 0x00000004 /* Receive Packet Error (read) */ 165a09e64fbSRussell King #define UDCCS1_SST 0x00000008 /* Sent STall */ 166a09e64fbSRussell King #define UDCCS1_FST 0x00000010 /* Force STall */ 167a09e64fbSRussell King #define UDCCS1_RNE 0x00000020 /* Receive FIFO Not Empty (read) */ 168a09e64fbSRussell King 169a09e64fbSRussell King #define UDCCS2_TFS 0x00000001 /* Transmit FIFO 8-bytes or less */ 170a09e64fbSRussell King /* Service request (read) */ 171a09e64fbSRussell King #define UDCCS2_TPC 0x00000002 /* Transmit Packet Complete */ 172a09e64fbSRussell King #define UDCCS2_TPE 0x00000004 /* Transmit Packet Error (read) */ 173a09e64fbSRussell King #define UDCCS2_TUR 0x00000008 /* Transmit FIFO Under-Run */ 174a09e64fbSRussell King #define UDCCS2_SST 0x00000010 /* Sent STall */ 175a09e64fbSRussell King #define UDCCS2_FST 0x00000020 /* Force STall */ 176a09e64fbSRussell King 177a09e64fbSRussell King #define UDCD0_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ 178a09e64fbSRussell King 179a09e64fbSRussell King #define UDCWC_WC Fld (4, 0) /* Write Count */ 180a09e64fbSRussell King 181a09e64fbSRussell King #define UDCDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ 182a09e64fbSRussell King 183a09e64fbSRussell King #define UDCSR_EIR 0x00000001 /* End-point 0 Interrupt Request */ 184a09e64fbSRussell King #define UDCSR_RIR 0x00000002 /* Receive Interrupt Request */ 185a09e64fbSRussell King #define UDCSR_TIR 0x00000004 /* Transmit Interrupt Request */ 186a09e64fbSRussell King #define UDCSR_SUSIR 0x00000008 /* SUSpend Interrupt Request */ 187a09e64fbSRussell King #define UDCSR_RESIR 0x00000010 /* RESume Interrupt Request */ 188a09e64fbSRussell King #define UDCSR_RSTIR 0x00000020 /* ReSeT Interrupt Request */ 189a09e64fbSRussell King 190a09e64fbSRussell King 191a09e64fbSRussell King /* 192a09e64fbSRussell King * Universal Asynchronous Receiver/Transmitter (UART) control registers 193a09e64fbSRussell King * 194a09e64fbSRussell King * Registers 195a09e64fbSRussell King * Ser1UTCR0 Serial port 1 Universal Asynchronous 196a09e64fbSRussell King * Receiver/Transmitter (UART) Control Register 0 197a09e64fbSRussell King * (read/write). 198a09e64fbSRussell King * Ser1UTCR1 Serial port 1 Universal Asynchronous 199a09e64fbSRussell King * Receiver/Transmitter (UART) Control Register 1 200a09e64fbSRussell King * (read/write). 201a09e64fbSRussell King * Ser1UTCR2 Serial port 1 Universal Asynchronous 202a09e64fbSRussell King * Receiver/Transmitter (UART) Control Register 2 203a09e64fbSRussell King * (read/write). 204a09e64fbSRussell King * Ser1UTCR3 Serial port 1 Universal Asynchronous 205a09e64fbSRussell King * Receiver/Transmitter (UART) Control Register 3 206a09e64fbSRussell King * (read/write). 207a09e64fbSRussell King * Ser1UTDR Serial port 1 Universal Asynchronous 208a09e64fbSRussell King * Receiver/Transmitter (UART) Data Register 209a09e64fbSRussell King * (read/write). 210a09e64fbSRussell King * Ser1UTSR0 Serial port 1 Universal Asynchronous 211a09e64fbSRussell King * Receiver/Transmitter (UART) Status Register 0 212a09e64fbSRussell King * (read/write). 213a09e64fbSRussell King * Ser1UTSR1 Serial port 1 Universal Asynchronous 214a09e64fbSRussell King * Receiver/Transmitter (UART) Status Register 1 (read). 215a09e64fbSRussell King * 216a09e64fbSRussell King * Ser2UTCR0 Serial port 2 Universal Asynchronous 217a09e64fbSRussell King * Receiver/Transmitter (UART) Control Register 0 218a09e64fbSRussell King * (read/write). 219a09e64fbSRussell King * Ser2UTCR1 Serial port 2 Universal Asynchronous 220a09e64fbSRussell King * Receiver/Transmitter (UART) Control Register 1 221a09e64fbSRussell King * (read/write). 222a09e64fbSRussell King * Ser2UTCR2 Serial port 2 Universal Asynchronous 223a09e64fbSRussell King * Receiver/Transmitter (UART) Control Register 2 224a09e64fbSRussell King * (read/write). 225a09e64fbSRussell King * Ser2UTCR3 Serial port 2 Universal Asynchronous 226a09e64fbSRussell King * Receiver/Transmitter (UART) Control Register 3 227a09e64fbSRussell King * (read/write). 228a09e64fbSRussell King * Ser2UTCR4 Serial port 2 Universal Asynchronous 229a09e64fbSRussell King * Receiver/Transmitter (UART) Control Register 4 230a09e64fbSRussell King * (read/write). 231a09e64fbSRussell King * Ser2UTDR Serial port 2 Universal Asynchronous 232a09e64fbSRussell King * Receiver/Transmitter (UART) Data Register 233a09e64fbSRussell King * (read/write). 234a09e64fbSRussell King * Ser2UTSR0 Serial port 2 Universal Asynchronous 235a09e64fbSRussell King * Receiver/Transmitter (UART) Status Register 0 236a09e64fbSRussell King * (read/write). 237a09e64fbSRussell King * Ser2UTSR1 Serial port 2 Universal Asynchronous 238a09e64fbSRussell King * Receiver/Transmitter (UART) Status Register 1 (read). 239a09e64fbSRussell King * 240a09e64fbSRussell King * Ser3UTCR0 Serial port 3 Universal Asynchronous 241a09e64fbSRussell King * Receiver/Transmitter (UART) Control Register 0 242a09e64fbSRussell King * (read/write). 243a09e64fbSRussell King * Ser3UTCR1 Serial port 3 Universal Asynchronous 244a09e64fbSRussell King * Receiver/Transmitter (UART) Control Register 1 245a09e64fbSRussell King * (read/write). 246a09e64fbSRussell King * Ser3UTCR2 Serial port 3 Universal Asynchronous 247a09e64fbSRussell King * Receiver/Transmitter (UART) Control Register 2 248a09e64fbSRussell King * (read/write). 249a09e64fbSRussell King * Ser3UTCR3 Serial port 3 Universal Asynchronous 250a09e64fbSRussell King * Receiver/Transmitter (UART) Control Register 3 251a09e64fbSRussell King * (read/write). 252a09e64fbSRussell King * Ser3UTDR Serial port 3 Universal Asynchronous 253a09e64fbSRussell King * Receiver/Transmitter (UART) Data Register 254a09e64fbSRussell King * (read/write). 255a09e64fbSRussell King * Ser3UTSR0 Serial port 3 Universal Asynchronous 256a09e64fbSRussell King * Receiver/Transmitter (UART) Status Register 0 257a09e64fbSRussell King * (read/write). 258a09e64fbSRussell King * Ser3UTSR1 Serial port 3 Universal Asynchronous 259a09e64fbSRussell King * Receiver/Transmitter (UART) Status Register 1 (read). 260a09e64fbSRussell King * 261a09e64fbSRussell King * Clocks 262a09e64fbSRussell King * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz 263a09e64fbSRussell King * or 3.5795 MHz). 264a09e64fbSRussell King * fua, Tua Frequency, period of the UART communication. 265a09e64fbSRussell King */ 266a09e64fbSRussell King 267a09e64fbSRussell King #define _UTCR0(Nb) __REG(0x80010000 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 0 [1..3] */ 268a09e64fbSRussell King #define _UTCR1(Nb) __REG(0x80010004 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 1 [1..3] */ 269a09e64fbSRussell King #define _UTCR2(Nb) __REG(0x80010008 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 2 [1..3] */ 270a09e64fbSRussell King #define _UTCR3(Nb) __REG(0x8001000C + ((Nb) - 1)*0x00020000) /* UART Control Reg. 3 [1..3] */ 271a09e64fbSRussell King #define _UTCR4(Nb) __REG(0x80010010 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 4 [2] */ 272a09e64fbSRussell King #define _UTDR(Nb) __REG(0x80010014 + ((Nb) - 1)*0x00020000) /* UART Data Reg. [1..3] */ 273a09e64fbSRussell King #define _UTSR0(Nb) __REG(0x8001001C + ((Nb) - 1)*0x00020000) /* UART Status Reg. 0 [1..3] */ 274a09e64fbSRussell King #define _UTSR1(Nb) __REG(0x80010020 + ((Nb) - 1)*0x00020000) /* UART Status Reg. 1 [1..3] */ 275a09e64fbSRussell King 276a09e64fbSRussell King #define Ser1UTCR0 _UTCR0 (1) /* Ser. port 1 UART Control Reg. 0 */ 277a09e64fbSRussell King #define Ser1UTCR1 _UTCR1 (1) /* Ser. port 1 UART Control Reg. 1 */ 278a09e64fbSRussell King #define Ser1UTCR2 _UTCR2 (1) /* Ser. port 1 UART Control Reg. 2 */ 279a09e64fbSRussell King #define Ser1UTCR3 _UTCR3 (1) /* Ser. port 1 UART Control Reg. 3 */ 280a09e64fbSRussell King #define Ser1UTDR _UTDR (1) /* Ser. port 1 UART Data Reg. */ 281a09e64fbSRussell King #define Ser1UTSR0 _UTSR0 (1) /* Ser. port 1 UART Status Reg. 0 */ 282a09e64fbSRussell King #define Ser1UTSR1 _UTSR1 (1) /* Ser. port 1 UART Status Reg. 1 */ 283a09e64fbSRussell King 284a09e64fbSRussell King #define Ser2UTCR0 _UTCR0 (2) /* Ser. port 2 UART Control Reg. 0 */ 285a09e64fbSRussell King #define Ser2UTCR1 _UTCR1 (2) /* Ser. port 2 UART Control Reg. 1 */ 286a09e64fbSRussell King #define Ser2UTCR2 _UTCR2 (2) /* Ser. port 2 UART Control Reg. 2 */ 287a09e64fbSRussell King #define Ser2UTCR3 _UTCR3 (2) /* Ser. port 2 UART Control Reg. 3 */ 288a09e64fbSRussell King #define Ser2UTCR4 _UTCR4 (2) /* Ser. port 2 UART Control Reg. 4 */ 289a09e64fbSRussell King #define Ser2UTDR _UTDR (2) /* Ser. port 2 UART Data Reg. */ 290a09e64fbSRussell King #define Ser2UTSR0 _UTSR0 (2) /* Ser. port 2 UART Status Reg. 0 */ 291a09e64fbSRussell King #define Ser2UTSR1 _UTSR1 (2) /* Ser. port 2 UART Status Reg. 1 */ 292a09e64fbSRussell King 293a09e64fbSRussell King #define Ser3UTCR0 _UTCR0 (3) /* Ser. port 3 UART Control Reg. 0 */ 294a09e64fbSRussell King #define Ser3UTCR1 _UTCR1 (3) /* Ser. port 3 UART Control Reg. 1 */ 295a09e64fbSRussell King #define Ser3UTCR2 _UTCR2 (3) /* Ser. port 3 UART Control Reg. 2 */ 296a09e64fbSRussell King #define Ser3UTCR3 _UTCR3 (3) /* Ser. port 3 UART Control Reg. 3 */ 297a09e64fbSRussell King #define Ser3UTDR _UTDR (3) /* Ser. port 3 UART Data Reg. */ 298a09e64fbSRussell King #define Ser3UTSR0 _UTSR0 (3) /* Ser. port 3 UART Status Reg. 0 */ 299a09e64fbSRussell King #define Ser3UTSR1 _UTSR1 (3) /* Ser. port 3 UART Status Reg. 1 */ 300a09e64fbSRussell King 301a09e64fbSRussell King /* Those are still used in some places */ 302a09e64fbSRussell King #define _Ser1UTCR0 __PREG(Ser1UTCR0) 303a09e64fbSRussell King #define _Ser2UTCR0 __PREG(Ser2UTCR0) 304a09e64fbSRussell King #define _Ser3UTCR0 __PREG(Ser3UTCR0) 305a09e64fbSRussell King 306a09e64fbSRussell King /* Register offsets */ 307a09e64fbSRussell King #define UTCR0 0x00 308a09e64fbSRussell King #define UTCR1 0x04 309a09e64fbSRussell King #define UTCR2 0x08 310a09e64fbSRussell King #define UTCR3 0x0c 311a09e64fbSRussell King #define UTDR 0x14 312a09e64fbSRussell King #define UTSR0 0x1c 313a09e64fbSRussell King #define UTSR1 0x20 314a09e64fbSRussell King 315a09e64fbSRussell King #define UTCR0_PE 0x00000001 /* Parity Enable */ 316a09e64fbSRussell King #define UTCR0_OES 0x00000002 /* Odd/Even parity Select */ 317a09e64fbSRussell King #define UTCR0_OddPar (UTCR0_OES*0) /* Odd Parity */ 318a09e64fbSRussell King #define UTCR0_EvenPar (UTCR0_OES*1) /* Even Parity */ 319a09e64fbSRussell King #define UTCR0_SBS 0x00000004 /* Stop Bit Select */ 320a09e64fbSRussell King #define UTCR0_1StpBit (UTCR0_SBS*0) /* 1 Stop Bit per frame */ 321a09e64fbSRussell King #define UTCR0_2StpBit (UTCR0_SBS*1) /* 2 Stop Bits per frame */ 322a09e64fbSRussell King #define UTCR0_DSS 0x00000008 /* Data Size Select */ 323a09e64fbSRussell King #define UTCR0_7BitData (UTCR0_DSS*0) /* 7-Bit Data */ 324a09e64fbSRussell King #define UTCR0_8BitData (UTCR0_DSS*1) /* 8-Bit Data */ 325a09e64fbSRussell King #define UTCR0_SCE 0x00000010 /* Sample Clock Enable */ 326a09e64fbSRussell King /* (ser. port 1: GPIO [18], */ 327a09e64fbSRussell King /* ser. port 3: GPIO [20]) */ 328a09e64fbSRussell King #define UTCR0_RCE 0x00000020 /* Receive Clock Edge select */ 329a09e64fbSRussell King #define UTCR0_RcRsEdg (UTCR0_RCE*0) /* Receive clock Rising-Edge */ 330a09e64fbSRussell King #define UTCR0_RcFlEdg (UTCR0_RCE*1) /* Receive clock Falling-Edge */ 331a09e64fbSRussell King #define UTCR0_TCE 0x00000040 /* Transmit Clock Edge select */ 332a09e64fbSRussell King #define UTCR0_TrRsEdg (UTCR0_TCE*0) /* Transmit clock Rising-Edge */ 333a09e64fbSRussell King #define UTCR0_TrFlEdg (UTCR0_TCE*1) /* Transmit clock Falling-Edge */ 334a09e64fbSRussell King #define UTCR0_Ser2IrDA /* Ser. port 2 IrDA settings */ \ 335a09e64fbSRussell King (UTCR0_1StpBit + UTCR0_8BitData) 336a09e64fbSRussell King 337a09e64fbSRussell King #define UTCR1_BRD Fld (4, 0) /* Baud Rate Divisor/16 - 1 [11:8] */ 338a09e64fbSRussell King #define UTCR2_BRD Fld (8, 0) /* Baud Rate Divisor/16 - 1 [7:0] */ 339a09e64fbSRussell King /* fua = fxtl/(16*(BRD[11:0] + 1)) */ 340a09e64fbSRussell King /* Tua = 16*(BRD [11:0] + 1)*Txtl */ 341a09e64fbSRussell King #define UTCR1_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \ 342a09e64fbSRussell King (((Div) - 16)/16 >> FSize (UTCR2_BRD) << \ 343a09e64fbSRussell King FShft (UTCR1_BRD)) 344a09e64fbSRussell King #define UTCR2_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \ 345a09e64fbSRussell King (((Div) - 16)/16 & FAlnMsk (UTCR2_BRD) << \ 346a09e64fbSRussell King FShft (UTCR2_BRD)) 347a09e64fbSRussell King /* fua = fxtl/(16*Floor (Div/16)) */ 348a09e64fbSRussell King /* Tua = 16*Floor (Div/16)*Txtl */ 349a09e64fbSRussell King #define UTCR1_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \ 350a09e64fbSRussell King (((Div) - 1)/16 >> FSize (UTCR2_BRD) << \ 351a09e64fbSRussell King FShft (UTCR1_BRD)) 352a09e64fbSRussell King #define UTCR2_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \ 353a09e64fbSRussell King (((Div) - 1)/16 & FAlnMsk (UTCR2_BRD) << \ 354a09e64fbSRussell King FShft (UTCR2_BRD)) 355a09e64fbSRussell King /* fua = fxtl/(16*Ceil (Div/16)) */ 356a09e64fbSRussell King /* Tua = 16*Ceil (Div/16)*Txtl */ 357a09e64fbSRussell King 358a09e64fbSRussell King #define UTCR3_RXE 0x00000001 /* Receive Enable */ 359a09e64fbSRussell King #define UTCR3_TXE 0x00000002 /* Transmit Enable */ 360a09e64fbSRussell King #define UTCR3_BRK 0x00000004 /* BReaK mode */ 361a09e64fbSRussell King #define UTCR3_RIE 0x00000008 /* Receive FIFO 1/3-to-2/3-full or */ 362a09e64fbSRussell King /* more Interrupt Enable */ 363a09e64fbSRussell King #define UTCR3_TIE 0x00000010 /* Transmit FIFO 1/2-full or less */ 364a09e64fbSRussell King /* Interrupt Enable */ 365a09e64fbSRussell King #define UTCR3_LBM 0x00000020 /* Look-Back Mode */ 366a09e64fbSRussell King #define UTCR3_Ser2IrDA /* Ser. port 2 IrDA settings (RIE, */ \ 367a09e64fbSRussell King /* TIE, LBM can be set or cleared) */ \ 368a09e64fbSRussell King (UTCR3_RXE + UTCR3_TXE) 369a09e64fbSRussell King 370a09e64fbSRussell King #define UTCR4_HSE 0x00000001 /* Hewlett-Packard Serial InfraRed */ 371a09e64fbSRussell King /* (HP-SIR) modulation Enable */ 372a09e64fbSRussell King #define UTCR4_NRZ (UTCR4_HSE*0) /* Non-Return to Zero modulation */ 373a09e64fbSRussell King #define UTCR4_HPSIR (UTCR4_HSE*1) /* HP-SIR modulation */ 374a09e64fbSRussell King #define UTCR4_LPM 0x00000002 /* Low-Power Mode */ 375a09e64fbSRussell King #define UTCR4_Z3_16Bit (UTCR4_LPM*0) /* Zero pulse = 3/16 Bit time */ 376a09e64fbSRussell King #define UTCR4_Z1_6us (UTCR4_LPM*1) /* Zero pulse = 1.6 us */ 377a09e64fbSRussell King 378a09e64fbSRussell King #define UTDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ 379a09e64fbSRussell King #if 0 /* Hidden receive FIFO bits */ 380a09e64fbSRussell King #define UTDR_PRE 0x00000100 /* receive PaRity Error (read) */ 381a09e64fbSRussell King #define UTDR_FRE 0x00000200 /* receive FRaming Error (read) */ 382a09e64fbSRussell King #define UTDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */ 383a09e64fbSRussell King #endif /* 0 */ 384a09e64fbSRussell King 385a09e64fbSRussell King #define UTSR0_TFS 0x00000001 /* Transmit FIFO 1/2-full or less */ 386a09e64fbSRussell King /* Service request (read) */ 387a09e64fbSRussell King #define UTSR0_RFS 0x00000002 /* Receive FIFO 1/3-to-2/3-full or */ 388a09e64fbSRussell King /* more Service request (read) */ 389a09e64fbSRussell King #define UTSR0_RID 0x00000004 /* Receiver IDle */ 390a09e64fbSRussell King #define UTSR0_RBB 0x00000008 /* Receive Beginning of Break */ 391a09e64fbSRussell King #define UTSR0_REB 0x00000010 /* Receive End of Break */ 392a09e64fbSRussell King #define UTSR0_EIF 0x00000020 /* Error In FIFO (read) */ 393a09e64fbSRussell King 394a09e64fbSRussell King #define UTSR1_TBY 0x00000001 /* Transmitter BusY (read) */ 395a09e64fbSRussell King #define UTSR1_RNE 0x00000002 /* Receive FIFO Not Empty (read) */ 396a09e64fbSRussell King #define UTSR1_TNF 0x00000004 /* Transmit FIFO Not Full (read) */ 397a09e64fbSRussell King #define UTSR1_PRE 0x00000008 /* receive PaRity Error (read) */ 398a09e64fbSRussell King #define UTSR1_FRE 0x00000010 /* receive FRaming Error (read) */ 399a09e64fbSRussell King #define UTSR1_ROR 0x00000020 /* Receive FIFO Over-Run (read) */ 400a09e64fbSRussell King 401a09e64fbSRussell King 402a09e64fbSRussell King /* 403a09e64fbSRussell King * Synchronous Data Link Controller (SDLC) control registers 404a09e64fbSRussell King * 405a09e64fbSRussell King * Registers 406a09e64fbSRussell King * Ser1SDCR0 Serial port 1 Synchronous Data Link Controller (SDLC) 407a09e64fbSRussell King * Control Register 0 (read/write). 408a09e64fbSRussell King * Ser1SDCR1 Serial port 1 Synchronous Data Link Controller (SDLC) 409a09e64fbSRussell King * Control Register 1 (read/write). 410a09e64fbSRussell King * Ser1SDCR2 Serial port 1 Synchronous Data Link Controller (SDLC) 411a09e64fbSRussell King * Control Register 2 (read/write). 412a09e64fbSRussell King * Ser1SDCR3 Serial port 1 Synchronous Data Link Controller (SDLC) 413a09e64fbSRussell King * Control Register 3 (read/write). 414a09e64fbSRussell King * Ser1SDCR4 Serial port 1 Synchronous Data Link Controller (SDLC) 415a09e64fbSRussell King * Control Register 4 (read/write). 416a09e64fbSRussell King * Ser1SDDR Serial port 1 Synchronous Data Link Controller (SDLC) 417a09e64fbSRussell King * Data Register (read/write). 418a09e64fbSRussell King * Ser1SDSR0 Serial port 1 Synchronous Data Link Controller (SDLC) 419a09e64fbSRussell King * Status Register 0 (read/write). 420a09e64fbSRussell King * Ser1SDSR1 Serial port 1 Synchronous Data Link Controller (SDLC) 421a09e64fbSRussell King * Status Register 1 (read/write). 422a09e64fbSRussell King * 423a09e64fbSRussell King * Clocks 424a09e64fbSRussell King * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz 425a09e64fbSRussell King * or 3.5795 MHz). 426a09e64fbSRussell King * fsd, Tsd Frequency, period of the SDLC communication. 427a09e64fbSRussell King */ 428a09e64fbSRussell King 429a09e64fbSRussell King #define Ser1SDCR0 __REG(0x80020060) /* Ser. port 1 SDLC Control Reg. 0 */ 430a09e64fbSRussell King #define Ser1SDCR1 __REG(0x80020064) /* Ser. port 1 SDLC Control Reg. 1 */ 431a09e64fbSRussell King #define Ser1SDCR2 __REG(0x80020068) /* Ser. port 1 SDLC Control Reg. 2 */ 432a09e64fbSRussell King #define Ser1SDCR3 __REG(0x8002006C) /* Ser. port 1 SDLC Control Reg. 3 */ 433a09e64fbSRussell King #define Ser1SDCR4 __REG(0x80020070) /* Ser. port 1 SDLC Control Reg. 4 */ 434a09e64fbSRussell King #define Ser1SDDR __REG(0x80020078) /* Ser. port 1 SDLC Data Reg. */ 435a09e64fbSRussell King #define Ser1SDSR0 __REG(0x80020080) /* Ser. port 1 SDLC Status Reg. 0 */ 436a09e64fbSRussell King #define Ser1SDSR1 __REG(0x80020084) /* Ser. port 1 SDLC Status Reg. 1 */ 437a09e64fbSRussell King 438a09e64fbSRussell King #define SDCR0_SUS 0x00000001 /* SDLC/UART Select */ 439a09e64fbSRussell King #define SDCR0_SDLC (SDCR0_SUS*0) /* SDLC mode (TXD1 & RXD1) */ 440a09e64fbSRussell King #define SDCR0_UART (SDCR0_SUS*1) /* UART mode (TXD1 & RXD1) */ 441a09e64fbSRussell King #define SDCR0_SDF 0x00000002 /* Single/Double start Flag select */ 442a09e64fbSRussell King #define SDCR0_SglFlg (SDCR0_SDF*0) /* Single start Flag */ 443a09e64fbSRussell King #define SDCR0_DblFlg (SDCR0_SDF*1) /* Double start Flag */ 444a09e64fbSRussell King #define SDCR0_LBM 0x00000004 /* Look-Back Mode */ 445a09e64fbSRussell King #define SDCR0_BMS 0x00000008 /* Bit Modulation Select */ 446a09e64fbSRussell King #define SDCR0_FM0 (SDCR0_BMS*0) /* Freq. Modulation zero (0) */ 447a09e64fbSRussell King #define SDCR0_NRZ (SDCR0_BMS*1) /* Non-Return to Zero modulation */ 448a09e64fbSRussell King #define SDCR0_SCE 0x00000010 /* Sample Clock Enable (GPIO [16]) */ 449a09e64fbSRussell King #define SDCR0_SCD 0x00000020 /* Sample Clock Direction select */ 450a09e64fbSRussell King /* (GPIO [16]) */ 451a09e64fbSRussell King #define SDCR0_SClkIn (SDCR0_SCD*0) /* Sample Clock Input */ 452a09e64fbSRussell King #define SDCR0_SClkOut (SDCR0_SCD*1) /* Sample Clock Output */ 453a09e64fbSRussell King #define SDCR0_RCE 0x00000040 /* Receive Clock Edge select */ 454a09e64fbSRussell King #define SDCR0_RcRsEdg (SDCR0_RCE*0) /* Receive clock Rising-Edge */ 455a09e64fbSRussell King #define SDCR0_RcFlEdg (SDCR0_RCE*1) /* Receive clock Falling-Edge */ 456a09e64fbSRussell King #define SDCR0_TCE 0x00000080 /* Transmit Clock Edge select */ 457a09e64fbSRussell King #define SDCR0_TrRsEdg (SDCR0_TCE*0) /* Transmit clock Rising-Edge */ 458a09e64fbSRussell King #define SDCR0_TrFlEdg (SDCR0_TCE*1) /* Transmit clock Falling-Edge */ 459a09e64fbSRussell King 460a09e64fbSRussell King #define SDCR1_AAF 0x00000001 /* Abort After Frame enable */ 461a09e64fbSRussell King /* (GPIO [17]) */ 462a09e64fbSRussell King #define SDCR1_TXE 0x00000002 /* Transmit Enable */ 463a09e64fbSRussell King #define SDCR1_RXE 0x00000004 /* Receive Enable */ 464a09e64fbSRussell King #define SDCR1_RIE 0x00000008 /* Receive FIFO 1/3-to-2/3-full or */ 465a09e64fbSRussell King /* more Interrupt Enable */ 466a09e64fbSRussell King #define SDCR1_TIE 0x00000010 /* Transmit FIFO 1/2-full or less */ 467a09e64fbSRussell King /* Interrupt Enable */ 468a09e64fbSRussell King #define SDCR1_AME 0x00000020 /* Address Match Enable */ 469a09e64fbSRussell King #define SDCR1_TUS 0x00000040 /* Transmit FIFO Under-run Select */ 470a09e64fbSRussell King #define SDCR1_EFrmURn (SDCR1_TUS*0) /* End Frame on Under-Run */ 471a09e64fbSRussell King #define SDCR1_AbortURn (SDCR1_TUS*1) /* Abort on Under-Run */ 472a09e64fbSRussell King #define SDCR1_RAE 0x00000080 /* Receive Abort interrupt Enable */ 473a09e64fbSRussell King 474a09e64fbSRussell King #define SDCR2_AMV Fld (8, 0) /* Address Match Value */ 475a09e64fbSRussell King 476a09e64fbSRussell King #define SDCR3_BRD Fld (4, 0) /* Baud Rate Divisor/16 - 1 [11:8] */ 477a09e64fbSRussell King #define SDCR4_BRD Fld (8, 0) /* Baud Rate Divisor/16 - 1 [7:0] */ 478a09e64fbSRussell King /* fsd = fxtl/(16*(BRD[11:0] + 1)) */ 479a09e64fbSRussell King /* Tsd = 16*(BRD[11:0] + 1)*Txtl */ 480a09e64fbSRussell King #define SDCR3_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \ 481a09e64fbSRussell King (((Div) - 16)/16 >> FSize (SDCR4_BRD) << \ 482a09e64fbSRussell King FShft (SDCR3_BRD)) 483a09e64fbSRussell King #define SDCR4_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \ 484a09e64fbSRussell King (((Div) - 16)/16 & FAlnMsk (SDCR4_BRD) << \ 485a09e64fbSRussell King FShft (SDCR4_BRD)) 486a09e64fbSRussell King /* fsd = fxtl/(16*Floor (Div/16)) */ 487a09e64fbSRussell King /* Tsd = 16*Floor (Div/16)*Txtl */ 488a09e64fbSRussell King #define SDCR3_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \ 489a09e64fbSRussell King (((Div) - 1)/16 >> FSize (SDCR4_BRD) << \ 490a09e64fbSRussell King FShft (SDCR3_BRD)) 491a09e64fbSRussell King #define SDCR4_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \ 492a09e64fbSRussell King (((Div) - 1)/16 & FAlnMsk (SDCR4_BRD) << \ 493a09e64fbSRussell King FShft (SDCR4_BRD)) 494a09e64fbSRussell King /* fsd = fxtl/(16*Ceil (Div/16)) */ 495a09e64fbSRussell King /* Tsd = 16*Ceil (Div/16)*Txtl */ 496a09e64fbSRussell King 497a09e64fbSRussell King #define SDDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ 498a09e64fbSRussell King #if 0 /* Hidden receive FIFO bits */ 499a09e64fbSRussell King #define SDDR_EOF 0x00000100 /* receive End-Of-Frame (read) */ 500a09e64fbSRussell King #define SDDR_CRE 0x00000200 /* receive CRC Error (read) */ 501a09e64fbSRussell King #define SDDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */ 502a09e64fbSRussell King #endif /* 0 */ 503a09e64fbSRussell King 504a09e64fbSRussell King #define SDSR0_EIF 0x00000001 /* Error In FIFO (read) */ 505a09e64fbSRussell King #define SDSR0_TUR 0x00000002 /* Transmit FIFO Under-Run */ 506a09e64fbSRussell King #define SDSR0_RAB 0x00000004 /* Receive ABort */ 507a09e64fbSRussell King #define SDSR0_TFS 0x00000008 /* Transmit FIFO 1/2-full or less */ 508a09e64fbSRussell King /* Service request (read) */ 509a09e64fbSRussell King #define SDSR0_RFS 0x00000010 /* Receive FIFO 1/3-to-2/3-full or */ 510a09e64fbSRussell King /* more Service request (read) */ 511a09e64fbSRussell King 512a09e64fbSRussell King #define SDSR1_RSY 0x00000001 /* Receiver SYnchronized (read) */ 513a09e64fbSRussell King #define SDSR1_TBY 0x00000002 /* Transmitter BusY (read) */ 514a09e64fbSRussell King #define SDSR1_RNE 0x00000004 /* Receive FIFO Not Empty (read) */ 515a09e64fbSRussell King #define SDSR1_TNF 0x00000008 /* Transmit FIFO Not Full (read) */ 516a09e64fbSRussell King #define SDSR1_RTD 0x00000010 /* Receive Transition Detected */ 517a09e64fbSRussell King #define SDSR1_EOF 0x00000020 /* receive End-Of-Frame (read) */ 518a09e64fbSRussell King #define SDSR1_CRE 0x00000040 /* receive CRC Error (read) */ 519a09e64fbSRussell King #define SDSR1_ROR 0x00000080 /* Receive FIFO Over-Run (read) */ 520a09e64fbSRussell King 521a09e64fbSRussell King 522a09e64fbSRussell King /* 523a09e64fbSRussell King * High-Speed Serial to Parallel controller (HSSP) control registers 524a09e64fbSRussell King * 525a09e64fbSRussell King * Registers 526a09e64fbSRussell King * Ser2HSCR0 Serial port 2 High-Speed Serial to Parallel 527a09e64fbSRussell King * controller (HSSP) Control Register 0 (read/write). 528a09e64fbSRussell King * Ser2HSCR1 Serial port 2 High-Speed Serial to Parallel 529a09e64fbSRussell King * controller (HSSP) Control Register 1 (read/write). 530a09e64fbSRussell King * Ser2HSDR Serial port 2 High-Speed Serial to Parallel 531a09e64fbSRussell King * controller (HSSP) Data Register (read/write). 532a09e64fbSRussell King * Ser2HSSR0 Serial port 2 High-Speed Serial to Parallel 533a09e64fbSRussell King * controller (HSSP) Status Register 0 (read/write). 534a09e64fbSRussell King * Ser2HSSR1 Serial port 2 High-Speed Serial to Parallel 535a09e64fbSRussell King * controller (HSSP) Status Register 1 (read). 536a09e64fbSRussell King * Ser2HSCR2 Serial port 2 High-Speed Serial to Parallel 537a09e64fbSRussell King * controller (HSSP) Control Register 2 (read/write). 538a09e64fbSRussell King * [The HSCR2 register is only implemented in 539a09e64fbSRussell King * versions 2.0 (rev. = 8) and higher of the StrongARM 540a09e64fbSRussell King * SA-1100.] 541a09e64fbSRussell King */ 542a09e64fbSRussell King 543a09e64fbSRussell King #define Ser2HSCR0 __REG(0x80040060) /* Ser. port 2 HSSP Control Reg. 0 */ 544a09e64fbSRussell King #define Ser2HSCR1 __REG(0x80040064) /* Ser. port 2 HSSP Control Reg. 1 */ 545a09e64fbSRussell King #define Ser2HSDR __REG(0x8004006C) /* Ser. port 2 HSSP Data Reg. */ 546a09e64fbSRussell King #define Ser2HSSR0 __REG(0x80040074) /* Ser. port 2 HSSP Status Reg. 0 */ 547a09e64fbSRussell King #define Ser2HSSR1 __REG(0x80040078) /* Ser. port 2 HSSP Status Reg. 1 */ 548a09e64fbSRussell King #define Ser2HSCR2 __REG(0x90060028) /* Ser. port 2 HSSP Control Reg. 2 */ 549a09e64fbSRussell King 550a09e64fbSRussell King #define HSCR0_ITR 0x00000001 /* IrDA Transmission Rate */ 551a09e64fbSRussell King #define HSCR0_UART (HSCR0_ITR*0) /* UART mode (115.2 kb/s if IrDA) */ 552a09e64fbSRussell King #define HSCR0_HSSP (HSCR0_ITR*1) /* HSSP mode (4 Mb/s) */ 553a09e64fbSRussell King #define HSCR0_LBM 0x00000002 /* Look-Back Mode */ 554a09e64fbSRussell King #define HSCR0_TUS 0x00000004 /* Transmit FIFO Under-run Select */ 555a09e64fbSRussell King #define HSCR0_EFrmURn (HSCR0_TUS*0) /* End Frame on Under-Run */ 556a09e64fbSRussell King #define HSCR0_AbortURn (HSCR0_TUS*1) /* Abort on Under-Run */ 557a09e64fbSRussell King #define HSCR0_TXE 0x00000008 /* Transmit Enable */ 558a09e64fbSRussell King #define HSCR0_RXE 0x00000010 /* Receive Enable */ 559a09e64fbSRussell King #define HSCR0_RIE 0x00000020 /* Receive FIFO 2/5-to-3/5-full or */ 560a09e64fbSRussell King /* more Interrupt Enable */ 561a09e64fbSRussell King #define HSCR0_TIE 0x00000040 /* Transmit FIFO 1/2-full or less */ 562a09e64fbSRussell King /* Interrupt Enable */ 563a09e64fbSRussell King #define HSCR0_AME 0x00000080 /* Address Match Enable */ 564a09e64fbSRussell King 565a09e64fbSRussell King #define HSCR1_AMV Fld (8, 0) /* Address Match Value */ 566a09e64fbSRussell King 567a09e64fbSRussell King #define HSDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ 568a09e64fbSRussell King #if 0 /* Hidden receive FIFO bits */ 569a09e64fbSRussell King #define HSDR_EOF 0x00000100 /* receive End-Of-Frame (read) */ 570a09e64fbSRussell King #define HSDR_CRE 0x00000200 /* receive CRC Error (read) */ 571a09e64fbSRussell King #define HSDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */ 572a09e64fbSRussell King #endif /* 0 */ 573a09e64fbSRussell King 574a09e64fbSRussell King #define HSSR0_EIF 0x00000001 /* Error In FIFO (read) */ 575a09e64fbSRussell King #define HSSR0_TUR 0x00000002 /* Transmit FIFO Under-Run */ 576a09e64fbSRussell King #define HSSR0_RAB 0x00000004 /* Receive ABort */ 577a09e64fbSRussell King #define HSSR0_TFS 0x00000008 /* Transmit FIFO 1/2-full or less */ 578a09e64fbSRussell King /* Service request (read) */ 579a09e64fbSRussell King #define HSSR0_RFS 0x00000010 /* Receive FIFO 2/5-to-3/5-full or */ 580a09e64fbSRussell King /* more Service request (read) */ 581a09e64fbSRussell King #define HSSR0_FRE 0x00000020 /* receive FRaming Error */ 582a09e64fbSRussell King 583a09e64fbSRussell King #define HSSR1_RSY 0x00000001 /* Receiver SYnchronized (read) */ 584a09e64fbSRussell King #define HSSR1_TBY 0x00000002 /* Transmitter BusY (read) */ 585a09e64fbSRussell King #define HSSR1_RNE 0x00000004 /* Receive FIFO Not Empty (read) */ 586a09e64fbSRussell King #define HSSR1_TNF 0x00000008 /* Transmit FIFO Not Full (read) */ 587a09e64fbSRussell King #define HSSR1_EOF 0x00000010 /* receive End-Of-Frame (read) */ 588a09e64fbSRussell King #define HSSR1_CRE 0x00000020 /* receive CRC Error (read) */ 589a09e64fbSRussell King #define HSSR1_ROR 0x00000040 /* Receive FIFO Over-Run (read) */ 590a09e64fbSRussell King 591a09e64fbSRussell King #define HSCR2_TXP 0x00040000 /* Transmit data Polarity (TXD_2) */ 592a09e64fbSRussell King #define HSCR2_TrDataL (HSCR2_TXP*0) /* Transmit Data active Low */ 593a09e64fbSRussell King /* (inverted) */ 594a09e64fbSRussell King #define HSCR2_TrDataH (HSCR2_TXP*1) /* Transmit Data active High */ 595a09e64fbSRussell King /* (non-inverted) */ 596a09e64fbSRussell King #define HSCR2_RXP 0x00080000 /* Receive data Polarity (RXD_2) */ 597a09e64fbSRussell King #define HSCR2_RcDataL (HSCR2_RXP*0) /* Receive Data active Low */ 598a09e64fbSRussell King /* (inverted) */ 599a09e64fbSRussell King #define HSCR2_RcDataH (HSCR2_RXP*1) /* Receive Data active High */ 600a09e64fbSRussell King /* (non-inverted) */ 601a09e64fbSRussell King 602a09e64fbSRussell King 603a09e64fbSRussell King /* 604a09e64fbSRussell King * Multi-media Communications Port (MCP) control registers 605a09e64fbSRussell King * 606a09e64fbSRussell King * Registers 607a09e64fbSRussell King * Ser4MCCR0 Serial port 4 Multi-media Communications Port (MCP) 608a09e64fbSRussell King * Control Register 0 (read/write). 609a09e64fbSRussell King * Ser4MCDR0 Serial port 4 Multi-media Communications Port (MCP) 610a09e64fbSRussell King * Data Register 0 (audio, read/write). 611a09e64fbSRussell King * Ser4MCDR1 Serial port 4 Multi-media Communications Port (MCP) 612a09e64fbSRussell King * Data Register 1 (telecom, read/write). 613a09e64fbSRussell King * Ser4MCDR2 Serial port 4 Multi-media Communications Port (MCP) 614a09e64fbSRussell King * Data Register 2 (CODEC registers, read/write). 615a09e64fbSRussell King * Ser4MCSR Serial port 4 Multi-media Communications Port (MCP) 616a09e64fbSRussell King * Status Register (read/write). 617a09e64fbSRussell King * Ser4MCCR1 Serial port 4 Multi-media Communications Port (MCP) 618a09e64fbSRussell King * Control Register 1 (read/write). 619a09e64fbSRussell King * [The MCCR1 register is only implemented in 620a09e64fbSRussell King * versions 2.0 (rev. = 8) and higher of the StrongARM 621a09e64fbSRussell King * SA-1100.] 622a09e64fbSRussell King * 623a09e64fbSRussell King * Clocks 624a09e64fbSRussell King * fmc, Tmc Frequency, period of the MCP communication (10 MHz, 625a09e64fbSRussell King * 12 MHz, or GPIO [21]). 626a09e64fbSRussell King * faud, Taud Frequency, period of the audio sampling. 627a09e64fbSRussell King * ftcm, Ttcm Frequency, period of the telecom sampling. 628a09e64fbSRussell King */ 629a09e64fbSRussell King 630a09e64fbSRussell King #define Ser4MCCR0 __REG(0x80060000) /* Ser. port 4 MCP Control Reg. 0 */ 631a09e64fbSRussell King #define Ser4MCDR0 __REG(0x80060008) /* Ser. port 4 MCP Data Reg. 0 (audio) */ 632a09e64fbSRussell King #define Ser4MCDR1 __REG(0x8006000C) /* Ser. port 4 MCP Data Reg. 1 (telecom) */ 633a09e64fbSRussell King #define Ser4MCDR2 __REG(0x80060010) /* Ser. port 4 MCP Data Reg. 2 (CODEC reg.) */ 634a09e64fbSRussell King #define Ser4MCSR __REG(0x80060018) /* Ser. port 4 MCP Status Reg. */ 635a09e64fbSRussell King #define Ser4MCCR1 __REG(0x90060030) /* Ser. port 4 MCP Control Reg. 1 */ 636a09e64fbSRussell King 637a09e64fbSRussell King #define MCCR0_ASD Fld (7, 0) /* Audio Sampling rate Divisor/32 */ 638a09e64fbSRussell King /* [6..127] */ 639a09e64fbSRussell King /* faud = fmc/(32*ASD) */ 640a09e64fbSRussell King /* Taud = 32*ASD*Tmc */ 641a09e64fbSRussell King #define MCCR0_AudSmpDiv(Div) /* Audio Sampling rate Divisor */ \ 642a09e64fbSRussell King /* [192..4064] */ \ 643a09e64fbSRussell King ((Div)/32 << FShft (MCCR0_ASD)) 644a09e64fbSRussell King /* faud = fmc/(32*Floor (Div/32)) */ 645a09e64fbSRussell King /* Taud = 32*Floor (Div/32)*Tmc */ 646a09e64fbSRussell King #define MCCR0_CeilAudSmpDiv(Div) /* Ceil. of AudSmpDiv [192..4064] */ \ 647a09e64fbSRussell King (((Div) + 31)/32 << FShft (MCCR0_ASD)) 648a09e64fbSRussell King /* faud = fmc/(32*Ceil (Div/32)) */ 649a09e64fbSRussell King /* Taud = 32*Ceil (Div/32)*Tmc */ 650a09e64fbSRussell King #define MCCR0_TSD Fld (7, 8) /* Telecom Sampling rate */ 651a09e64fbSRussell King /* Divisor/32 [16..127] */ 652a09e64fbSRussell King /* ftcm = fmc/(32*TSD) */ 653a09e64fbSRussell King /* Ttcm = 32*TSD*Tmc */ 654a09e64fbSRussell King #define MCCR0_TcmSmpDiv(Div) /* Telecom Sampling rate Divisor */ \ 655a09e64fbSRussell King /* [512..4064] */ \ 656a09e64fbSRussell King ((Div)/32 << FShft (MCCR0_TSD)) 657a09e64fbSRussell King /* ftcm = fmc/(32*Floor (Div/32)) */ 658a09e64fbSRussell King /* Ttcm = 32*Floor (Div/32)*Tmc */ 659a09e64fbSRussell King #define MCCR0_CeilTcmSmpDiv(Div) /* Ceil. of TcmSmpDiv [512..4064] */ \ 660a09e64fbSRussell King (((Div) + 31)/32 << FShft (MCCR0_TSD)) 661a09e64fbSRussell King /* ftcm = fmc/(32*Ceil (Div/32)) */ 662a09e64fbSRussell King /* Ttcm = 32*Ceil (Div/32)*Tmc */ 663a09e64fbSRussell King #define MCCR0_MCE 0x00010000 /* MCP Enable */ 664a09e64fbSRussell King #define MCCR0_ECS 0x00020000 /* External Clock Select */ 665a09e64fbSRussell King #define MCCR0_IntClk (MCCR0_ECS*0) /* Internal Clock (10 or 12 MHz) */ 666a09e64fbSRussell King #define MCCR0_ExtClk (MCCR0_ECS*1) /* External Clock (GPIO [21]) */ 667a09e64fbSRussell King #define MCCR0_ADM 0x00040000 /* A/D (audio/telecom) data */ 668a09e64fbSRussell King /* sampling/storing Mode */ 669a09e64fbSRussell King #define MCCR0_VldBit (MCCR0_ADM*0) /* Valid Bit storing mode */ 670a09e64fbSRussell King #define MCCR0_SmpCnt (MCCR0_ADM*1) /* Sampling Counter storing mode */ 671a09e64fbSRussell King #define MCCR0_TTE 0x00080000 /* Telecom Transmit FIFO 1/2-full */ 672a09e64fbSRussell King /* or less interrupt Enable */ 673a09e64fbSRussell King #define MCCR0_TRE 0x00100000 /* Telecom Receive FIFO 1/2-full */ 674a09e64fbSRussell King /* or more interrupt Enable */ 675a09e64fbSRussell King #define MCCR0_ATE 0x00200000 /* Audio Transmit FIFO 1/2-full */ 676a09e64fbSRussell King /* or less interrupt Enable */ 677a09e64fbSRussell King #define MCCR0_ARE 0x00400000 /* Audio Receive FIFO 1/2-full or */ 678a09e64fbSRussell King /* more interrupt Enable */ 679a09e64fbSRussell King #define MCCR0_LBM 0x00800000 /* Look-Back Mode */ 680a09e64fbSRussell King #define MCCR0_ECP Fld (2, 24) /* External Clock Prescaler - 1 */ 681a09e64fbSRussell King #define MCCR0_ExtClkDiv(Div) /* External Clock Divisor [1..4] */ \ 682a09e64fbSRussell King (((Div) - 1) << FShft (MCCR0_ECP)) 683a09e64fbSRussell King 684a09e64fbSRussell King #define MCDR0_DATA Fld (12, 4) /* receive/transmit audio DATA */ 685a09e64fbSRussell King /* FIFOs */ 686a09e64fbSRussell King 687a09e64fbSRussell King #define MCDR1_DATA Fld (14, 2) /* receive/transmit telecom DATA */ 688a09e64fbSRussell King /* FIFOs */ 689a09e64fbSRussell King 690a09e64fbSRussell King /* receive/transmit CODEC reg. */ 691a09e64fbSRussell King /* FIFOs: */ 692a09e64fbSRussell King #define MCDR2_DATA Fld (16, 0) /* reg. DATA */ 693a09e64fbSRussell King #define MCDR2_RW 0x00010000 /* reg. Read/Write (transmit) */ 694a09e64fbSRussell King #define MCDR2_Rd (MCDR2_RW*0) /* reg. Read */ 695a09e64fbSRussell King #define MCDR2_Wr (MCDR2_RW*1) /* reg. Write */ 696a09e64fbSRussell King #define MCDR2_ADD Fld (4, 17) /* reg. ADDress */ 697a09e64fbSRussell King 698a09e64fbSRussell King #define MCSR_ATS 0x00000001 /* Audio Transmit FIFO 1/2-full */ 699a09e64fbSRussell King /* or less Service request (read) */ 700a09e64fbSRussell King #define MCSR_ARS 0x00000002 /* Audio Receive FIFO 1/2-full or */ 701a09e64fbSRussell King /* more Service request (read) */ 702a09e64fbSRussell King #define MCSR_TTS 0x00000004 /* Telecom Transmit FIFO 1/2-full */ 703a09e64fbSRussell King /* or less Service request (read) */ 704a09e64fbSRussell King #define MCSR_TRS 0x00000008 /* Telecom Receive FIFO 1/2-full */ 705a09e64fbSRussell King /* or more Service request (read) */ 706a09e64fbSRussell King #define MCSR_ATU 0x00000010 /* Audio Transmit FIFO Under-run */ 707a09e64fbSRussell King #define MCSR_ARO 0x00000020 /* Audio Receive FIFO Over-run */ 708a09e64fbSRussell King #define MCSR_TTU 0x00000040 /* Telecom Transmit FIFO Under-run */ 709a09e64fbSRussell King #define MCSR_TRO 0x00000080 /* Telecom Receive FIFO Over-run */ 710a09e64fbSRussell King #define MCSR_ANF 0x00000100 /* Audio transmit FIFO Not Full */ 711a09e64fbSRussell King /* (read) */ 712a09e64fbSRussell King #define MCSR_ANE 0x00000200 /* Audio receive FIFO Not Empty */ 713a09e64fbSRussell King /* (read) */ 714a09e64fbSRussell King #define MCSR_TNF 0x00000400 /* Telecom transmit FIFO Not Full */ 715a09e64fbSRussell King /* (read) */ 716a09e64fbSRussell King #define MCSR_TNE 0x00000800 /* Telecom receive FIFO Not Empty */ 717a09e64fbSRussell King /* (read) */ 718a09e64fbSRussell King #define MCSR_CWC 0x00001000 /* CODEC register Write Completed */ 719a09e64fbSRussell King /* (read) */ 720a09e64fbSRussell King #define MCSR_CRC 0x00002000 /* CODEC register Read Completed */ 721a09e64fbSRussell King /* (read) */ 722a09e64fbSRussell King #define MCSR_ACE 0x00004000 /* Audio CODEC Enabled (read) */ 723a09e64fbSRussell King #define MCSR_TCE 0x00008000 /* Telecom CODEC Enabled (read) */ 724a09e64fbSRussell King 725a09e64fbSRussell King #define MCCR1_CFS 0x00100000 /* Clock Freq. Select */ 726a09e64fbSRussell King #define MCCR1_F12MHz (MCCR1_CFS*0) /* Freq. (fmc) = ~ 12 MHz */ 727a09e64fbSRussell King /* (11.981 MHz) */ 728a09e64fbSRussell King #define MCCR1_F10MHz (MCCR1_CFS*1) /* Freq. (fmc) = ~ 10 MHz */ 729a09e64fbSRussell King /* (9.585 MHz) */ 730a09e64fbSRussell King 731a09e64fbSRussell King 732a09e64fbSRussell King /* 733a09e64fbSRussell King * Synchronous Serial Port (SSP) control registers 734a09e64fbSRussell King * 735a09e64fbSRussell King * Registers 736a09e64fbSRussell King * Ser4SSCR0 Serial port 4 Synchronous Serial Port (SSP) Control 737a09e64fbSRussell King * Register 0 (read/write). 738a09e64fbSRussell King * Ser4SSCR1 Serial port 4 Synchronous Serial Port (SSP) Control 739a09e64fbSRussell King * Register 1 (read/write). 740a09e64fbSRussell King * [Bits SPO and SP are only implemented in versions 2.0 741a09e64fbSRussell King * (rev. = 8) and higher of the StrongARM SA-1100.] 742a09e64fbSRussell King * Ser4SSDR Serial port 4 Synchronous Serial Port (SSP) Data 743a09e64fbSRussell King * Register (read/write). 744a09e64fbSRussell King * Ser4SSSR Serial port 4 Synchronous Serial Port (SSP) Status 745a09e64fbSRussell King * Register (read/write). 746a09e64fbSRussell King * 747a09e64fbSRussell King * Clocks 748a09e64fbSRussell King * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz 749a09e64fbSRussell King * or 3.5795 MHz). 750a09e64fbSRussell King * fss, Tss Frequency, period of the SSP communication. 751a09e64fbSRussell King */ 752a09e64fbSRussell King 753a09e64fbSRussell King #define Ser4SSCR0 __REG(0x80070060) /* Ser. port 4 SSP Control Reg. 0 */ 754a09e64fbSRussell King #define Ser4SSCR1 __REG(0x80070064) /* Ser. port 4 SSP Control Reg. 1 */ 755a09e64fbSRussell King #define Ser4SSDR __REG(0x8007006C) /* Ser. port 4 SSP Data Reg. */ 756a09e64fbSRussell King #define Ser4SSSR __REG(0x80070074) /* Ser. port 4 SSP Status Reg. */ 757a09e64fbSRussell King 758a09e64fbSRussell King #define SSCR0_DSS Fld (4, 0) /* Data Size - 1 Select [3..15] */ 759a09e64fbSRussell King #define SSCR0_DataSize(Size) /* Data Size Select [4..16] */ \ 760a09e64fbSRussell King (((Size) - 1) << FShft (SSCR0_DSS)) 761a09e64fbSRussell King #define SSCR0_FRF Fld (2, 4) /* FRame Format */ 762a09e64fbSRussell King #define SSCR0_Motorola /* Motorola Serial Peripheral */ \ 763a09e64fbSRussell King /* Interface (SPI) format */ \ 764a09e64fbSRussell King (0 << FShft (SSCR0_FRF)) 765a09e64fbSRussell King #define SSCR0_TI /* Texas Instruments Synchronous */ \ 766a09e64fbSRussell King /* Serial format */ \ 767a09e64fbSRussell King (1 << FShft (SSCR0_FRF)) 768a09e64fbSRussell King #define SSCR0_National /* National Microwire format */ \ 769a09e64fbSRussell King (2 << FShft (SSCR0_FRF)) 770a09e64fbSRussell King #define SSCR0_SSE 0x00000080 /* SSP Enable */ 771a09e64fbSRussell King #define SSCR0_SCR Fld (8, 8) /* Serial Clock Rate divisor/2 - 1 */ 772a09e64fbSRussell King /* fss = fxtl/(2*(SCR + 1)) */ 773a09e64fbSRussell King /* Tss = 2*(SCR + 1)*Txtl */ 774a09e64fbSRussell King #define SSCR0_SerClkDiv(Div) /* Serial Clock Divisor [2..512] */ \ 775a09e64fbSRussell King (((Div) - 2)/2 << FShft (SSCR0_SCR)) 776a09e64fbSRussell King /* fss = fxtl/(2*Floor (Div/2)) */ 777a09e64fbSRussell King /* Tss = 2*Floor (Div/2)*Txtl */ 778a09e64fbSRussell King #define SSCR0_CeilSerClkDiv(Div) /* Ceil. of SerClkDiv [2..512] */ \ 779a09e64fbSRussell King (((Div) - 1)/2 << FShft (SSCR0_SCR)) 780a09e64fbSRussell King /* fss = fxtl/(2*Ceil (Div/2)) */ 781a09e64fbSRussell King /* Tss = 2*Ceil (Div/2)*Txtl */ 782a09e64fbSRussell King 783a09e64fbSRussell King #define SSCR1_RIE 0x00000001 /* Receive FIFO 1/2-full or more */ 784a09e64fbSRussell King /* Interrupt Enable */ 785a09e64fbSRussell King #define SSCR1_TIE 0x00000002 /* Transmit FIFO 1/2-full or less */ 786a09e64fbSRussell King /* Interrupt Enable */ 787a09e64fbSRussell King #define SSCR1_LBM 0x00000004 /* Look-Back Mode */ 788a09e64fbSRussell King #define SSCR1_SPO 0x00000008 /* Sample clock (SCLK) POlarity */ 789a09e64fbSRussell King #define SSCR1_SClkIactL (SSCR1_SPO*0) /* Sample Clock Inactive Low */ 790a09e64fbSRussell King #define SSCR1_SClkIactH (SSCR1_SPO*1) /* Sample Clock Inactive High */ 791a09e64fbSRussell King #define SSCR1_SP 0x00000010 /* Sample clock (SCLK) Phase */ 792a09e64fbSRussell King #define SSCR1_SClk1P (SSCR1_SP*0) /* Sample Clock active 1 Period */ 793a09e64fbSRussell King /* after frame (SFRM, 1st edge) */ 794a09e64fbSRussell King #define SSCR1_SClk1_2P (SSCR1_SP*1) /* Sample Clock active 1/2 Period */ 795a09e64fbSRussell King /* after frame (SFRM, 1st edge) */ 796a09e64fbSRussell King #define SSCR1_ECS 0x00000020 /* External Clock Select */ 797a09e64fbSRussell King #define SSCR1_IntClk (SSCR1_ECS*0) /* Internal Clock */ 798a09e64fbSRussell King #define SSCR1_ExtClk (SSCR1_ECS*1) /* External Clock (GPIO [19]) */ 799a09e64fbSRussell King 800a09e64fbSRussell King #define SSDR_DATA Fld (16, 0) /* receive/transmit DATA FIFOs */ 801a09e64fbSRussell King 802a09e64fbSRussell King #define SSSR_TNF 0x00000002 /* Transmit FIFO Not Full (read) */ 803a09e64fbSRussell King #define SSSR_RNE 0x00000004 /* Receive FIFO Not Empty (read) */ 804a09e64fbSRussell King #define SSSR_BSY 0x00000008 /* SSP BuSY (read) */ 805a09e64fbSRussell King #define SSSR_TFS 0x00000010 /* Transmit FIFO 1/2-full or less */ 806a09e64fbSRussell King /* Service request (read) */ 807a09e64fbSRussell King #define SSSR_RFS 0x00000020 /* Receive FIFO 1/2-full or more */ 808a09e64fbSRussell King /* Service request (read) */ 809a09e64fbSRussell King #define SSSR_ROR 0x00000040 /* Receive FIFO Over-Run */ 810a09e64fbSRussell King 811a09e64fbSRussell King 812a09e64fbSRussell King /* 813a09e64fbSRussell King * Operating System (OS) timer control registers 814a09e64fbSRussell King * 815a09e64fbSRussell King * Registers 816a09e64fbSRussell King * OSMR0 Operating System (OS) timer Match Register 0 817a09e64fbSRussell King * (read/write). 818a09e64fbSRussell King * OSMR1 Operating System (OS) timer Match Register 1 819a09e64fbSRussell King * (read/write). 820a09e64fbSRussell King * OSMR2 Operating System (OS) timer Match Register 2 821a09e64fbSRussell King * (read/write). 822a09e64fbSRussell King * OSMR3 Operating System (OS) timer Match Register 3 823a09e64fbSRussell King * (read/write). 824a09e64fbSRussell King * OSCR Operating System (OS) timer Counter Register 825a09e64fbSRussell King * (read/write). 826a09e64fbSRussell King * OSSR Operating System (OS) timer Status Register 827a09e64fbSRussell King * (read/write). 828a09e64fbSRussell King * OWER Operating System (OS) timer Watch-dog Enable Register 829a09e64fbSRussell King * (read/write). 830a09e64fbSRussell King * OIER Operating System (OS) timer Interrupt Enable Register 831a09e64fbSRussell King * (read/write). 832a09e64fbSRussell King */ 833a09e64fbSRussell King 8343169663aSRussell King #define OSMR0 io_p2v(0x90000000) /* OS timer Match Reg. 0 */ 8353169663aSRussell King #define OSMR1 io_p2v(0x90000004) /* OS timer Match Reg. 1 */ 8363169663aSRussell King #define OSMR2 io_p2v(0x90000008) /* OS timer Match Reg. 2 */ 8373169663aSRussell King #define OSMR3 io_p2v(0x9000000c) /* OS timer Match Reg. 3 */ 8383169663aSRussell King #define OSCR io_p2v(0x90000010) /* OS timer Counter Reg. */ 8393169663aSRussell King #define OSSR io_p2v(0x90000014) /* OS timer Status Reg. */ 8403169663aSRussell King #define OWER io_p2v(0x90000018) /* OS timer Watch-dog Enable Reg. */ 8413169663aSRussell King #define OIER io_p2v(0x9000001C) /* OS timer Interrupt Enable Reg. */ 842a09e64fbSRussell King 843a09e64fbSRussell King #define OSSR_M(Nb) /* Match detected [0..3] */ \ 844a09e64fbSRussell King (0x00000001 << (Nb)) 845a09e64fbSRussell King #define OSSR_M0 OSSR_M (0) /* Match detected 0 */ 846a09e64fbSRussell King #define OSSR_M1 OSSR_M (1) /* Match detected 1 */ 847a09e64fbSRussell King #define OSSR_M2 OSSR_M (2) /* Match detected 2 */ 848a09e64fbSRussell King #define OSSR_M3 OSSR_M (3) /* Match detected 3 */ 849a09e64fbSRussell King 850a09e64fbSRussell King #define OWER_WME 0x00000001 /* Watch-dog Match Enable */ 851a09e64fbSRussell King /* (set only) */ 852a09e64fbSRussell King 853a09e64fbSRussell King #define OIER_E(Nb) /* match interrupt Enable [0..3] */ \ 854a09e64fbSRussell King (0x00000001 << (Nb)) 855a09e64fbSRussell King #define OIER_E0 OIER_E (0) /* match interrupt Enable 0 */ 856a09e64fbSRussell King #define OIER_E1 OIER_E (1) /* match interrupt Enable 1 */ 857a09e64fbSRussell King #define OIER_E2 OIER_E (2) /* match interrupt Enable 2 */ 858a09e64fbSRussell King #define OIER_E3 OIER_E (3) /* match interrupt Enable 3 */ 859a09e64fbSRussell King 860a09e64fbSRussell King 861a09e64fbSRussell King /* 862a09e64fbSRussell King * Power Manager (PM) control registers 863a09e64fbSRussell King * 864a09e64fbSRussell King * Registers 865a09e64fbSRussell King * PMCR Power Manager (PM) Control Register (read/write). 866a09e64fbSRussell King * PSSR Power Manager (PM) Sleep Status Register (read/write). 867a09e64fbSRussell King * PSPR Power Manager (PM) Scratch-Pad Register (read/write). 868a09e64fbSRussell King * PWER Power Manager (PM) Wake-up Enable Register 869a09e64fbSRussell King * (read/write). 870a09e64fbSRussell King * PCFR Power Manager (PM) general ConFiguration Register 871a09e64fbSRussell King * (read/write). 872a09e64fbSRussell King * PPCR Power Manager (PM) Phase-Locked Loop (PLL) 873a09e64fbSRussell King * Configuration Register (read/write). 874a09e64fbSRussell King * PGSR Power Manager (PM) General-Purpose Input/Output (GPIO) 875a09e64fbSRussell King * Sleep state Register (read/write, see GPIO pins). 876a09e64fbSRussell King * POSR Power Manager (PM) Oscillator Status Register (read). 877a09e64fbSRussell King * 878a09e64fbSRussell King * Clocks 879a09e64fbSRussell King * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz 880a09e64fbSRussell King * or 3.5795 MHz). 881a09e64fbSRussell King * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). 882a09e64fbSRussell King */ 883a09e64fbSRussell King 884a09e64fbSRussell King #define PMCR __REG(0x90020000) /* PM Control Reg. */ 885a09e64fbSRussell King #define PSSR __REG(0x90020004) /* PM Sleep Status Reg. */ 886a09e64fbSRussell King #define PSPR __REG(0x90020008) /* PM Scratch-Pad Reg. */ 887a09e64fbSRussell King #define PWER __REG(0x9002000C) /* PM Wake-up Enable Reg. */ 888a09e64fbSRussell King #define PCFR __REG(0x90020010) /* PM general ConFiguration Reg. */ 889a09e64fbSRussell King #define PPCR __REG(0x90020014) /* PM PLL Configuration Reg. */ 890a09e64fbSRussell King #define PGSR __REG(0x90020018) /* PM GPIO Sleep state Reg. */ 891a09e64fbSRussell King #define POSR __REG(0x9002001C) /* PM Oscillator Status Reg. */ 892a09e64fbSRussell King 893a09e64fbSRussell King #define PMCR_SF 0x00000001 /* Sleep Force (set only) */ 894a09e64fbSRussell King 895a09e64fbSRussell King #define PSSR_SS 0x00000001 /* Software Sleep */ 896a09e64fbSRussell King #define PSSR_BFS 0x00000002 /* Battery Fault Status */ 897a09e64fbSRussell King /* (BATT_FAULT) */ 898a09e64fbSRussell King #define PSSR_VFS 0x00000004 /* Vdd Fault Status (VDD_FAULT) */ 899a09e64fbSRussell King #define PSSR_DH 0x00000008 /* DRAM control Hold */ 900a09e64fbSRussell King #define PSSR_PH 0x00000010 /* Peripheral control Hold */ 901a09e64fbSRussell King 902a09e64fbSRussell King #define PWER_GPIO(Nb) GPIO_GPIO (Nb) /* GPIO [0..27] wake-up enable */ 903a09e64fbSRussell King #define PWER_GPIO0 PWER_GPIO (0) /* GPIO [0] wake-up enable */ 904a09e64fbSRussell King #define PWER_GPIO1 PWER_GPIO (1) /* GPIO [1] wake-up enable */ 905a09e64fbSRussell King #define PWER_GPIO2 PWER_GPIO (2) /* GPIO [2] wake-up enable */ 906a09e64fbSRussell King #define PWER_GPIO3 PWER_GPIO (3) /* GPIO [3] wake-up enable */ 907a09e64fbSRussell King #define PWER_GPIO4 PWER_GPIO (4) /* GPIO [4] wake-up enable */ 908a09e64fbSRussell King #define PWER_GPIO5 PWER_GPIO (5) /* GPIO [5] wake-up enable */ 909a09e64fbSRussell King #define PWER_GPIO6 PWER_GPIO (6) /* GPIO [6] wake-up enable */ 910a09e64fbSRussell King #define PWER_GPIO7 PWER_GPIO (7) /* GPIO [7] wake-up enable */ 911a09e64fbSRussell King #define PWER_GPIO8 PWER_GPIO (8) /* GPIO [8] wake-up enable */ 912a09e64fbSRussell King #define PWER_GPIO9 PWER_GPIO (9) /* GPIO [9] wake-up enable */ 913a09e64fbSRussell King #define PWER_GPIO10 PWER_GPIO (10) /* GPIO [10] wake-up enable */ 914a09e64fbSRussell King #define PWER_GPIO11 PWER_GPIO (11) /* GPIO [11] wake-up enable */ 915a09e64fbSRussell King #define PWER_GPIO12 PWER_GPIO (12) /* GPIO [12] wake-up enable */ 916a09e64fbSRussell King #define PWER_GPIO13 PWER_GPIO (13) /* GPIO [13] wake-up enable */ 917a09e64fbSRussell King #define PWER_GPIO14 PWER_GPIO (14) /* GPIO [14] wake-up enable */ 918a09e64fbSRussell King #define PWER_GPIO15 PWER_GPIO (15) /* GPIO [15] wake-up enable */ 919a09e64fbSRussell King #define PWER_GPIO16 PWER_GPIO (16) /* GPIO [16] wake-up enable */ 920a09e64fbSRussell King #define PWER_GPIO17 PWER_GPIO (17) /* GPIO [17] wake-up enable */ 921a09e64fbSRussell King #define PWER_GPIO18 PWER_GPIO (18) /* GPIO [18] wake-up enable */ 922a09e64fbSRussell King #define PWER_GPIO19 PWER_GPIO (19) /* GPIO [19] wake-up enable */ 923a09e64fbSRussell King #define PWER_GPIO20 PWER_GPIO (20) /* GPIO [20] wake-up enable */ 924a09e64fbSRussell King #define PWER_GPIO21 PWER_GPIO (21) /* GPIO [21] wake-up enable */ 925a09e64fbSRussell King #define PWER_GPIO22 PWER_GPIO (22) /* GPIO [22] wake-up enable */ 926a09e64fbSRussell King #define PWER_GPIO23 PWER_GPIO (23) /* GPIO [23] wake-up enable */ 927a09e64fbSRussell King #define PWER_GPIO24 PWER_GPIO (24) /* GPIO [24] wake-up enable */ 928a09e64fbSRussell King #define PWER_GPIO25 PWER_GPIO (25) /* GPIO [25] wake-up enable */ 929a09e64fbSRussell King #define PWER_GPIO26 PWER_GPIO (26) /* GPIO [26] wake-up enable */ 930a09e64fbSRussell King #define PWER_GPIO27 PWER_GPIO (27) /* GPIO [27] wake-up enable */ 931a09e64fbSRussell King #define PWER_RTC 0x80000000 /* RTC alarm wake-up enable */ 932a09e64fbSRussell King 933a09e64fbSRussell King #define PCFR_OPDE 0x00000001 /* Oscillator Power-Down Enable */ 934a09e64fbSRussell King #define PCFR_ClkRun (PCFR_OPDE*0) /* Clock Running in sleep mode */ 935a09e64fbSRussell King #define PCFR_ClkStp (PCFR_OPDE*1) /* Clock Stopped in sleep mode */ 936a09e64fbSRussell King #define PCFR_FP 0x00000002 /* Float PCMCIA pins */ 937a09e64fbSRussell King #define PCFR_PCMCIANeg (PCFR_FP*0) /* PCMCIA pins Negated (1) */ 938a09e64fbSRussell King #define PCFR_PCMCIAFlt (PCFR_FP*1) /* PCMCIA pins Floating */ 939a09e64fbSRussell King #define PCFR_FS 0x00000004 /* Float Static memory pins */ 940a09e64fbSRussell King #define PCFR_StMemNeg (PCFR_FS*0) /* Static Memory pins Negated (1) */ 941a09e64fbSRussell King #define PCFR_StMemFlt (PCFR_FS*1) /* Static Memory pins Floating */ 942a09e64fbSRussell King #define PCFR_FO 0x00000008 /* Force RTC oscillator */ 943a09e64fbSRussell King /* (32.768 kHz) enable On */ 944a09e64fbSRussell King 945a09e64fbSRussell King #define PPCR_CCF Fld (5, 0) /* CPU core Clock (CCLK) Freq. */ 946a09e64fbSRussell King #define PPCR_Fx16 /* Freq. x 16 (fcpu = 16*fxtl) */ \ 947a09e64fbSRussell King (0x00 << FShft (PPCR_CCF)) 948a09e64fbSRussell King #define PPCR_Fx20 /* Freq. x 20 (fcpu = 20*fxtl) */ \ 949a09e64fbSRussell King (0x01 << FShft (PPCR_CCF)) 950a09e64fbSRussell King #define PPCR_Fx24 /* Freq. x 24 (fcpu = 24*fxtl) */ \ 951a09e64fbSRussell King (0x02 << FShft (PPCR_CCF)) 952a09e64fbSRussell King #define PPCR_Fx28 /* Freq. x 28 (fcpu = 28*fxtl) */ \ 953a09e64fbSRussell King (0x03 << FShft (PPCR_CCF)) 954a09e64fbSRussell King #define PPCR_Fx32 /* Freq. x 32 (fcpu = 32*fxtl) */ \ 955a09e64fbSRussell King (0x04 << FShft (PPCR_CCF)) 956a09e64fbSRussell King #define PPCR_Fx36 /* Freq. x 36 (fcpu = 36*fxtl) */ \ 957a09e64fbSRussell King (0x05 << FShft (PPCR_CCF)) 958a09e64fbSRussell King #define PPCR_Fx40 /* Freq. x 40 (fcpu = 40*fxtl) */ \ 959a09e64fbSRussell King (0x06 << FShft (PPCR_CCF)) 960a09e64fbSRussell King #define PPCR_Fx44 /* Freq. x 44 (fcpu = 44*fxtl) */ \ 961a09e64fbSRussell King (0x07 << FShft (PPCR_CCF)) 962a09e64fbSRussell King #define PPCR_Fx48 /* Freq. x 48 (fcpu = 48*fxtl) */ \ 963a09e64fbSRussell King (0x08 << FShft (PPCR_CCF)) 964a09e64fbSRussell King #define PPCR_Fx52 /* Freq. x 52 (fcpu = 52*fxtl) */ \ 965a09e64fbSRussell King (0x09 << FShft (PPCR_CCF)) 966a09e64fbSRussell King #define PPCR_Fx56 /* Freq. x 56 (fcpu = 56*fxtl) */ \ 967a09e64fbSRussell King (0x0A << FShft (PPCR_CCF)) 968a09e64fbSRussell King #define PPCR_Fx60 /* Freq. x 60 (fcpu = 60*fxtl) */ \ 969a09e64fbSRussell King (0x0B << FShft (PPCR_CCF)) 970a09e64fbSRussell King #define PPCR_Fx64 /* Freq. x 64 (fcpu = 64*fxtl) */ \ 971a09e64fbSRussell King (0x0C << FShft (PPCR_CCF)) 972a09e64fbSRussell King #define PPCR_Fx68 /* Freq. x 68 (fcpu = 68*fxtl) */ \ 973a09e64fbSRussell King (0x0D << FShft (PPCR_CCF)) 974a09e64fbSRussell King #define PPCR_Fx72 /* Freq. x 72 (fcpu = 72*fxtl) */ \ 975a09e64fbSRussell King (0x0E << FShft (PPCR_CCF)) 976a09e64fbSRussell King #define PPCR_Fx76 /* Freq. x 76 (fcpu = 76*fxtl) */ \ 977a09e64fbSRussell King (0x0F << FShft (PPCR_CCF)) 978a09e64fbSRussell King /* 3.6864 MHz crystal (fxtl): */ 979a09e64fbSRussell King #define PPCR_F59_0MHz PPCR_Fx16 /* Freq. (fcpu) = 59.0 MHz */ 980a09e64fbSRussell King #define PPCR_F73_7MHz PPCR_Fx20 /* Freq. (fcpu) = 73.7 MHz */ 981a09e64fbSRussell King #define PPCR_F88_5MHz PPCR_Fx24 /* Freq. (fcpu) = 88.5 MHz */ 982a09e64fbSRussell King #define PPCR_F103_2MHz PPCR_Fx28 /* Freq. (fcpu) = 103.2 MHz */ 983a09e64fbSRussell King #define PPCR_F118_0MHz PPCR_Fx32 /* Freq. (fcpu) = 118.0 MHz */ 984a09e64fbSRussell King #define PPCR_F132_7MHz PPCR_Fx36 /* Freq. (fcpu) = 132.7 MHz */ 985a09e64fbSRussell King #define PPCR_F147_5MHz PPCR_Fx40 /* Freq. (fcpu) = 147.5 MHz */ 986a09e64fbSRussell King #define PPCR_F162_2MHz PPCR_Fx44 /* Freq. (fcpu) = 162.2 MHz */ 987a09e64fbSRussell King #define PPCR_F176_9MHz PPCR_Fx48 /* Freq. (fcpu) = 176.9 MHz */ 988a09e64fbSRussell King #define PPCR_F191_7MHz PPCR_Fx52 /* Freq. (fcpu) = 191.7 MHz */ 989a09e64fbSRussell King #define PPCR_F206_4MHz PPCR_Fx56 /* Freq. (fcpu) = 206.4 MHz */ 990a09e64fbSRussell King #define PPCR_F221_2MHz PPCR_Fx60 /* Freq. (fcpu) = 221.2 MHz */ 991a09e64fbSRussell King #define PPCR_F239_6MHz PPCR_Fx64 /* Freq. (fcpu) = 239.6 MHz */ 992a09e64fbSRussell King #define PPCR_F250_7MHz PPCR_Fx68 /* Freq. (fcpu) = 250.7 MHz */ 993a09e64fbSRussell King #define PPCR_F265_4MHz PPCR_Fx72 /* Freq. (fcpu) = 265.4 MHz */ 994a09e64fbSRussell King #define PPCR_F280_2MHz PPCR_Fx76 /* Freq. (fcpu) = 280.2 MHz */ 995a09e64fbSRussell King /* 3.5795 MHz crystal (fxtl): */ 996a09e64fbSRussell King #define PPCR_F57_3MHz PPCR_Fx16 /* Freq. (fcpu) = 57.3 MHz */ 997a09e64fbSRussell King #define PPCR_F71_6MHz PPCR_Fx20 /* Freq. (fcpu) = 71.6 MHz */ 998a09e64fbSRussell King #define PPCR_F85_9MHz PPCR_Fx24 /* Freq. (fcpu) = 85.9 MHz */ 999a09e64fbSRussell King #define PPCR_F100_2MHz PPCR_Fx28 /* Freq. (fcpu) = 100.2 MHz */ 1000a09e64fbSRussell King #define PPCR_F114_5MHz PPCR_Fx32 /* Freq. (fcpu) = 114.5 MHz */ 1001a09e64fbSRussell King #define PPCR_F128_9MHz PPCR_Fx36 /* Freq. (fcpu) = 128.9 MHz */ 1002a09e64fbSRussell King #define PPCR_F143_2MHz PPCR_Fx40 /* Freq. (fcpu) = 143.2 MHz */ 1003a09e64fbSRussell King #define PPCR_F157_5MHz PPCR_Fx44 /* Freq. (fcpu) = 157.5 MHz */ 1004a09e64fbSRussell King #define PPCR_F171_8MHz PPCR_Fx48 /* Freq. (fcpu) = 171.8 MHz */ 1005a09e64fbSRussell King #define PPCR_F186_1MHz PPCR_Fx52 /* Freq. (fcpu) = 186.1 MHz */ 1006a09e64fbSRussell King #define PPCR_F200_5MHz PPCR_Fx56 /* Freq. (fcpu) = 200.5 MHz */ 1007a09e64fbSRussell King #define PPCR_F214_8MHz PPCR_Fx60 /* Freq. (fcpu) = 214.8 MHz */ 1008a09e64fbSRussell King #define PPCR_F229_1MHz PPCR_Fx64 /* Freq. (fcpu) = 229.1 MHz */ 1009a09e64fbSRussell King #define PPCR_F243_4MHz PPCR_Fx68 /* Freq. (fcpu) = 243.4 MHz */ 1010a09e64fbSRussell King #define PPCR_F257_7MHz PPCR_Fx72 /* Freq. (fcpu) = 257.7 MHz */ 1011a09e64fbSRussell King #define PPCR_F272_0MHz PPCR_Fx76 /* Freq. (fcpu) = 272.0 MHz */ 1012a09e64fbSRussell King 1013a09e64fbSRussell King #define POSR_OOK 0x00000001 /* RTC Oscillator (32.768 kHz) OK */ 1014a09e64fbSRussell King 1015a09e64fbSRussell King 1016a09e64fbSRussell King /* 1017a09e64fbSRussell King * Reset Controller (RC) control registers 1018a09e64fbSRussell King * 1019a09e64fbSRussell King * Registers 1020a09e64fbSRussell King * RSRR Reset Controller (RC) Software Reset Register 1021a09e64fbSRussell King * (read/write). 1022a09e64fbSRussell King * RCSR Reset Controller (RC) Status Register (read/write). 1023a09e64fbSRussell King */ 1024a09e64fbSRussell King 1025a09e64fbSRussell King #define RSRR __REG(0x90030000) /* RC Software Reset Reg. */ 1026a09e64fbSRussell King #define RCSR __REG(0x90030004) /* RC Status Reg. */ 1027a09e64fbSRussell King 1028a09e64fbSRussell King #define RSRR_SWR 0x00000001 /* SoftWare Reset (set only) */ 1029a09e64fbSRussell King 1030a09e64fbSRussell King #define RCSR_HWR 0x00000001 /* HardWare Reset */ 1031a09e64fbSRussell King #define RCSR_SWR 0x00000002 /* SoftWare Reset */ 1032a09e64fbSRussell King #define RCSR_WDR 0x00000004 /* Watch-Dog Reset */ 1033a09e64fbSRussell King #define RCSR_SMR 0x00000008 /* Sleep-Mode Reset */ 1034a09e64fbSRussell King 1035a09e64fbSRussell King 1036a09e64fbSRussell King /* 1037a09e64fbSRussell King * Test unit control registers 1038a09e64fbSRussell King * 1039a09e64fbSRussell King * Registers 1040a09e64fbSRussell King * TUCR Test Unit Control Register (read/write). 1041a09e64fbSRussell King */ 1042a09e64fbSRussell King 1043a09e64fbSRussell King #define TUCR __REG(0x90030008) /* Test Unit Control Reg. */ 1044a09e64fbSRussell King 1045a09e64fbSRussell King #define TUCR_TIC 0x00000040 /* TIC mode */ 1046a09e64fbSRussell King #define TUCR_TTST 0x00000080 /* Trim TeST mode */ 1047a09e64fbSRussell King #define TUCR_RCRC 0x00000100 /* Richard's Cyclic Redundancy */ 1048a09e64fbSRussell King /* Check */ 1049a09e64fbSRussell King #define TUCR_PMD 0x00000200 /* Power Management Disable */ 1050a09e64fbSRussell King #define TUCR_MR 0x00000400 /* Memory Request mode */ 1051a09e64fbSRussell King #define TUCR_NoMB (TUCR_MR*0) /* No Memory Bus request & grant */ 1052a09e64fbSRussell King #define TUCR_MBGPIO (TUCR_MR*1) /* Memory Bus request (MBREQ) & */ 1053a09e64fbSRussell King /* grant (MBGNT) on GPIO [22:21] */ 1054a09e64fbSRussell King #define TUCR_CTB Fld (3, 20) /* Clock Test Bits */ 1055a09e64fbSRussell King #define TUCR_FDC 0x00800000 /* RTC Force Delete Count */ 1056a09e64fbSRussell King #define TUCR_FMC 0x01000000 /* Force Michelle's Control mode */ 1057a09e64fbSRussell King #define TUCR_TMC 0x02000000 /* RTC Trimmer Multiplexer Control */ 1058a09e64fbSRussell King #define TUCR_DPS 0x04000000 /* Disallow Pad Sleep */ 1059a09e64fbSRussell King #define TUCR_TSEL Fld (3, 29) /* clock Test SELect on GPIO [27] */ 1060a09e64fbSRussell King #define TUCR_32_768kHz /* 32.768 kHz osc. on GPIO [27] */ \ 1061a09e64fbSRussell King (0 << FShft (TUCR_TSEL)) 1062a09e64fbSRussell King #define TUCR_3_6864MHz /* 3.6864 MHz osc. on GPIO [27] */ \ 1063a09e64fbSRussell King (1 << FShft (TUCR_TSEL)) 1064a09e64fbSRussell King #define TUCR_VDD /* VDD ring osc./16 on GPIO [27] */ \ 1065a09e64fbSRussell King (2 << FShft (TUCR_TSEL)) 1066a09e64fbSRussell King #define TUCR_96MHzPLL /* 96 MHz PLL/4 on GPIO [27] */ \ 1067a09e64fbSRussell King (3 << FShft (TUCR_TSEL)) 1068a09e64fbSRussell King #define TUCR_Clock /* internal (fcpu/2) & 32.768 kHz */ \ 1069a09e64fbSRussell King /* Clocks on GPIO [26:27] */ \ 1070a09e64fbSRussell King (4 << FShft (TUCR_TSEL)) 1071a09e64fbSRussell King #define TUCR_3_6864MHzA /* 3.6864 MHz osc. on GPIO [27] */ \ 1072a09e64fbSRussell King /* (Alternative) */ \ 1073a09e64fbSRussell King (5 << FShft (TUCR_TSEL)) 1074a09e64fbSRussell King #define TUCR_MainPLL /* Main PLL/16 on GPIO [27] */ \ 1075a09e64fbSRussell King (6 << FShft (TUCR_TSEL)) 1076a09e64fbSRussell King #define TUCR_VDDL /* VDDL ring osc./4 on GPIO [27] */ \ 1077a09e64fbSRussell King (7 << FShft (TUCR_TSEL)) 1078a09e64fbSRussell King 1079a09e64fbSRussell King 1080a09e64fbSRussell King /* 1081a09e64fbSRussell King * General-Purpose Input/Output (GPIO) control registers 1082a09e64fbSRussell King * 1083a09e64fbSRussell King * Registers 1084a09e64fbSRussell King * GPLR General-Purpose Input/Output (GPIO) Pin Level 1085a09e64fbSRussell King * Register (read). 1086a09e64fbSRussell King * GPDR General-Purpose Input/Output (GPIO) Pin Direction 1087a09e64fbSRussell King * Register (read/write). 1088a09e64fbSRussell King * GPSR General-Purpose Input/Output (GPIO) Pin output Set 1089a09e64fbSRussell King * Register (write). 1090a09e64fbSRussell King * GPCR General-Purpose Input/Output (GPIO) Pin output Clear 1091a09e64fbSRussell King * Register (write). 1092a09e64fbSRussell King * GRER General-Purpose Input/Output (GPIO) Rising-Edge 1093a09e64fbSRussell King * detect Register (read/write). 1094a09e64fbSRussell King * GFER General-Purpose Input/Output (GPIO) Falling-Edge 1095a09e64fbSRussell King * detect Register (read/write). 1096a09e64fbSRussell King * GEDR General-Purpose Input/Output (GPIO) Edge Detect 1097a09e64fbSRussell King * status Register (read/write). 1098a09e64fbSRussell King * GAFR General-Purpose Input/Output (GPIO) Alternate 1099a09e64fbSRussell King * Function Register (read/write). 1100a09e64fbSRussell King * 1101a09e64fbSRussell King * Clock 1102a09e64fbSRussell King * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). 1103a09e64fbSRussell King */ 1104a09e64fbSRussell King 1105a09e64fbSRussell King #define GPLR __REG(0x90040000) /* GPIO Pin Level Reg. */ 1106a09e64fbSRussell King #define GPDR __REG(0x90040004) /* GPIO Pin Direction Reg. */ 1107a09e64fbSRussell King #define GPSR __REG(0x90040008) /* GPIO Pin output Set Reg. */ 1108a09e64fbSRussell King #define GPCR __REG(0x9004000C) /* GPIO Pin output Clear Reg. */ 1109a09e64fbSRussell King #define GRER __REG(0x90040010) /* GPIO Rising-Edge detect Reg. */ 1110a09e64fbSRussell King #define GFER __REG(0x90040014) /* GPIO Falling-Edge detect Reg. */ 1111a09e64fbSRussell King #define GEDR __REG(0x90040018) /* GPIO Edge Detect status Reg. */ 1112a09e64fbSRussell King #define GAFR __REG(0x9004001C) /* GPIO Alternate Function Reg. */ 1113a09e64fbSRussell King 1114a09e64fbSRussell King #define GPIO_MIN (0) 1115a09e64fbSRussell King #define GPIO_MAX (27) 1116a09e64fbSRussell King 1117a09e64fbSRussell King #define GPIO_GPIO(Nb) /* GPIO [0..27] */ \ 1118a09e64fbSRussell King (0x00000001 << (Nb)) 1119a09e64fbSRussell King #define GPIO_GPIO0 GPIO_GPIO (0) /* GPIO [0] */ 1120a09e64fbSRussell King #define GPIO_GPIO1 GPIO_GPIO (1) /* GPIO [1] */ 1121a09e64fbSRussell King #define GPIO_GPIO2 GPIO_GPIO (2) /* GPIO [2] */ 1122a09e64fbSRussell King #define GPIO_GPIO3 GPIO_GPIO (3) /* GPIO [3] */ 1123a09e64fbSRussell King #define GPIO_GPIO4 GPIO_GPIO (4) /* GPIO [4] */ 1124a09e64fbSRussell King #define GPIO_GPIO5 GPIO_GPIO (5) /* GPIO [5] */ 1125a09e64fbSRussell King #define GPIO_GPIO6 GPIO_GPIO (6) /* GPIO [6] */ 1126a09e64fbSRussell King #define GPIO_GPIO7 GPIO_GPIO (7) /* GPIO [7] */ 1127a09e64fbSRussell King #define GPIO_GPIO8 GPIO_GPIO (8) /* GPIO [8] */ 1128a09e64fbSRussell King #define GPIO_GPIO9 GPIO_GPIO (9) /* GPIO [9] */ 1129a09e64fbSRussell King #define GPIO_GPIO10 GPIO_GPIO (10) /* GPIO [10] */ 1130a09e64fbSRussell King #define GPIO_GPIO11 GPIO_GPIO (11) /* GPIO [11] */ 1131a09e64fbSRussell King #define GPIO_GPIO12 GPIO_GPIO (12) /* GPIO [12] */ 1132a09e64fbSRussell King #define GPIO_GPIO13 GPIO_GPIO (13) /* GPIO [13] */ 1133a09e64fbSRussell King #define GPIO_GPIO14 GPIO_GPIO (14) /* GPIO [14] */ 1134a09e64fbSRussell King #define GPIO_GPIO15 GPIO_GPIO (15) /* GPIO [15] */ 1135a09e64fbSRussell King #define GPIO_GPIO16 GPIO_GPIO (16) /* GPIO [16] */ 1136a09e64fbSRussell King #define GPIO_GPIO17 GPIO_GPIO (17) /* GPIO [17] */ 1137a09e64fbSRussell King #define GPIO_GPIO18 GPIO_GPIO (18) /* GPIO [18] */ 1138a09e64fbSRussell King #define GPIO_GPIO19 GPIO_GPIO (19) /* GPIO [19] */ 1139a09e64fbSRussell King #define GPIO_GPIO20 GPIO_GPIO (20) /* GPIO [20] */ 1140a09e64fbSRussell King #define GPIO_GPIO21 GPIO_GPIO (21) /* GPIO [21] */ 1141a09e64fbSRussell King #define GPIO_GPIO22 GPIO_GPIO (22) /* GPIO [22] */ 1142a09e64fbSRussell King #define GPIO_GPIO23 GPIO_GPIO (23) /* GPIO [23] */ 1143a09e64fbSRussell King #define GPIO_GPIO24 GPIO_GPIO (24) /* GPIO [24] */ 1144a09e64fbSRussell King #define GPIO_GPIO25 GPIO_GPIO (25) /* GPIO [25] */ 1145a09e64fbSRussell King #define GPIO_GPIO26 GPIO_GPIO (26) /* GPIO [26] */ 1146a09e64fbSRussell King #define GPIO_GPIO27 GPIO_GPIO (27) /* GPIO [27] */ 1147a09e64fbSRussell King 1148a09e64fbSRussell King #define GPIO_LDD(Nb) /* LCD Data [8..15] (O) */ \ 1149a09e64fbSRussell King GPIO_GPIO ((Nb) - 6) 1150a09e64fbSRussell King #define GPIO_LDD8 GPIO_LDD (8) /* LCD Data [8] (O) */ 1151a09e64fbSRussell King #define GPIO_LDD9 GPIO_LDD (9) /* LCD Data [9] (O) */ 1152a09e64fbSRussell King #define GPIO_LDD10 GPIO_LDD (10) /* LCD Data [10] (O) */ 1153a09e64fbSRussell King #define GPIO_LDD11 GPIO_LDD (11) /* LCD Data [11] (O) */ 1154a09e64fbSRussell King #define GPIO_LDD12 GPIO_LDD (12) /* LCD Data [12] (O) */ 1155a09e64fbSRussell King #define GPIO_LDD13 GPIO_LDD (13) /* LCD Data [13] (O) */ 1156a09e64fbSRussell King #define GPIO_LDD14 GPIO_LDD (14) /* LCD Data [14] (O) */ 1157a09e64fbSRussell King #define GPIO_LDD15 GPIO_LDD (15) /* LCD Data [15] (O) */ 1158a09e64fbSRussell King /* ser. port 4: */ 1159a09e64fbSRussell King #define GPIO_SSP_TXD GPIO_GPIO (10) /* SSP Transmit Data (O) */ 1160a09e64fbSRussell King #define GPIO_SSP_RXD GPIO_GPIO (11) /* SSP Receive Data (I) */ 1161a09e64fbSRussell King #define GPIO_SSP_SCLK GPIO_GPIO (12) /* SSP Sample CLocK (O) */ 1162a09e64fbSRussell King #define GPIO_SSP_SFRM GPIO_GPIO (13) /* SSP Sample FRaMe (O) */ 1163a09e64fbSRussell King /* ser. port 1: */ 1164a09e64fbSRussell King #define GPIO_UART_TXD GPIO_GPIO (14) /* UART Transmit Data (O) */ 1165a09e64fbSRussell King #define GPIO_UART_RXD GPIO_GPIO (15) /* UART Receive Data (I) */ 1166a09e64fbSRussell King #define GPIO_SDLC_SCLK GPIO_GPIO (16) /* SDLC Sample CLocK (I/O) */ 1167a09e64fbSRussell King #define GPIO_SDLC_AAF GPIO_GPIO (17) /* SDLC Abort After Frame (O) */ 1168a09e64fbSRussell King #define GPIO_UART_SCLK1 GPIO_GPIO (18) /* UART Sample CLocK 1 (I) */ 1169a09e64fbSRussell King /* ser. port 4: */ 1170a09e64fbSRussell King #define GPIO_SSP_CLK GPIO_GPIO (19) /* SSP external CLocK (I) */ 1171a09e64fbSRussell King /* ser. port 3: */ 1172a09e64fbSRussell King #define GPIO_UART_SCLK3 GPIO_GPIO (20) /* UART Sample CLocK 3 (I) */ 1173a09e64fbSRussell King /* ser. port 4: */ 1174a09e64fbSRussell King #define GPIO_MCP_CLK GPIO_GPIO (21) /* MCP CLocK (I) */ 1175a09e64fbSRussell King /* test controller: */ 1176a09e64fbSRussell King #define GPIO_TIC_ACK GPIO_GPIO (21) /* TIC ACKnowledge (O) */ 1177a09e64fbSRussell King #define GPIO_MBGNT GPIO_GPIO (21) /* Memory Bus GraNT (O) */ 1178a09e64fbSRussell King #define GPIO_TREQA GPIO_GPIO (22) /* TIC REQuest A (I) */ 1179a09e64fbSRussell King #define GPIO_MBREQ GPIO_GPIO (22) /* Memory Bus REQuest (I) */ 1180a09e64fbSRussell King #define GPIO_TREQB GPIO_GPIO (23) /* TIC REQuest B (I) */ 1181a09e64fbSRussell King #define GPIO_1Hz GPIO_GPIO (25) /* 1 Hz clock (O) */ 1182a09e64fbSRussell King #define GPIO_RCLK GPIO_GPIO (26) /* internal (R) CLocK (O, fcpu/2) */ 1183a09e64fbSRussell King #define GPIO_32_768kHz GPIO_GPIO (27) /* 32.768 kHz clock (O, RTC) */ 1184a09e64fbSRussell King 1185a09e64fbSRussell King #define GPDR_In 0 /* Input */ 1186a09e64fbSRussell King #define GPDR_Out 1 /* Output */ 1187a09e64fbSRussell King 1188a09e64fbSRussell King 1189a09e64fbSRussell King /* 1190a09e64fbSRussell King * Interrupt Controller (IC) control registers 1191a09e64fbSRussell King * 1192a09e64fbSRussell King * Registers 1193a09e64fbSRussell King * ICIP Interrupt Controller (IC) Interrupt ReQuest (IRQ) 1194a09e64fbSRussell King * Pending register (read). 1195a09e64fbSRussell King * ICMR Interrupt Controller (IC) Mask Register (read/write). 1196a09e64fbSRussell King * ICLR Interrupt Controller (IC) Level Register (read/write). 1197a09e64fbSRussell King * ICCR Interrupt Controller (IC) Control Register 1198a09e64fbSRussell King * (read/write). 1199a09e64fbSRussell King * [The ICCR register is only implemented in versions 2.0 1200a09e64fbSRussell King * (rev. = 8) and higher of the StrongARM SA-1100.] 1201a09e64fbSRussell King * ICFP Interrupt Controller (IC) Fast Interrupt reQuest 1202a09e64fbSRussell King * (FIQ) Pending register (read). 1203a09e64fbSRussell King * ICPR Interrupt Controller (IC) Pending Register (read). 1204a09e64fbSRussell King * [The ICPR register is active low (inverted) in 1205a09e64fbSRussell King * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the 1206a09e64fbSRussell King * StrongARM SA-1100, it is active high (non-inverted) in 1207a09e64fbSRussell King * versions 2.0 (rev. = 8) and higher.] 1208a09e64fbSRussell King */ 1209a09e64fbSRussell King 1210a09e64fbSRussell King #define ICIP __REG(0x90050000) /* IC IRQ Pending reg. */ 1211a09e64fbSRussell King #define ICMR __REG(0x90050004) /* IC Mask Reg. */ 1212a09e64fbSRussell King #define ICLR __REG(0x90050008) /* IC Level Reg. */ 1213a09e64fbSRussell King #define ICCR __REG(0x9005000C) /* IC Control Reg. */ 1214a09e64fbSRussell King #define ICFP __REG(0x90050010) /* IC FIQ Pending reg. */ 1215a09e64fbSRussell King #define ICPR __REG(0x90050020) /* IC Pending Reg. */ 1216a09e64fbSRussell King 1217a09e64fbSRussell King #define IC_GPIO(Nb) /* GPIO [0..10] */ \ 1218a09e64fbSRussell King (0x00000001 << (Nb)) 1219a09e64fbSRussell King #define IC_GPIO0 IC_GPIO (0) /* GPIO [0] */ 1220a09e64fbSRussell King #define IC_GPIO1 IC_GPIO (1) /* GPIO [1] */ 1221a09e64fbSRussell King #define IC_GPIO2 IC_GPIO (2) /* GPIO [2] */ 1222a09e64fbSRussell King #define IC_GPIO3 IC_GPIO (3) /* GPIO [3] */ 1223a09e64fbSRussell King #define IC_GPIO4 IC_GPIO (4) /* GPIO [4] */ 1224a09e64fbSRussell King #define IC_GPIO5 IC_GPIO (5) /* GPIO [5] */ 1225a09e64fbSRussell King #define IC_GPIO6 IC_GPIO (6) /* GPIO [6] */ 1226a09e64fbSRussell King #define IC_GPIO7 IC_GPIO (7) /* GPIO [7] */ 1227a09e64fbSRussell King #define IC_GPIO8 IC_GPIO (8) /* GPIO [8] */ 1228a09e64fbSRussell King #define IC_GPIO9 IC_GPIO (9) /* GPIO [9] */ 1229a09e64fbSRussell King #define IC_GPIO10 IC_GPIO (10) /* GPIO [10] */ 1230a09e64fbSRussell King #define IC_GPIO11_27 0x00000800 /* GPIO [11:27] (ORed) */ 1231a09e64fbSRussell King #define IC_LCD 0x00001000 /* LCD controller */ 1232a09e64fbSRussell King #define IC_Ser0UDC 0x00002000 /* Ser. port 0 UDC */ 1233a09e64fbSRussell King #define IC_Ser1SDLC 0x00004000 /* Ser. port 1 SDLC */ 1234a09e64fbSRussell King #define IC_Ser1UART 0x00008000 /* Ser. port 1 UART */ 1235a09e64fbSRussell King #define IC_Ser2ICP 0x00010000 /* Ser. port 2 ICP */ 1236a09e64fbSRussell King #define IC_Ser3UART 0x00020000 /* Ser. port 3 UART */ 1237a09e64fbSRussell King #define IC_Ser4MCP 0x00040000 /* Ser. port 4 MCP */ 1238a09e64fbSRussell King #define IC_Ser4SSP 0x00080000 /* Ser. port 4 SSP */ 1239a09e64fbSRussell King #define IC_DMA(Nb) /* DMA controller channel [0..5] */ \ 1240a09e64fbSRussell King (0x00100000 << (Nb)) 1241a09e64fbSRussell King #define IC_DMA0 IC_DMA (0) /* DMA controller channel 0 */ 1242a09e64fbSRussell King #define IC_DMA1 IC_DMA (1) /* DMA controller channel 1 */ 1243a09e64fbSRussell King #define IC_DMA2 IC_DMA (2) /* DMA controller channel 2 */ 1244a09e64fbSRussell King #define IC_DMA3 IC_DMA (3) /* DMA controller channel 3 */ 1245a09e64fbSRussell King #define IC_DMA4 IC_DMA (4) /* DMA controller channel 4 */ 1246a09e64fbSRussell King #define IC_DMA5 IC_DMA (5) /* DMA controller channel 5 */ 1247a09e64fbSRussell King #define IC_OST(Nb) /* OS Timer match [0..3] */ \ 1248a09e64fbSRussell King (0x04000000 << (Nb)) 1249a09e64fbSRussell King #define IC_OST0 IC_OST (0) /* OS Timer match 0 */ 1250a09e64fbSRussell King #define IC_OST1 IC_OST (1) /* OS Timer match 1 */ 1251a09e64fbSRussell King #define IC_OST2 IC_OST (2) /* OS Timer match 2 */ 1252a09e64fbSRussell King #define IC_OST3 IC_OST (3) /* OS Timer match 3 */ 1253a09e64fbSRussell King #define IC_RTC1Hz 0x40000000 /* RTC 1 Hz clock */ 1254a09e64fbSRussell King #define IC_RTCAlrm 0x80000000 /* RTC Alarm */ 1255a09e64fbSRussell King 1256a09e64fbSRussell King #define ICLR_IRQ 0 /* Interrupt ReQuest */ 1257a09e64fbSRussell King #define ICLR_FIQ 1 /* Fast Interrupt reQuest */ 1258a09e64fbSRussell King 1259a09e64fbSRussell King #define ICCR_DIM 0x00000001 /* Disable Idle-mode interrupt */ 1260a09e64fbSRussell King /* Mask */ 1261a09e64fbSRussell King #define ICCR_IdleAllInt (ICCR_DIM*0) /* Idle-mode All Interrupt enable */ 1262a09e64fbSRussell King /* (ICMR ignored) */ 1263a09e64fbSRussell King #define ICCR_IdleMskInt (ICCR_DIM*1) /* Idle-mode non-Masked Interrupt */ 1264a09e64fbSRussell King /* enable (ICMR used) */ 1265a09e64fbSRussell King 1266a09e64fbSRussell King 1267a09e64fbSRussell King /* 1268a09e64fbSRussell King * Peripheral Pin Controller (PPC) control registers 1269a09e64fbSRussell King * 1270a09e64fbSRussell King * Registers 1271a09e64fbSRussell King * PPDR Peripheral Pin Controller (PPC) Pin Direction 1272a09e64fbSRussell King * Register (read/write). 1273a09e64fbSRussell King * PPSR Peripheral Pin Controller (PPC) Pin State Register 1274a09e64fbSRussell King * (read/write). 1275a09e64fbSRussell King * PPAR Peripheral Pin Controller (PPC) Pin Assignment 1276a09e64fbSRussell King * Register (read/write). 1277a09e64fbSRussell King * PSDR Peripheral Pin Controller (PPC) Sleep-mode pin 1278a09e64fbSRussell King * Direction Register (read/write). 1279a09e64fbSRussell King * PPFR Peripheral Pin Controller (PPC) Pin Flag Register 1280a09e64fbSRussell King * (read). 1281a09e64fbSRussell King */ 1282a09e64fbSRussell King 1283a09e64fbSRussell King #define PPDR __REG(0x90060000) /* PPC Pin Direction Reg. */ 1284a09e64fbSRussell King #define PPSR __REG(0x90060004) /* PPC Pin State Reg. */ 1285a09e64fbSRussell King #define PPAR __REG(0x90060008) /* PPC Pin Assignment Reg. */ 1286a09e64fbSRussell King #define PSDR __REG(0x9006000C) /* PPC Sleep-mode pin Direction Reg. */ 1287a09e64fbSRussell King #define PPFR __REG(0x90060010) /* PPC Pin Flag Reg. */ 1288a09e64fbSRussell King 1289a09e64fbSRussell King #define PPC_LDD(Nb) /* LCD Data [0..7] */ \ 1290a09e64fbSRussell King (0x00000001 << (Nb)) 1291a09e64fbSRussell King #define PPC_LDD0 PPC_LDD (0) /* LCD Data [0] */ 1292a09e64fbSRussell King #define PPC_LDD1 PPC_LDD (1) /* LCD Data [1] */ 1293a09e64fbSRussell King #define PPC_LDD2 PPC_LDD (2) /* LCD Data [2] */ 1294a09e64fbSRussell King #define PPC_LDD3 PPC_LDD (3) /* LCD Data [3] */ 1295a09e64fbSRussell King #define PPC_LDD4 PPC_LDD (4) /* LCD Data [4] */ 1296a09e64fbSRussell King #define PPC_LDD5 PPC_LDD (5) /* LCD Data [5] */ 1297a09e64fbSRussell King #define PPC_LDD6 PPC_LDD (6) /* LCD Data [6] */ 1298a09e64fbSRussell King #define PPC_LDD7 PPC_LDD (7) /* LCD Data [7] */ 1299a09e64fbSRussell King #define PPC_L_PCLK 0x00000100 /* LCD Pixel CLocK */ 1300a09e64fbSRussell King #define PPC_L_LCLK 0x00000200 /* LCD Line CLocK */ 1301a09e64fbSRussell King #define PPC_L_FCLK 0x00000400 /* LCD Frame CLocK */ 1302a09e64fbSRussell King #define PPC_L_BIAS 0x00000800 /* LCD AC BIAS */ 1303a09e64fbSRussell King /* ser. port 1: */ 1304a09e64fbSRussell King #define PPC_TXD1 0x00001000 /* SDLC/UART Transmit Data 1 */ 1305a09e64fbSRussell King #define PPC_RXD1 0x00002000 /* SDLC/UART Receive Data 1 */ 1306a09e64fbSRussell King /* ser. port 2: */ 1307a09e64fbSRussell King #define PPC_TXD2 0x00004000 /* IPC Transmit Data 2 */ 1308a09e64fbSRussell King #define PPC_RXD2 0x00008000 /* IPC Receive Data 2 */ 1309a09e64fbSRussell King /* ser. port 3: */ 1310a09e64fbSRussell King #define PPC_TXD3 0x00010000 /* UART Transmit Data 3 */ 1311a09e64fbSRussell King #define PPC_RXD3 0x00020000 /* UART Receive Data 3 */ 1312a09e64fbSRussell King /* ser. port 4: */ 1313a09e64fbSRussell King #define PPC_TXD4 0x00040000 /* MCP/SSP Transmit Data 4 */ 1314a09e64fbSRussell King #define PPC_RXD4 0x00080000 /* MCP/SSP Receive Data 4 */ 1315a09e64fbSRussell King #define PPC_SCLK 0x00100000 /* MCP/SSP Sample CLocK */ 1316a09e64fbSRussell King #define PPC_SFRM 0x00200000 /* MCP/SSP Sample FRaMe */ 1317a09e64fbSRussell King 1318a09e64fbSRussell King #define PPDR_In 0 /* Input */ 1319a09e64fbSRussell King #define PPDR_Out 1 /* Output */ 1320a09e64fbSRussell King 1321a09e64fbSRussell King /* ser. port 1: */ 1322a09e64fbSRussell King #define PPAR_UPR 0x00001000 /* UART Pin Reassignment */ 1323a09e64fbSRussell King #define PPAR_UARTTR (PPAR_UPR*0) /* UART on TXD_1 & RXD_1 */ 1324a09e64fbSRussell King #define PPAR_UARTGPIO (PPAR_UPR*1) /* UART on GPIO [14:15] */ 1325a09e64fbSRussell King /* ser. port 4: */ 1326a09e64fbSRussell King #define PPAR_SPR 0x00040000 /* SSP Pin Reassignment */ 1327a09e64fbSRussell King #define PPAR_SSPTRSS (PPAR_SPR*0) /* SSP on TXD_C, RXD_C, SCLK_C, */ 1328a09e64fbSRussell King /* & SFRM_C */ 1329a09e64fbSRussell King #define PPAR_SSPGPIO (PPAR_SPR*1) /* SSP on GPIO [10:13] */ 1330a09e64fbSRussell King 1331a09e64fbSRussell King #define PSDR_OutL 0 /* Output Low in sleep mode */ 1332a09e64fbSRussell King #define PSDR_Flt 1 /* Floating (input) in sleep mode */ 1333a09e64fbSRussell King 1334a09e64fbSRussell King #define PPFR_LCD 0x00000001 /* LCD controller */ 1335a09e64fbSRussell King #define PPFR_SP1TX 0x00001000 /* Ser. Port 1 SDLC/UART Transmit */ 1336a09e64fbSRussell King #define PPFR_SP1RX 0x00002000 /* Ser. Port 1 SDLC/UART Receive */ 1337a09e64fbSRussell King #define PPFR_SP2TX 0x00004000 /* Ser. Port 2 ICP Transmit */ 1338a09e64fbSRussell King #define PPFR_SP2RX 0x00008000 /* Ser. Port 2 ICP Receive */ 1339a09e64fbSRussell King #define PPFR_SP3TX 0x00010000 /* Ser. Port 3 UART Transmit */ 1340a09e64fbSRussell King #define PPFR_SP3RX 0x00020000 /* Ser. Port 3 UART Receive */ 1341a09e64fbSRussell King #define PPFR_SP4 0x00040000 /* Ser. Port 4 MCP/SSP */ 1342a09e64fbSRussell King #define PPFR_PerEn 0 /* Peripheral Enabled */ 1343a09e64fbSRussell King #define PPFR_PPCEn 1 /* PPC Enabled */ 1344a09e64fbSRussell King 1345a09e64fbSRussell King 1346a09e64fbSRussell King /* 1347a09e64fbSRussell King * Dynamic Random-Access Memory (DRAM) control registers 1348a09e64fbSRussell King * 1349a09e64fbSRussell King * Registers 1350a09e64fbSRussell King * MDCNFG Memory system: Dynamic Random-Access Memory (DRAM) 1351a09e64fbSRussell King * CoNFiGuration register (read/write). 1352a09e64fbSRussell King * MDCAS0 Memory system: Dynamic Random-Access Memory (DRAM) 1353a09e64fbSRussell King * Column Address Strobe (CAS) shift register 0 1354a09e64fbSRussell King * (read/write). 1355a09e64fbSRussell King * MDCAS1 Memory system: Dynamic Random-Access Memory (DRAM) 1356a09e64fbSRussell King * Column Address Strobe (CAS) shift register 1 1357a09e64fbSRussell King * (read/write). 1358a09e64fbSRussell King * MDCAS2 Memory system: Dynamic Random-Access Memory (DRAM) 1359a09e64fbSRussell King * Column Address Strobe (CAS) shift register 2 1360a09e64fbSRussell King * (read/write). 1361a09e64fbSRussell King * 1362a09e64fbSRussell King * Clocks 1363a09e64fbSRussell King * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). 1364a09e64fbSRussell King * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2). 1365a09e64fbSRussell King * fcas, Tcas Frequency, period of the DRAM CAS shift registers. 1366a09e64fbSRussell King */ 1367a09e64fbSRussell King 1368a09e64fbSRussell King #define MDCNFG __REG(0xA0000000) /* DRAM CoNFiGuration reg. */ 1369a09e64fbSRussell King #define MDCAS0 __REG(0xA0000004) /* DRAM CAS shift reg. 0 */ 1370a09e64fbSRussell King #define MDCAS1 __REG(0xA0000008) /* DRAM CAS shift reg. 1 */ 1371a09e64fbSRussell King #define MDCAS2 __REG(0xA000000c) /* DRAM CAS shift reg. 2 */ 1372a09e64fbSRussell King 1373a09e64fbSRussell King /* SA1100 MDCNFG values */ 1374a09e64fbSRussell King #define MDCNFG_DE(Nb) /* DRAM Enable bank [0..3] */ \ 1375a09e64fbSRussell King (0x00000001 << (Nb)) 1376a09e64fbSRussell King #define MDCNFG_DE0 MDCNFG_DE (0) /* DRAM Enable bank 0 */ 1377a09e64fbSRussell King #define MDCNFG_DE1 MDCNFG_DE (1) /* DRAM Enable bank 1 */ 1378a09e64fbSRussell King #define MDCNFG_DE2 MDCNFG_DE (2) /* DRAM Enable bank 2 */ 1379a09e64fbSRussell King #define MDCNFG_DE3 MDCNFG_DE (3) /* DRAM Enable bank 3 */ 1380a09e64fbSRussell King #define MDCNFG_DRAC Fld (2, 4) /* DRAM Row Address Count - 9 */ 1381a09e64fbSRussell King #define MDCNFG_RowAdd(Add) /* Row Address count [9..12] */ \ 1382a09e64fbSRussell King (((Add) - 9) << FShft (MDCNFG_DRAC)) 1383a09e64fbSRussell King #define MDCNFG_CDB2 0x00000040 /* shift reg. Clock Divide By 2 */ 1384a09e64fbSRussell King /* (fcas = fcpu/2) */ 1385a09e64fbSRussell King #define MDCNFG_TRP Fld (4, 7) /* Time RAS Pre-charge - 1 [Tmem] */ 1386a09e64fbSRussell King #define MDCNFG_PrChrg(Tcpu) /* Pre-Charge time [2..32 Tcpu] */ \ 1387a09e64fbSRussell King (((Tcpu) - 2)/2 << FShft (MDCNFG_TRP)) 1388a09e64fbSRussell King #define MDCNFG_CeilPrChrg(Tcpu) /* Ceil. of PrChrg [2..32 Tcpu] */ \ 1389a09e64fbSRussell King (((Tcpu) - 1)/2 << FShft (MDCNFG_TRP)) 1390a09e64fbSRussell King #define MDCNFG_TRASR Fld (4, 11) /* Time RAS Refresh - 1 [Tmem] */ 1391a09e64fbSRussell King #define MDCNFG_Ref(Tcpu) /* Refresh time [2..32 Tcpu] */ \ 1392a09e64fbSRussell King (((Tcpu) - 2)/2 << FShft (MDCNFG_TRASR)) 1393a09e64fbSRussell King #define MDCNFG_CeilRef(Tcpu) /* Ceil. of Ref [2..32 Tcpu] */ \ 1394a09e64fbSRussell King (((Tcpu) - 1)/2 << FShft (MDCNFG_TRASR)) 1395a09e64fbSRussell King #define MDCNFG_TDL Fld (2, 15) /* Time Data Latch [Tcpu] */ 1396a09e64fbSRussell King #define MDCNFG_DataLtch(Tcpu) /* Data Latch delay [0..3 Tcpu] */ \ 1397a09e64fbSRussell King ((Tcpu) << FShft (MDCNFG_TDL)) 1398a09e64fbSRussell King #define MDCNFG_DRI Fld (15, 17) /* min. DRAM Refresh Interval/4 */ 1399a09e64fbSRussell King /* [Tmem] */ 1400a09e64fbSRussell King #define MDCNFG_RefInt(Tcpu) /* min. Refresh Interval */ \ 1401a09e64fbSRussell King /* [0..262136 Tcpu] */ \ 1402a09e64fbSRussell King ((Tcpu)/8 << FShft (MDCNFG_DRI)) 1403a09e64fbSRussell King 1404a09e64fbSRussell King /* SA1110 MDCNFG values */ 1405a09e64fbSRussell King #define MDCNFG_SA1110_DE0 0x00000001 /* DRAM Enable bank 0 */ 1406a09e64fbSRussell King #define MDCNFG_SA1110_DE1 0x00000002 /* DRAM Enable bank 1 */ 1407a09e64fbSRussell King #define MDCNFG_SA1110_DTIM0 0x00000004 /* DRAM timing type 0/1 */ 1408a09e64fbSRussell King #define MDCNFG_SA1110_DWID0 0x00000008 /* DRAM bus width 0/1 */ 1409a09e64fbSRussell King #define MDCNFG_SA1110_DRAC0 Fld(3, 4) /* DRAM row addr bit count */ 1410a09e64fbSRussell King /* bank 0/1 */ 1411a09e64fbSRussell King #define MDCNFG_SA1110_CDB20 0x00000080 /* Mem Clock divide by 2 0/1 */ 1412a09e64fbSRussell King #define MDCNFG_SA1110_TRP0 Fld(3, 8) /* RAS precharge 0/1 */ 1413a09e64fbSRussell King #define MDCNFG_SA1110_TDL0 Fld(2, 12) /* Data input latch after CAS*/ 1414a09e64fbSRussell King /* deassertion 0/1 */ 1415a09e64fbSRussell King #define MDCNFG_SA1110_TWR0 Fld(2, 14) /* SDRAM write recovery 0/1 */ 1416a09e64fbSRussell King #define MDCNFG_SA1110_DE2 0x00010000 /* DRAM Enable bank 0 */ 1417a09e64fbSRussell King #define MDCNFG_SA1110_DE3 0x00020000 /* DRAM Enable bank 1 */ 1418a09e64fbSRussell King #define MDCNFG_SA1110_DTIM2 0x00040000 /* DRAM timing type 0/1 */ 1419a09e64fbSRussell King #define MDCNFG_SA1110_DWID2 0x00080000 /* DRAM bus width 0/1 */ 1420a09e64fbSRussell King #define MDCNFG_SA1110_DRAC2 Fld(3, 20) /* DRAM row addr bit count */ 1421a09e64fbSRussell King /* bank 0/1 */ 1422a09e64fbSRussell King #define MDCNFG_SA1110_CDB22 0x00800000 /* Mem Clock divide by 2 0/1 */ 1423a09e64fbSRussell King #define MDCNFG_SA1110_TRP2 Fld(3, 24) /* RAS precharge 0/1 */ 1424a09e64fbSRussell King #define MDCNFG_SA1110_TDL2 Fld(2, 28) /* Data input latch after CAS*/ 1425a09e64fbSRussell King /* deassertion 0/1 */ 1426a09e64fbSRussell King #define MDCNFG_SA1110_TWR2 Fld(2, 30) /* SDRAM write recovery 0/1 */ 1427a09e64fbSRussell King 1428a09e64fbSRussell King 1429a09e64fbSRussell King /* 1430a09e64fbSRussell King * Static memory control registers 1431a09e64fbSRussell King * 1432a09e64fbSRussell King * Registers 1433a09e64fbSRussell King * MSC0 Memory system: Static memory Control register 0 1434a09e64fbSRussell King * (read/write). 1435a09e64fbSRussell King * MSC1 Memory system: Static memory Control register 1 1436a09e64fbSRussell King * (read/write). 1437a09e64fbSRussell King * 1438a09e64fbSRussell King * Clocks 1439a09e64fbSRussell King * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). 1440a09e64fbSRussell King * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2). 1441a09e64fbSRussell King */ 1442a09e64fbSRussell King 1443a09e64fbSRussell King #define MSC0 __REG(0xa0000010) /* Static memory Control reg. 0 */ 1444a09e64fbSRussell King #define MSC1 __REG(0xa0000014) /* Static memory Control reg. 1 */ 1445a09e64fbSRussell King #define MSC2 __REG(0xa000002c) /* Static memory Control reg. 2, not contiguous */ 1446a09e64fbSRussell King 1447a09e64fbSRussell King #define MSC_Bnk(Nb) /* static memory Bank [0..3] */ \ 1448a09e64fbSRussell King Fld (16, ((Nb) Modulo 2)*16) 1449a09e64fbSRussell King #define MSC0_Bnk0 MSC_Bnk (0) /* static memory Bank 0 */ 1450a09e64fbSRussell King #define MSC0_Bnk1 MSC_Bnk (1) /* static memory Bank 1 */ 1451a09e64fbSRussell King #define MSC1_Bnk2 MSC_Bnk (2) /* static memory Bank 2 */ 1452a09e64fbSRussell King #define MSC1_Bnk3 MSC_Bnk (3) /* static memory Bank 3 */ 1453a09e64fbSRussell King 1454a09e64fbSRussell King #define MSC_RT Fld (2, 0) /* ROM/static memory Type */ 1455a09e64fbSRussell King #define MSC_NonBrst /* Non-Burst static memory */ \ 1456a09e64fbSRussell King (0 << FShft (MSC_RT)) 1457a09e64fbSRussell King #define MSC_SRAM /* 32-bit byte-writable SRAM */ \ 1458a09e64fbSRussell King (1 << FShft (MSC_RT)) 1459a09e64fbSRussell King #define MSC_Brst4 /* Burst-of-4 static memory */ \ 1460a09e64fbSRussell King (2 << FShft (MSC_RT)) 1461a09e64fbSRussell King #define MSC_Brst8 /* Burst-of-8 static memory */ \ 1462a09e64fbSRussell King (3 << FShft (MSC_RT)) 1463a09e64fbSRussell King #define MSC_RBW 0x0004 /* ROM/static memory Bus Width */ 1464a09e64fbSRussell King #define MSC_32BitStMem (MSC_RBW*0) /* 32-Bit Static Memory */ 1465a09e64fbSRussell King #define MSC_16BitStMem (MSC_RBW*1) /* 16-Bit Static Memory */ 1466a09e64fbSRussell King #define MSC_RDF Fld (5, 3) /* ROM/static memory read Delay */ 1467a09e64fbSRussell King /* First access - 1(.5) [Tmem] */ 1468a09e64fbSRussell King #define MSC_1stRdAcc(Tcpu) /* 1st Read Access time (burst */ \ 1469a09e64fbSRussell King /* static memory) [3..65 Tcpu] */ \ 1470a09e64fbSRussell King ((((Tcpu) - 3)/2) << FShft (MSC_RDF)) 1471a09e64fbSRussell King #define MSC_Ceil1stRdAcc(Tcpu) /* Ceil. of 1stRdAcc [3..65 Tcpu] */ \ 1472a09e64fbSRussell King ((((Tcpu) - 2)/2) << FShft (MSC_RDF)) 1473a09e64fbSRussell King #define MSC_RdAcc(Tcpu) /* Read Access time (non-burst */ \ 1474a09e64fbSRussell King /* static memory) [2..64 Tcpu] */ \ 1475a09e64fbSRussell King ((((Tcpu) - 2)/2) << FShft (MSC_RDF)) 1476a09e64fbSRussell King #define MSC_CeilRdAcc(Tcpu) /* Ceil. of RdAcc [2..64 Tcpu] */ \ 1477a09e64fbSRussell King ((((Tcpu) - 1)/2) << FShft (MSC_RDF)) 1478a09e64fbSRussell King #define MSC_RDN Fld (5, 8) /* ROM/static memory read Delay */ 1479a09e64fbSRussell King /* Next access - 1 [Tmem] */ 1480a09e64fbSRussell King #define MSC_NxtRdAcc(Tcpu) /* Next Read Access time (burst */ \ 1481a09e64fbSRussell King /* static memory) [2..64 Tcpu] */ \ 1482a09e64fbSRussell King ((((Tcpu) - 2)/2) << FShft (MSC_RDN)) 1483a09e64fbSRussell King #define MSC_CeilNxtRdAcc(Tcpu) /* Ceil. of NxtRdAcc [2..64 Tcpu] */ \ 1484a09e64fbSRussell King ((((Tcpu) - 1)/2) << FShft (MSC_RDN)) 1485a09e64fbSRussell King #define MSC_WrAcc(Tcpu) /* Write Access time (non-burst */ \ 1486a09e64fbSRussell King /* static memory) [2..64 Tcpu] */ \ 1487a09e64fbSRussell King ((((Tcpu) - 2)/2) << FShft (MSC_RDN)) 1488a09e64fbSRussell King #define MSC_CeilWrAcc(Tcpu) /* Ceil. of WrAcc [2..64 Tcpu] */ \ 1489a09e64fbSRussell King ((((Tcpu) - 1)/2) << FShft (MSC_RDN)) 1490a09e64fbSRussell King #define MSC_RRR Fld (3, 13) /* ROM/static memory RecoveRy */ 1491a09e64fbSRussell King /* time/2 [Tmem] */ 1492a09e64fbSRussell King #define MSC_Rec(Tcpu) /* Recovery time [0..28 Tcpu] */ \ 1493a09e64fbSRussell King (((Tcpu)/4) << FShft (MSC_RRR)) 1494a09e64fbSRussell King #define MSC_CeilRec(Tcpu) /* Ceil. of Rec [0..28 Tcpu] */ \ 1495a09e64fbSRussell King ((((Tcpu) + 3)/4) << FShft (MSC_RRR)) 1496a09e64fbSRussell King 1497a09e64fbSRussell King 1498a09e64fbSRussell King /* 1499a09e64fbSRussell King * Personal Computer Memory Card International Association (PCMCIA) control 1500a09e64fbSRussell King * register 1501a09e64fbSRussell King * 1502a09e64fbSRussell King * Register 1503a09e64fbSRussell King * MECR Memory system: Expansion memory bus (PCMCIA) 1504a09e64fbSRussell King * Configuration Register (read/write). 1505a09e64fbSRussell King * 1506a09e64fbSRussell King * Clocks 1507a09e64fbSRussell King * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). 1508a09e64fbSRussell King * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2). 1509a09e64fbSRussell King * fbclk, Tbclk Frequency, period of the PCMCIA clock (BCLK). 1510a09e64fbSRussell King */ 1511a09e64fbSRussell King 1512a09e64fbSRussell King /* Memory system: */ 1513a09e64fbSRussell King #define MECR __REG(0xA0000018) /* Expansion memory bus (PCMCIA) Configuration Reg. */ 1514a09e64fbSRussell King 1515a09e64fbSRussell King #define MECR_PCMCIA(Nb) /* PCMCIA [0..1] */ \ 1516a09e64fbSRussell King Fld (15, (Nb)*16) 1517a09e64fbSRussell King #define MECR_PCMCIA0 MECR_PCMCIA (0) /* PCMCIA 0 */ 1518a09e64fbSRussell King #define MECR_PCMCIA1 MECR_PCMCIA (1) /* PCMCIA 1 */ 1519a09e64fbSRussell King 1520a09e64fbSRussell King #define MECR_BSIO Fld (5, 0) /* BCLK Select I/O - 1 [Tmem] */ 1521a09e64fbSRussell King #define MECR_IOClk(Tcpu) /* I/O Clock [2..64 Tcpu] */ \ 1522a09e64fbSRussell King ((((Tcpu) - 2)/2) << FShft (MECR_BSIO)) 1523a09e64fbSRussell King #define MECR_CeilIOClk(Tcpu) /* Ceil. of IOClk [2..64 Tcpu] */ \ 1524a09e64fbSRussell King ((((Tcpu) - 1)/2) << FShft (MECR_BSIO)) 1525a09e64fbSRussell King #define MECR_BSA Fld (5, 5) /* BCLK Select Attribute - 1 */ 1526a09e64fbSRussell King /* [Tmem] */ 1527a09e64fbSRussell King #define MECR_AttrClk(Tcpu) /* Attribute Clock [2..64 Tcpu] */ \ 1528a09e64fbSRussell King ((((Tcpu) - 2)/2) << FShft (MECR_BSA)) 1529a09e64fbSRussell King #define MECR_CeilAttrClk(Tcpu) /* Ceil. of AttrClk [2..64 Tcpu] */ \ 1530a09e64fbSRussell King ((((Tcpu) - 1)/2) << FShft (MECR_BSA)) 1531a09e64fbSRussell King #define MECR_BSM Fld (5, 10) /* BCLK Select Memory - 1 [Tmem] */ 1532a09e64fbSRussell King #define MECR_MemClk(Tcpu) /* Memory Clock [2..64 Tcpu] */ \ 1533a09e64fbSRussell King ((((Tcpu) - 2)/2) << FShft (MECR_BSM)) 1534a09e64fbSRussell King #define MECR_CeilMemClk(Tcpu) /* Ceil. of MemClk [2..64 Tcpu] */ \ 1535a09e64fbSRussell King ((((Tcpu) - 1)/2) << FShft (MECR_BSM)) 1536a09e64fbSRussell King 1537a09e64fbSRussell King /* 1538a09e64fbSRussell King * On SA1110 only 1539a09e64fbSRussell King */ 1540a09e64fbSRussell King 1541a09e64fbSRussell King #define MDREFR __REG(0xA000001C) 1542a09e64fbSRussell King 1543a09e64fbSRussell King #define MDREFR_TRASR Fld (4, 0) 1544a09e64fbSRussell King #define MDREFR_DRI Fld (12, 4) 1545a09e64fbSRussell King #define MDREFR_E0PIN (1 << 16) 1546a09e64fbSRussell King #define MDREFR_K0RUN (1 << 17) 1547a09e64fbSRussell King #define MDREFR_K0DB2 (1 << 18) 1548a09e64fbSRussell King #define MDREFR_E1PIN (1 << 20) 1549a09e64fbSRussell King #define MDREFR_K1RUN (1 << 21) 1550a09e64fbSRussell King #define MDREFR_K1DB2 (1 << 22) 1551a09e64fbSRussell King #define MDREFR_K2RUN (1 << 25) 1552a09e64fbSRussell King #define MDREFR_K2DB2 (1 << 26) 1553a09e64fbSRussell King #define MDREFR_EAPD (1 << 28) 1554a09e64fbSRussell King #define MDREFR_KAPD (1 << 29) 1555a09e64fbSRussell King #define MDREFR_SLFRSH (1 << 31) 1556a09e64fbSRussell King 1557a09e64fbSRussell King 1558a09e64fbSRussell King /* 1559a09e64fbSRussell King * Direct Memory Access (DMA) control registers 1560a09e64fbSRussell King */ 1561c2132010SRussell King #define DMA_SIZE (6 * 0x20) 1562c2132010SRussell King #define DMA_PHYS 0xb0000000 1563a09e64fbSRussell King 1564a09e64fbSRussell King 1565a09e64fbSRussell King /* 1566a09e64fbSRussell King * Liquid Crystal Display (LCD) control registers 1567a09e64fbSRussell King * 1568a09e64fbSRussell King * Registers 1569a09e64fbSRussell King * LCCR0 Liquid Crystal Display (LCD) Control Register 0 1570a09e64fbSRussell King * (read/write). 1571a09e64fbSRussell King * [Bits LDM, BAM, and ERM are only implemented in 1572a09e64fbSRussell King * versions 2.0 (rev. = 8) and higher of the StrongARM 1573a09e64fbSRussell King * SA-1100.] 1574a09e64fbSRussell King * LCSR Liquid Crystal Display (LCD) Status Register 1575a09e64fbSRussell King * (read/write). 1576a09e64fbSRussell King * [Bit LDD can be only read in versions 1.0 (rev. = 1) 1577a09e64fbSRussell King * and 1.1 (rev. = 2) of the StrongARM SA-1100, it can be 1578a09e64fbSRussell King * read and written (cleared) in versions 2.0 (rev. = 8) 1579a09e64fbSRussell King * and higher.] 1580a09e64fbSRussell King * DBAR1 Liquid Crystal Display (LCD) Direct Memory Access 1581a09e64fbSRussell King * (DMA) Base Address Register channel 1 (read/write). 1582a09e64fbSRussell King * DCAR1 Liquid Crystal Display (LCD) Direct Memory Access 1583a09e64fbSRussell King * (DMA) Current Address Register channel 1 (read). 1584a09e64fbSRussell King * DBAR2 Liquid Crystal Display (LCD) Direct Memory Access 1585a09e64fbSRussell King * (DMA) Base Address Register channel 2 (read/write). 1586a09e64fbSRussell King * DCAR2 Liquid Crystal Display (LCD) Direct Memory Access 1587a09e64fbSRussell King * (DMA) Current Address Register channel 2 (read). 1588a09e64fbSRussell King * LCCR1 Liquid Crystal Display (LCD) Control Register 1 1589a09e64fbSRussell King * (read/write). 1590a09e64fbSRussell King * [The LCCR1 register can be only written in 1591a09e64fbSRussell King * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the 1592a09e64fbSRussell King * StrongARM SA-1100, it can be written and read in 1593a09e64fbSRussell King * versions 2.0 (rev. = 8) and higher.] 1594a09e64fbSRussell King * LCCR2 Liquid Crystal Display (LCD) Control Register 2 1595a09e64fbSRussell King * (read/write). 1596a09e64fbSRussell King * [The LCCR1 register can be only written in 1597a09e64fbSRussell King * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the 1598a09e64fbSRussell King * StrongARM SA-1100, it can be written and read in 1599a09e64fbSRussell King * versions 2.0 (rev. = 8) and higher.] 1600a09e64fbSRussell King * LCCR3 Liquid Crystal Display (LCD) Control Register 3 1601a09e64fbSRussell King * (read/write). 1602a09e64fbSRussell King * [The LCCR1 register can be only written in 1603a09e64fbSRussell King * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the 1604a09e64fbSRussell King * StrongARM SA-1100, it can be written and read in 1605a09e64fbSRussell King * versions 2.0 (rev. = 8) and higher. Bit PCP is only 1606a09e64fbSRussell King * implemented in versions 2.0 (rev. = 8) and higher of 1607a09e64fbSRussell King * the StrongARM SA-1100.] 1608a09e64fbSRussell King * 1609a09e64fbSRussell King * Clocks 1610a09e64fbSRussell King * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). 1611a09e64fbSRussell King * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2). 1612a09e64fbSRussell King * fpix, Tpix Frequency, period of the pixel clock. 1613a09e64fbSRussell King * fln, Tln Frequency, period of the line clock. 1614a09e64fbSRussell King * fac, Tac Frequency, period of the AC bias clock. 1615a09e64fbSRussell King */ 1616a09e64fbSRussell King 1617a09e64fbSRussell King #define LCD_PEntrySp 2 /* LCD Palette Entry Space [byte] */ 1618a09e64fbSRussell King #define LCD_4BitPSp /* LCD 4-Bit pixel Palette Space */ \ 1619a09e64fbSRussell King /* [byte] */ \ 1620a09e64fbSRussell King (16*LCD_PEntrySp) 1621a09e64fbSRussell King #define LCD_8BitPSp /* LCD 8-Bit pixel Palette Space */ \ 1622a09e64fbSRussell King /* [byte] */ \ 1623a09e64fbSRussell King (256*LCD_PEntrySp) 1624a09e64fbSRussell King #define LCD_12_16BitPSp /* LCD 12/16-Bit pixel */ \ 1625a09e64fbSRussell King /* dummy-Palette Space [byte] */ \ 1626a09e64fbSRussell King (16*LCD_PEntrySp) 1627a09e64fbSRussell King 1628a09e64fbSRussell King #define LCD_PGrey Fld (4, 0) /* LCD Palette entry Grey value */ 1629a09e64fbSRussell King #define LCD_PBlue Fld (4, 0) /* LCD Palette entry Blue value */ 1630a09e64fbSRussell King #define LCD_PGreen Fld (4, 4) /* LCD Palette entry Green value */ 1631a09e64fbSRussell King #define LCD_PRed Fld (4, 8) /* LCD Palette entry Red value */ 1632a09e64fbSRussell King #define LCD_PBS Fld (2, 12) /* LCD Pixel Bit Size */ 1633a09e64fbSRussell King #define LCD_4Bit /* LCD 4-Bit pixel mode */ \ 1634a09e64fbSRussell King (0 << FShft (LCD_PBS)) 1635a09e64fbSRussell King #define LCD_8Bit /* LCD 8-Bit pixel mode */ \ 1636a09e64fbSRussell King (1 << FShft (LCD_PBS)) 1637a09e64fbSRussell King #define LCD_12_16Bit /* LCD 12/16-Bit pixel mode */ \ 1638a09e64fbSRussell King (2 << FShft (LCD_PBS)) 1639a09e64fbSRussell King 1640a09e64fbSRussell King #define LCD_Int0_0 0x0 /* LCD Intensity = 0.0% = 0 */ 1641a09e64fbSRussell King #define LCD_Int11_1 0x1 /* LCD Intensity = 11.1% = 1/9 */ 1642a09e64fbSRussell King #define LCD_Int20_0 0x2 /* LCD Intensity = 20.0% = 1/5 */ 1643a09e64fbSRussell King #define LCD_Int26_7 0x3 /* LCD Intensity = 26.7% = 4/15 */ 1644a09e64fbSRussell King #define LCD_Int33_3 0x4 /* LCD Intensity = 33.3% = 3/9 */ 1645a09e64fbSRussell King #define LCD_Int40_0 0x5 /* LCD Intensity = 40.0% = 2/5 */ 1646a09e64fbSRussell King #define LCD_Int44_4 0x6 /* LCD Intensity = 44.4% = 4/9 */ 1647a09e64fbSRussell King #define LCD_Int50_0 0x7 /* LCD Intensity = 50.0% = 1/2 */ 1648a09e64fbSRussell King #define LCD_Int55_6 0x8 /* LCD Intensity = 55.6% = 5/9 */ 1649a09e64fbSRussell King #define LCD_Int60_0 0x9 /* LCD Intensity = 60.0% = 3/5 */ 1650a09e64fbSRussell King #define LCD_Int66_7 0xA /* LCD Intensity = 66.7% = 6/9 */ 1651a09e64fbSRussell King #define LCD_Int73_3 0xB /* LCD Intensity = 73.3% = 11/15 */ 1652a09e64fbSRussell King #define LCD_Int80_0 0xC /* LCD Intensity = 80.0% = 4/5 */ 1653a09e64fbSRussell King #define LCD_Int88_9 0xD /* LCD Intensity = 88.9% = 8/9 */ 1654a09e64fbSRussell King #define LCD_Int100_0 0xE /* LCD Intensity = 100.0% = 1 */ 1655a09e64fbSRussell King #define LCD_Int100_0A 0xF /* LCD Intensity = 100.0% = 1 */ 1656a09e64fbSRussell King /* (Alternative) */ 1657a09e64fbSRussell King 1658a09e64fbSRussell King #define LCCR0_LEN 0x00000001 /* LCD ENable */ 1659a09e64fbSRussell King #define LCCR0_CMS 0x00000002 /* Color/Monochrome display Select */ 1660a09e64fbSRussell King #define LCCR0_Color (LCCR0_CMS*0) /* Color display */ 1661a09e64fbSRussell King #define LCCR0_Mono (LCCR0_CMS*1) /* Monochrome display */ 1662a09e64fbSRussell King #define LCCR0_SDS 0x00000004 /* Single/Dual panel display */ 1663a09e64fbSRussell King /* Select */ 1664a09e64fbSRussell King #define LCCR0_Sngl (LCCR0_SDS*0) /* Single panel display */ 1665a09e64fbSRussell King #define LCCR0_Dual (LCCR0_SDS*1) /* Dual panel display */ 1666a09e64fbSRussell King #define LCCR0_LDM 0x00000008 /* LCD Disable done (LDD) */ 1667a09e64fbSRussell King /* interrupt Mask (disable) */ 1668a09e64fbSRussell King #define LCCR0_BAM 0x00000010 /* Base Address update (BAU) */ 1669a09e64fbSRussell King /* interrupt Mask (disable) */ 1670a09e64fbSRussell King #define LCCR0_ERM 0x00000020 /* LCD ERror (BER, IOL, IUL, IOU, */ 1671a09e64fbSRussell King /* IUU, OOL, OUL, OOU, and OUU) */ 1672a09e64fbSRussell King /* interrupt Mask (disable) */ 1673a09e64fbSRussell King #define LCCR0_PAS 0x00000080 /* Passive/Active display Select */ 1674a09e64fbSRussell King #define LCCR0_Pas (LCCR0_PAS*0) /* Passive display (STN) */ 1675a09e64fbSRussell King #define LCCR0_Act (LCCR0_PAS*1) /* Active display (TFT) */ 1676a09e64fbSRussell King #define LCCR0_BLE 0x00000100 /* Big/Little Endian select */ 1677a09e64fbSRussell King #define LCCR0_LtlEnd (LCCR0_BLE*0) /* Little Endian frame buffer */ 1678a09e64fbSRussell King #define LCCR0_BigEnd (LCCR0_BLE*1) /* Big Endian frame buffer */ 1679a09e64fbSRussell King #define LCCR0_DPD 0x00000200 /* Double Pixel Data (monochrome */ 1680a09e64fbSRussell King /* display mode) */ 1681a09e64fbSRussell King #define LCCR0_4PixMono (LCCR0_DPD*0) /* 4-Pixel/clock Monochrome */ 1682a09e64fbSRussell King /* display */ 1683a09e64fbSRussell King #define LCCR0_8PixMono (LCCR0_DPD*1) /* 8-Pixel/clock Monochrome */ 1684a09e64fbSRussell King /* display */ 1685a09e64fbSRussell King #define LCCR0_PDD Fld (8, 12) /* Palette DMA request Delay */ 1686a09e64fbSRussell King /* [Tmem] */ 1687a09e64fbSRussell King #define LCCR0_DMADel(Tcpu) /* palette DMA request Delay */ \ 1688a09e64fbSRussell King /* [0..510 Tcpu] */ \ 1689a09e64fbSRussell King ((Tcpu)/2 << FShft (LCCR0_PDD)) 1690a09e64fbSRussell King 1691a09e64fbSRussell King #define LCSR_LDD 0x00000001 /* LCD Disable Done */ 1692a09e64fbSRussell King #define LCSR_BAU 0x00000002 /* Base Address Update (read) */ 1693a09e64fbSRussell King #define LCSR_BER 0x00000004 /* Bus ERror */ 1694a09e64fbSRussell King #define LCSR_ABC 0x00000008 /* AC Bias clock Count */ 1695a09e64fbSRussell King #define LCSR_IOL 0x00000010 /* Input FIFO Over-run Lower */ 1696a09e64fbSRussell King /* panel */ 1697a09e64fbSRussell King #define LCSR_IUL 0x00000020 /* Input FIFO Under-run Lower */ 1698a09e64fbSRussell King /* panel */ 1699a09e64fbSRussell King #define LCSR_IOU 0x00000040 /* Input FIFO Over-run Upper */ 1700a09e64fbSRussell King /* panel */ 1701a09e64fbSRussell King #define LCSR_IUU 0x00000080 /* Input FIFO Under-run Upper */ 1702a09e64fbSRussell King /* panel */ 1703a09e64fbSRussell King #define LCSR_OOL 0x00000100 /* Output FIFO Over-run Lower */ 1704a09e64fbSRussell King /* panel */ 1705a09e64fbSRussell King #define LCSR_OUL 0x00000200 /* Output FIFO Under-run Lower */ 1706a09e64fbSRussell King /* panel */ 1707a09e64fbSRussell King #define LCSR_OOU 0x00000400 /* Output FIFO Over-run Upper */ 1708a09e64fbSRussell King /* panel */ 1709a09e64fbSRussell King #define LCSR_OUU 0x00000800 /* Output FIFO Under-run Upper */ 1710a09e64fbSRussell King /* panel */ 1711a09e64fbSRussell King 1712a09e64fbSRussell King #define LCCR1_PPL Fld (6, 4) /* Pixels Per Line/16 - 1 */ 1713a09e64fbSRussell King #define LCCR1_DisWdth(Pixel) /* Display Width [16..1024 pix.] */ \ 1714a09e64fbSRussell King (((Pixel) - 16)/16 << FShft (LCCR1_PPL)) 1715a09e64fbSRussell King #define LCCR1_HSW Fld (6, 10) /* Horizontal Synchronization */ 1716a09e64fbSRussell King /* pulse Width - 1 [Tpix] (L_LCLK) */ 1717a09e64fbSRussell King #define LCCR1_HorSnchWdth(Tpix) /* Horizontal Synchronization */ \ 1718a09e64fbSRussell King /* pulse Width [1..64 Tpix] */ \ 1719a09e64fbSRussell King (((Tpix) - 1) << FShft (LCCR1_HSW)) 1720a09e64fbSRussell King #define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait */ 1721a09e64fbSRussell King /* count - 1 [Tpix] */ 1722a09e64fbSRussell King #define LCCR1_EndLnDel(Tpix) /* End-of-Line Delay */ \ 1723a09e64fbSRussell King /* [1..256 Tpix] */ \ 1724a09e64fbSRussell King (((Tpix) - 1) << FShft (LCCR1_ELW)) 1725a09e64fbSRussell King #define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */ 1726a09e64fbSRussell King /* Wait count - 1 [Tpix] */ 1727a09e64fbSRussell King #define LCCR1_BegLnDel(Tpix) /* Beginning-of-Line Delay */ \ 1728a09e64fbSRussell King /* [1..256 Tpix] */ \ 1729a09e64fbSRussell King (((Tpix) - 1) << FShft (LCCR1_BLW)) 1730a09e64fbSRussell King 1731a09e64fbSRussell King #define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */ 1732a09e64fbSRussell King #define LCCR2_DisHght(Line) /* Display Height [1..1024 lines] */ \ 1733a09e64fbSRussell King (((Line) - 1) << FShft (LCCR2_LPP)) 1734a09e64fbSRussell King #define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse */ 1735a09e64fbSRussell King /* Width - 1 [Tln] (L_FCLK) */ 1736a09e64fbSRussell King #define LCCR2_VrtSnchWdth(Tln) /* Vertical Synchronization pulse */ \ 1737a09e64fbSRussell King /* Width [1..64 Tln] */ \ 1738a09e64fbSRussell King (((Tln) - 1) << FShft (LCCR2_VSW)) 1739a09e64fbSRussell King #define LCCR2_EFW Fld (8, 16) /* End-of-Frame line clock Wait */ 1740a09e64fbSRussell King /* count [Tln] */ 1741a09e64fbSRussell King #define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \ 1742a09e64fbSRussell King /* [0..255 Tln] */ \ 1743a09e64fbSRussell King ((Tln) << FShft (LCCR2_EFW)) 1744a09e64fbSRussell King #define LCCR2_BFW Fld (8, 24) /* Beginning-of-Frame line clock */ 1745a09e64fbSRussell King /* Wait count [Tln] */ 1746a09e64fbSRussell King #define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \ 1747a09e64fbSRussell King /* [0..255 Tln] */ \ 1748a09e64fbSRussell King ((Tln) << FShft (LCCR2_BFW)) 1749a09e64fbSRussell King 1750a09e64fbSRussell King #define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor/2 - 2 */ 1751a09e64fbSRussell King /* [1..255] (L_PCLK) */ 1752a09e64fbSRussell King /* fpix = fcpu/(2*(PCD + 2)) */ 1753a09e64fbSRussell King /* Tpix = 2*(PCD + 2)*Tcpu */ 1754a09e64fbSRussell King #define LCCR3_PixClkDiv(Div) /* Pixel Clock Divisor [6..514] */ \ 1755a09e64fbSRussell King (((Div) - 4)/2 << FShft (LCCR3_PCD)) 1756a09e64fbSRussell King /* fpix = fcpu/(2*Floor (Div/2)) */ 1757a09e64fbSRussell King /* Tpix = 2*Floor (Div/2)*Tcpu */ 1758a09e64fbSRussell King #define LCCR3_CeilPixClkDiv(Div) /* Ceil. of PixClkDiv [6..514] */ \ 1759a09e64fbSRussell King (((Div) - 3)/2 << FShft (LCCR3_PCD)) 1760a09e64fbSRussell King /* fpix = fcpu/(2*Ceil (Div/2)) */ 1761a09e64fbSRussell King /* Tpix = 2*Ceil (Div/2)*Tcpu */ 1762a09e64fbSRussell King #define LCCR3_ACB Fld (8, 8) /* AC Bias clock half period - 1 */ 1763a09e64fbSRussell King /* [Tln] (L_BIAS) */ 1764a09e64fbSRussell King #define LCCR3_ACBsDiv(Div) /* AC Bias clock Divisor [2..512] */ \ 1765a09e64fbSRussell King (((Div) - 2)/2 << FShft (LCCR3_ACB)) 1766a09e64fbSRussell King /* fac = fln/(2*Floor (Div/2)) */ 1767a09e64fbSRussell King /* Tac = 2*Floor (Div/2)*Tln */ 1768a09e64fbSRussell King #define LCCR3_CeilACBsDiv(Div) /* Ceil. of ACBsDiv [2..512] */ \ 1769a09e64fbSRussell King (((Div) - 1)/2 << FShft (LCCR3_ACB)) 1770a09e64fbSRussell King /* fac = fln/(2*Ceil (Div/2)) */ 1771a09e64fbSRussell King /* Tac = 2*Ceil (Div/2)*Tln */ 1772a09e64fbSRussell King #define LCCR3_API Fld (4, 16) /* AC bias Pin transitions per */ 1773a09e64fbSRussell King /* Interrupt */ 1774a09e64fbSRussell King #define LCCR3_ACBsCntOff /* AC Bias clock transition Count */ \ 1775a09e64fbSRussell King /* Off */ \ 1776a09e64fbSRussell King (0 << FShft (LCCR3_API)) 1777a09e64fbSRussell King #define LCCR3_ACBsCnt(Trans) /* AC Bias clock transition Count */ \ 1778a09e64fbSRussell King /* [1..15] */ \ 1779a09e64fbSRussell King ((Trans) << FShft (LCCR3_API)) 1780a09e64fbSRussell King #define LCCR3_VSP 0x00100000 /* Vertical Synchronization pulse */ 1781a09e64fbSRussell King /* Polarity (L_FCLK) */ 1782a09e64fbSRussell King #define LCCR3_VrtSnchH (LCCR3_VSP*0) /* Vertical Synchronization pulse */ 1783a09e64fbSRussell King /* active High */ 1784a09e64fbSRussell King #define LCCR3_VrtSnchL (LCCR3_VSP*1) /* Vertical Synchronization pulse */ 1785a09e64fbSRussell King /* active Low */ 1786a09e64fbSRussell King #define LCCR3_HSP 0x00200000 /* Horizontal Synchronization */ 1787a09e64fbSRussell King /* pulse Polarity (L_LCLK) */ 1788a09e64fbSRussell King #define LCCR3_HorSnchH (LCCR3_HSP*0) /* Horizontal Synchronization */ 1789a09e64fbSRussell King /* pulse active High */ 1790a09e64fbSRussell King #define LCCR3_HorSnchL (LCCR3_HSP*1) /* Horizontal Synchronization */ 1791a09e64fbSRussell King /* pulse active Low */ 1792a09e64fbSRussell King #define LCCR3_PCP 0x00400000 /* Pixel Clock Polarity (L_PCLK) */ 1793a09e64fbSRussell King #define LCCR3_PixRsEdg (LCCR3_PCP*0) /* Pixel clock Rising-Edge */ 1794a09e64fbSRussell King #define LCCR3_PixFlEdg (LCCR3_PCP*1) /* Pixel clock Falling-Edge */ 1795a09e64fbSRussell King #define LCCR3_OEP 0x00800000 /* Output Enable Polarity (L_BIAS, */ 1796a09e64fbSRussell King /* active display mode) */ 1797a09e64fbSRussell King #define LCCR3_OutEnH (LCCR3_OEP*0) /* Output Enable active High */ 1798a09e64fbSRussell King #define LCCR3_OutEnL (LCCR3_OEP*1) /* Output Enable active Low */ 1799