Lines Matching +full:write +full:- +full:enable
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * TW5864 driver - registers description
8 /* According to TW5864_datasheet_0.6d.pdf, tw5864b1-ds.pdf */
10 /* Register Description - Direct Map Space */
11 /* 0x0000 ~ 0x1ffc - H264 Register Map */
19 /* Enable bit for Inter module */
21 /* Enable bit for Sensor Interface module */
23 /* Enable bit for Host Burst Access */
25 /* Enable bit for Loop Filter module */
27 /* Enable bit for PLBK module */
76 * 0->3 4 VLC data buffer in DDR (1M each)
77 * 0->7 8 VLC data buffer in DDR (512k each)
120 /* [15:0] SEN_EN_CH[n] SENIF original frame capture enable for each channel */
135 /* VLC Flow Control: 1 for enable */
147 /* DDR-DPR Burst Read Enable */
157 * 0 Single R/W Access (Host <-> DDR)
158 * 1 Burst R/W Access (Host <-> DPR)
196 * Inter_Mode Start. 2-nd bit? A guess. Missing in datasheet. Without this bit
200 /* Deinterlacer Enable */
203 * De-interlacer Mode
205 * 0 Normal Un-Shuffled Frame
210 * 11: Un-used
211 * 10: down-sample to 1/4
212 * 01: down-sample to 1/2
213 * 00: down-sample disabled
218 * 11: Un-used
219 * 10: down-sample to 1/4
220 * 01: down-sample to 1/2
221 * 00: down-sample disabled
240 * Skip Offset Enable bit
250 /* Enable quarter pel search mode */
252 /* Enable half pel search mode */
254 /* Enable motion search mode */
256 /* Enable Intra mode */
258 /* Enable Skip Mode */
289 /* OSD enable bit for each channel */
292 /* 0x0280 ~ 0x029c - Motion Vector for 1st 4x4 Block, e.g., 80 (X), 84 (Y) */
294 /* 0x02a0 ~ 0x02bc - Motion Vector for 2nd 4x4 Block, e.g., A0 (X), A4 (Y) */
296 /* 0x02c0 ~ 0x02dc - Motion Vector for 3rd 4x4 Block, e.g., C0 (X), C4 (Y) */
298 /* 0x02e0 ~ 0x02fc - Motion Vector for 4th 4x4 Block, e.g., E0 (X), E4 (Y) */
336 /* 0x0800 ~ 0x09ff - Quantization TABLE Values */
422 * Swap byte order of VLC stream in d-word.
427 /* Enable Adding 03 circuit for VLC stream */
438 /* Enable VLC overflow control */
446 * 0 Enable Adding 03 to VLC header and stream
465 /* VLC BK0 full status, write '1' to clear */
467 /* VLC BK1 full status, write '1' to clear */
469 /* VLC end slice status, write '1' to clear */
471 /* VLC Buffer overflow status, write '1' to clear */
479 /* [0] VLC Encoder Interrupt. Write '1' to clear */
497 /* 0x2000 ~ 0x2ffc - H264 Stream Memory Map */
509 /* 0x4000 ~ 0x4ffc - Audio Register Map */
515 /* ADPCM decoder enable */
517 /* ADPCM input data enable */
519 /* ADPCM encoder enable */
524 /* Record path PCM Audio enable bit for each channel */
526 /* Speaker path PCM Audio Enable */
548 /* Enable AD Loopback Test */
558 /* Record path ADPCM audio channel enable, one bit for each */
560 /* Speaker path ADPCM audio channel enable */
699 * The system / DDR clock (166 MHz) is generated with an on-chip system clock
829 /* 0x8800 ~ 0x88fc - Interrupt Register Map */
838 /* Enable of interrupt source 0 ~ 15 */
840 /* Enable of interrupt source 16 ~ 31 */
848 * 1 High level or pos-edge is assertion
849 * 0 Low level or neg-edge is assertion
912 /* 0x9000 ~ 0x920c - Video Capture (VIF) Register Map */
920 * [15:0] H264EN_CH_EN[n] H264 Encoding Path Enable for channel
992 * H264EN_BUSm_MAP_CHn The 16-to-1 MUX configuration register for each encoding
1009 /* GPIO Output Enable of Group n */
1012 /* 0xa000 ~ 0xa8ff - DDR Controller Register Map */
1035 * Trcd value, the minimum cycle of active to internal read/write command
1040 /* Twr value, write recovery time, default is 4"h3 */
1067 * 0 Common read/write mode
1068 * 1 DDR self-test mode
1072 * 0 DDR self-test single read/write
1073 * 1 DDR self-test burst read/write
1077 * 0 DDR self-test write command
1078 * 1 DDR self-test read command
1083 * 0 write 32'haaaa5555 to DDR
1084 * 1 write 32'hffffffff to DDR
1085 * 2 write 32'hha5a55a5a to DDR
1086 * 3 write increasing data to DDR
1090 /* [7:0] The maximum data of one burst in DDR self-test mode */
1092 /* [15:0] The maximum burst counter (bit 15~0) in DDR self-test mode */
1094 /* The maximum burst counter (bit 31~16) in DDR self-test mode */
1096 /* [0]: Start one DDR self-test */
1098 /* The maximum error counter (bit 15 ~ 0) in DDR self-test */
1103 /* The maximum error counter (bit 30 ~ 16) in DDR self-test */
1105 /* DDR self-test end flag */
1114 /* 0xb004 ~ 0xb018 - HW version/ARB12 Register Map */
1120 /* Audio data in to DDR enable (default 1) */
1122 /* Audio encode request to DDR enable (default 1) */
1124 /* Audio decode request0 to DDR enable (default 1) */
1126 /* Audio decode request1 to DDR enable (default 1) */
1128 /* VLC stream request to DDR enable (default 1) */
1130 /* H264 MV request to DDR enable (default 1) */
1132 /* mux_core MVD request to DDR enable (default 1) */
1134 /* mux_core MVD temp data request to DDR enable (default 1) */
1136 /* JPEG request to DDR enable (default 1) */
1138 /* mv_flag request to DDR enable (default 1) */
1143 /* ARB12 Enable (default 1) */
1148 /* 0xb800 ~ 0xb80c - Indirect Access Register Map */
1156 * Write Registers:
1157 * (1) Write IND_DATA at 0xb804 ~ 0xb807
1159 * (3) Write IND_ADDR at 0xb800 ~ 0xb801. Set R/W to "1", ENABLE to "1"
1162 * (2) Write IND_ADDR at 0xb800 ~ 0xb801. Set R/W to "0", ENABLE to "1"
1174 /* Read/Write command */
1177 /* [31:0] Data used to read/write indirect register space */
1180 /* 0xc000 ~ 0xc7fc - Preview Register Map */
1189 * [15:0] PCI Preview Path Enable for channel n
1190 * 1 Channel Enable
1195 /* 0xc800 ~ 0xc804 - JPEG Capture Register Map */
1197 /* 0xd000 ~ 0xd0fc - JPEG Control Register Map */
1200 /* 0xe000 ~ 0xfc04 - Motion Vector Register Map */
1209 /* mv bank0 full status , write "1" to clear */
1211 /* mv bank1 full status , write "1" to clear */
1213 /* slice end status; write "1" to clear */
1215 /* mv encode interrupt status; write "1" to clear */
1217 /* mv write memory overflow, write "1" to clear */
1234 /* 0x18000 ~ 0x181fc - PCI Master/Slave Control Map */
1256 /* master enable */
1258 /* mvd&vlc master enable */
1262 /* preview master enable */
1264 /* preview overflow enable */
1266 /* timer interrupt enable */
1268 /* JPEG master (push mode) enable */
1271 /* audio master channel enable */
1273 /* IIC interrupt enable */
1275 /* ad interrupt enable */
1277 /* target burst enable */
1279 /* vlc stream burst enable */
1281 /* ddr burst enable (1 enable, and must set DDR_BRST_EN) */
1300 /* master enable */
1302 /* mvd and vlc master enable */
1304 /* ad vsync master enable */
1306 /* jpeg master enable */
1308 /* preview master enable */
1312 * Every channel of preview and audio have ping-pong buffers in system memory,
1375 * PREV_PCI_ENB_CHN[0] Enable 9th preview channel (9CIF prev) or 1D1 channel in
1377 * PREV_PCI_ENB_CHN[1] Enable 10th preview channel
1382 /* IIC enable */
1407 /* 0x80000 ~ 0x87fff - DDR Burst RW Register Map */
1411 /* Length of 32-bit data burst */
1414 * Burst Read/Write
1416 * 1 Write Burst to DDR
1423 /* Enable Error Interrupt for Single DDR Access */
1425 /* Enable Error Interrupt for Burst DDR Access */
1427 /* Enable Interrupt for End of DDR Burst Access */
1444 /* 0x84000 - 0x87ffc */
1454 /* Read-only register */
1469 * 1 Sub-carrier PLL is locked to the incoming video source.
1470 * 0 Sub-carrier PLL is not locked.
1497 /* VCR signal indicator. Read-only. */
1499 /* Weak signal indicator 2. Read-only. */
1501 /* Weak signal indicator controlled by WKTH. Read-only. */
1505 * 0 = Non-standard signal
1506 * Read-only
1510 * 1 = Non-interlaced signal
1512 * Read-only
1559 * value from +36o (7Fh) to -36o (80h) with an increment of 2.8o. The 2 LSB has
1598 * These bits control the brightness. They have value of -128 to 127 in 2's
1624 /* Read-only */
1627 /* Macrovision color stripe detection may be un-reliable */
1641 /* Read-only */
1645 * Read-only.
1666 * 0 Enable VACTIVE and HDELAY shadow registers value depending on STANDARD.
1687 * process. This bit is a self-clearing bit
1691 /* Enable recognition of PAL60 (Default) */
1693 /* Enable recognition of PAL (CN). (Default) */
1695 /* Enable recognition of PAL (M). (Default) */
1697 /* Enable recognition of NTSC 4.43. (Default) */
1699 /* Enable recognition of SECAM. (Default) */
1701 /* Enable recognition of PAL (B, D, G, H, I). (Default) */
1703 /* Enable recognition of NTSC (M). (Default) */
1708 /* Use falling edge to sample VD1-VD4 from 54 MHz to 108 MHz */
1746 * LAWMD Select u-Law/A-Law/PCM/SB data output format on ADATR and ADATM pin.
1749 * 2 u-Law output
1750 * 3 A-Law output
1761 * Enable the mute function for audio channel AINn when n is 0 to 3. It effects
1762 * only for mixing. When n = 4, it enable the mute function of the playback
1774 * ADATP signal is coming from external ADPCM decoder, instead of on-chip ADPCM
1820 * 1 Almost duty 50-50% clock output on ACLKR pin. If this mode is selected, two
1825 /* Playback ACLKP/ASYNP/ADATP input data MSB-LSB swapping */
1842 * 1 Add 1 ACLKP clock delay in ADATP input data. This is for left-justified
1847 * Select u-Law/A-Law/PCM/SB data input format on ADATP pin.
1850 * 2 u-Law input
1851 * 3 A-Law input
1856 * Enable state register updating and interrupt request of audio AIN5 detection
1878 /* Enable cropping from 720 to 704 */
1882 * Interrupt status register from the front-end. Write "1" to each bit to clear
1933 * 0 Enable motion and blind detection (default)
2003 * Define the threshold of sub-cell number for motion detection.
2004 * 0 Motion is detected if 1 sub-cell has motion (More sensitive) (default)
2005 * 1 Motion is detected if 2 sub-cells have motion
2006 * 2 Motion is detected if 3 sub-cells have motion
2007 * 3 Motion is detected if 4 sub-cells have motion (Less sensitive)