Lines Matching +full:write +full:- +full:enable
1 /* SPDX-License-Identifier: GPL-2.0 */
12 #define CACR_DEC 0x80000000 /* Enable data cache */
13 #define CACR_DWP 0x40000000 /* Data write protection */
14 #define CACR_DESB 0x20000000 /* Enable data store buffer */
17 #define CACR_DDCM_WT 0x00000000 /* Write through cache*/
22 #define CACR_BEC 0x00080000 /* Enable branch cache */
24 #define CACR_IEC 0x00008000 /* Enable instruction cache */
30 #define CACR_EUSP 0x00000020 /* Enable separate user a7 */
34 #define ACR_ENABLE 0x00008000 /* Enable address */
38 #define ACR_CM_WT 0x00000000 /* Write through mode */
44 #define ACR_WPROTECT 0x00000004 /* Write protect */
47 #define ACR_ADMSK(x) ((((x) - 1) & 0xff000000) >> 8)
51 #define ICACHE_SIZE 0x4000 /* instruction - 16k */
52 #define DCACHE_SIZE 0x2000 /* data - 8k */
56 #define ICACHE_SIZE 0x8000 /* instruction - 32k */
57 #define DCACHE_SIZE 0x8000 /* data - 32k */
61 #define ICACHE_SIZE 0x2000 /* instruction - 8k */
62 #define DCACHE_SIZE 0x2000 /* data - 8k */
68 #define ICACHE_SET_MASK ((ICACHE_SIZE / 64 - 1) << CACHE_WAYS)
69 #define DCACHE_SET_MASK ((DCACHE_SIZE / 64 - 1) << CACHE_WAYS)
75 * and data cache. Enable data and instruction caches, also enable write
81 /* Enable data cache */
82 /* Enable data store buffer */
84 /* Enable instruction+branch caches */
95 * register region as non-cacheable. And then we map all our RAM as
114 * For the non-MMU enabled case we map all of RAM as cacheable.