Lines Matching +full:write +full:- +full:enable

1 /* SPDX-License-Identifier: GPL-2.0 */
6 /* Write Register 0 */
37 /* Write Register 1 */
39 #define	EXT_INT_ENAB	0x1	/* Ext Int Enable */
40 #define	TxINT_ENAB	0x2	/* Tx Int Enable */
50 #define	WT_RDY_ENAB	0x80	/* Wait/Ready Enable */
52 /* Write Register #2 (Interrupt Vector) */
54 /* Write Register 3 */
56 #define	RxENABLE	0x1	/* Rx Enable */
59 #define	RxCRC_ENAB	0x8	/* Rx CRC Enable */
67 /* Write Register 4 */
69 #define	PAR_ENA		0x1	/* Parity Enable */
72 #define	SYNC_ENAB	0	/* Sync Modes Enable */
87 /* Write Register 5 */
89 #define	TxCRC_ENAB	0x1	/* Tx CRC Enable */
91 #define	SDLC_CRC	0x4	/* SDLC/CRC-16 */
92 #define	TxENAB		0x8	/* Tx Enable */
100 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
102 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
104 /* Write Register 8 (transmit buffer) */
106 /* Write Register 9 (Master interrupt control) */
110 #define	MIE	8	/* Master Interrupt Enable */
112 #define	NORESET	0	/* No reset on write to R9 */
117 /* Write Register 10 (misc control bits) */
129 /* Write Register 11 (Clock Mode control) */
145 /* Write Register 12 (lower byte of baud rate generator time constant) */
147 /* Write Register 13 (upper byte of baud rate generator time constant) */
149 /* Write Register 14 (Misc control bits) */
150 #define	BRENABL	1	/* Baud rate generator enable */
163 /* Write Register 15 (external/status interrupt control) */
199 /* Read Register 2 (channel b only) - Interrupt vector */
225 /* Write Register 7' (SDLC/HDLC Programmable Enhancements) */
236 /* Write Register 15 (external/status interrupt control) */
237 #define SHDLCE	1		/* SDLC/HDLC Enhancements Enable */
238 #define FIFOE	4		/* FIFO Enable */