Lines Matching +full:write +full:- +full:enable
1 /* SPDX-License-Identifier: GPL-2.0+ */
26 * struct plx_dma_desc - DMA descriptor format for PLX PCI 9080
32 * Describes the format of a scatter-gather DMA descriptor for the PLX
33 * PCI 9080. All members are raw, little-endian register values that
37 * The DMA descriptors must be aligned on a 16-byte boundary. Bits 3:0
74 #define PLX_LASBA_EN BIT(0) /* Enable slave decode */
93 /* Local Bus Latency Timer Enable */
95 /* Local Bus Pause Timer Enable */
97 /* Local Bus BREQ Enable */
106 /* Direct Slace LLOCKo# Enable */
112 /* PCI Read No Write Mode */
114 /* PCI Read with Write Flush Mode */
137 /* Big Endian Byte Lane Mode - use most significant byte lanes */
174 /* Memory Space Ready Input Enable */
176 /* Memory Space BTERM# Input Enable */
180 /* Memory Space 1 Burst Enable (LBRD1 only) */
186 /* Read Prefetch Count Enable */
202 /* Expansion ROM Space Ready Input Enable (LBDR0 only) */
204 /* Expansion ROM Space BTERM# Input Enable (LBRD0 only) */
206 /* Memory Space 0 Burst Enable (LBRD0 only) */
210 /* Expansion ROM Space Burst Enable (LBRD0 only) */
212 /* Direct Slave PCI Write Mode - assert TRDY# when FIFO full (LBRD0 only) */
231 /* Direct Master Memory Access Enable */
233 /* Direct Master I/O Access Enable */
235 /* LLOCK# Input Enable */
243 /* Direct Master PCI Read Mode - deassert IRDY when FIFO full */
251 /* Write And Invalidate Mode */
257 /* Direct Master Write Delay */
263 /* Remap of Local-to-PCI Space Into PCI Address Space */
289 /* Configuration Enable */
315 /* PCI-to-Local Doorbell Register */
318 /* Local-to-PCI Doorbell Register */
324 /* Enable Local Bus LSERR# when PCI Bus Target Abort or Master Abort occurs */
326 /* Enable Local Bus LSERR# when PCI parity error occurs */
330 /* Mailbox Interrupt Enable (local bus interrupts on PCI write to MBOX0-3) */
332 /* PCI Interrupt Enable */
334 /* PCI Doorbell Interrupt Enable */
336 /* PCI Abort Interrupt Enable */
338 /* PCI Local Interrupt Enable */
340 /* Retry Abort Enable (for diagnostic purposes only) */
342 /* PCI Doorbell Interrupt Active (read-only) */
344 /* PCI Abort Interrupt Active (read-only) */
346 /* Local Interrupt (LINTi#) Active (read-only) */
348 /* Local Interrupt Output (LINTo#) Enable */
350 /* Local Doorbell Interrupt Enable */
352 /* DMA Channel 0 Interrupt Enable */
354 /* DMA Channel 1 Interrupt Enable */
356 /* DMA Channel N Interrupt Enable (N <= 1) */
358 /* Local Doorbell Interrupt Active (read-only) */
360 /* DMA Channel 0 Interrupt Active (read-only) */
362 /* DMA Channel 1 Interrupt Active (read-only) */
364 /* DMA Channel N Interrupt Active (N <= 1) (read-only) */
366 /* BIST Interrupt Active (read-only) */
368 /* Direct Master Not Bus Master During Master Or Target Abort (read-only) */
370 /* DMA Channel 0 Not Bus Master During Master Or Target Abort (read-only) */
372 /* DMA Channel 1 Not Bus Master During Master Or Target Abort (read-only) */
374 /* DMA Channel N Not Bus Master During Master Or Target Abort (read-only) */
377 /* Target Abort Not Generated After 256 Master Retries (read-only) */
379 /* PCI Wrote Mailbox 0 (enabled if bit 3 set) (read-only) */
381 /* PCI Wrote Mailbox 1 (enabled if bit 3 set) (read-only) */
383 /* PCI Wrote Mailbox 2 (enabled if bit 3 set) (read-only) */
385 /* PCI Wrote Mailbox 3 (enabled if bit 3 set) (read-only) */
387 /* PCI Wrote Mailbox N (N <= 3) (enabled if bit 3 set) (read-only) */
401 /* PCI Write Command Code For DMA 0 */
411 /* PCI Memory Write Command Code For Direct Master */
418 /* General Purpose Input (USERI) (read-only) */
424 /* Serial EEPROM Data Write Bit (EEDI (sic)) */
426 /* Serial EEPROM Data Read Bit (EEDO (sic)) (read-only) */
428 /* Serial EEPROM Present (read-only) */
434 /* Local Init Status (read-only) */
446 /* PCI Permanent Configuration ID Register (hard-coded PLX vendor and device) */
449 /* Hard-coded ID for PLX PCI 9080 */
452 /* PCI Permanent Revision ID Register (hard-coded silicon revision) (8-bit). */
470 /* Ready Input Enable */
472 /* BTERM# Input Enable */
474 /* Local Burst Enable */
476 /* Chaining Enable */
478 /* Done Interrupt Enable */
484 /* Write And Invalidate Mode */
486 /* DMA EOT Enable - enables EOT0# or EOT1# input pin */
488 /* DMA Stop Data Transfer Mode - 0:BLAST; 1:EOT asserted or DREQ deasserted */
490 /* DMA Clear Count Mode - count in descriptor cleared on completion */
492 /* DMA Channel Interrupt Select - 0:local bus interrupt; 1:PCI interrupt */
526 /* DMA Channel N Command/Status Register (N <= 1) (8-bit) */
531 /* Channel Enable */
533 /* Channel Start - write 1 to start transfer (write-only) */
535 /* Channel Abort - write 1 to abort transfer (write-only) */
537 /* Clear Interrupt - write 1 to clear DMA Channel Interrupt (write-only) */
539 /* Channel Done - transfer complete/inactive (read-only) */
553 /* DMA Channel 0 PCI-to-Local Almost Full (divided by 2, minus 1) */
557 /* DMA Channel 0 Local-to-PCI Almost Empty (divided by 2, minus 1) */
561 /* DMA Channel 0 Local-to-PCI Almost Full (divided by 2, minus 1) */
565 /* DMA Channel 0 PCI-to-Local Almost Empty (divided by 2, minus 1) */
569 /* DMA Channel 1 PCI-to-Local Almost Full (divided by 2, minus 1) */
573 /* DMA Channel 1 Local-to-PCI Almost Empty (divided by 2, minus 1) */
577 /* DMA Channel 1 Local-to-PCI Almost Full (divided by 2, minus 1) */
581 /* DMA Channel 1 PCI-to-Local Almost Empty (divided by 2, minus 1) */
597 /* Value of QSR after reset - disables I2O feature completely. */
602 * to pre-fetch data off of end-of-ram. Limit the size of
603 * memory so host-side accesses cannot occur.
609 * plx9080_abort_dma - Abort a PLX PCI 9080 DMA transfer
618 * -%ETIMEDOUT if timed out waiting for abort to complete.
640 return -ETIMEDOUT; in plx9080_abort_dma()
651 return -ETIMEDOUT; in plx9080_abort_dma()