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/linux/drivers/net/wireless/ath/ath9k/
H A Dar9003_paprd.c2 * Copyright (c) 2010-2011 Atheros Communications Inc.
21 void ar9003_paprd_enable(struct ath_hw *ah, bool val) in ar9003_paprd_enable() argument
23 struct ath9k_channel *chan = ah->curchan; in ar9003_paprd_enable()
28 * is used for sub-band disabling of PAPRD. in ar9003_paprd_enable()
29 * 5G band is divided into 3 sub-bands -- upper, in ar9003_paprd_enable()
32 * -- disable PAPRD for upper band 5GHz in ar9003_paprd_enable()
34 * -- disable PAPRD for middle band 5GHz in ar9003_paprd_enable()
36 * -- disable PAPRD for lower band 5GHz in ar9003_paprd_enable()
40 if (chan->channel >= UPPER_5G_SUB_BAND_START) { in ar9003_paprd_enable()
41 if (ar9003_get_paprd_rate_mask_ht20(ah, is2ghz) in ar9003_paprd_enable()
[all …]
H A Dar5008_phy.c2 * Copyright (c) 2008-2011 Atheros Communications Inc.
18 #include "hw-ops.h"
72 /* Addr 5G 2G */
89 static void ar5008_write_bank6(struct ath_hw *ah, unsigned int *writecnt) in ar5008_write_bank6() argument
91 struct ar5416IniArray *array = &ah->iniBank6; in ar5008_write_bank6()
92 u32 *data = ah->analogBank6Data; in ar5008_write_bank6()
95 ENABLE_REGWRITE_BUFFER(ah); in ar5008_write_bank6()
97 for (r = 0; r < array->ia_rows; r++) { in ar5008_write_bank6()
98 REG_WRITE(ah, INI_RA(array, r, 0), data[r]); in ar5008_write_bank6()
102 REGWRITE_BUFFER_FLUSH(ah); in ar5008_write_bank6()
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H A Dar9003_eeprom.c2 * Copyright (c) 2010-2011 Atheros Communications Inc.
36 #define SUB_NUM_CTL_MODES_AT_5G_40 2 /* excluding HT40, EXT-OFDM */
37 #define SUB_NUM_CTL_MODES_AT_2G_40 3 /* excluding HT40, EXT-OFDM, EXT-CCK */
49 .macAddr = {0, 2, 3, 4, 5, 6},
62 .deviceType = 5, /* takes lower byte in eeprom location */
67 * bit0 - enable tx temp comp - disabled
68 * bit1 - enable tx volt comp - disabled
69 * bit2 - enable fastClock - enabled
70 * bit3 - enable doubling - enabled
71 * bit4 - enable internal regulator - disabled
[all …]
H A Dhw.c2 * Copyright (c) 2008-2011 Atheros Communications Inc.
28 #include "hw-ops.h"
34 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
40 static void ath9k_hw_set_clockrate(struct ath_hw *ah) in ath9k_hw_set_clockrate() argument
42 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_set_clockrate()
43 struct ath9k_channel *chan = ah->curchan; in ath9k_hw_set_clockrate()
47 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) in ath9k_hw_set_clockrate()
53 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK) in ath9k_hw_set_clockrate()
67 common->clockrate = clockrate; in ath9k_hw_set_clockrate()
70 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs) in ath9k_hw_mac_to_clks() argument
[all …]
H A Deeprom.h2 * Copyright (c) 2008-2011 Atheros Communications Inc.
20 #define AR_EEPROM_MODAL_SPURS 5
80 #define CTL_2GHT20 5
109 #define FREQ2FBIN(x, y) (u8)((y) ? ((x) - 2300) : (((x) - 4800) / 5))
110 #define FBIN2FREQ(x, y) ((y) ? (2300 + x) : (4800 + 5 * x))
111 #define ath9k_hw_use_flash(_ah) (!(_ah->ah_flags & AH_USE_EEPROM))
114 _ah->eep_ops->get_eeprom(_ah, EEP_OL_PWRCTRL))
116 _ah->eep_ops->get_eeprom(_ah, EEP_OL_PWRCTRL))
122 #define EEP_RFSILENT_GPIO_SEL ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x00fc : 0x001c)
159 #define AR5416_PD_GAIN_ICEPTS 5
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H A Dar9003_wow.c19 #include "reg.h"
21 #include "hw-ops.h"
23 static void ath9k_hw_set_sta_powersave(struct ath_hw *ah) in ath9k_hw_set_sta_powersave() argument
25 if (!ath9k_hw_mci_is_enabled(ah)) in ath9k_hw_set_sta_powersave()
31 if (ar9003_mci_state(ah, MCI_STATE_GET_WLAN_PS_STATE) != MCI_PS_DISABLE) in ath9k_hw_set_sta_powersave()
34 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); in ath9k_hw_set_sta_powersave()
37 static void ath9k_hw_set_powermode_wow_sleep(struct ath_hw *ah) in ath9k_hw_set_powermode_wow_sleep() argument
39 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_set_powermode_wow_sleep()
41 ath9k_hw_set_sta_powersave(ah); in ath9k_hw_set_powermode_wow_sleep()
44 REG_WRITE(ah, AR_CR, AR_CR_RXD); in ath9k_hw_set_powermode_wow_sleep()
[all …]
H A Dhtc_drv_init.c2 * Copyright (c) 2010-2011 Atheros Communications Inc.
35 MODULE_PARM_DESC(btcoex_enable, "Enable wifi-BT coexistence");
53 { .throughput = 5 * 1024, .blink_time = 220 },
66 ath9k_htc_ps_wakeup(common->priv); in ath9k_htc_op_ps_wakeup()
71 ath9k_htc_ps_restore(common->priv); in ath9k_htc_op_ps_restore()
83 if (atomic_read(&priv->htc->tgt_ready) > 0) { in ath9k_htc_wait_for_target()
84 atomic_dec(&priv->htc->tgt_ready); in ath9k_htc_wait_for_target()
89 time_left = wait_for_completion_timeout(&priv->htc->target_wait, HZ); in ath9k_htc_wait_for_target()
91 dev_err(priv->dev, "ath9k_htc: Target is unresponsive\n"); in ath9k_htc_wait_for_target()
92 return -ETIMEDOUT; in ath9k_htc_wait_for_target()
[all …]
H A Dar9003_phy.c2 * Copyright (c) 2010-2011 Atheros Communications Inc.
38 /* level: 0 1 2 3 4 5 6 7 8 */
39 { -4, -2, 0, 2, 4, 6, 8, 10, 12 }; /* lvl 0-8, default 2 */
42 /* level: 0 1 2 3 4 5 6 7 8 */
43 { -6, -4, -2, 0, 2, 4, 6, 8 }; /* lvl 0-7, default 3 */
125 * ar9003_hw_set_channel - set channel on single-chip device
126 * @ah: atheros hardware structure
129 * This is the function to change channel on single-chip devices, that is
141 * For 5GHz channel,
145 * For 5GHz channels which are 5MHz spaced,
[all …]
H A Dinit.c2 * Copyright (c) 2008-2011 Atheros Communications Inc.
19 #include <linux/dma-mapping.h>
24 #include <linux/nvmem-consumer.h>
33 struct ath_hw *ah; member
54 static int ath9k_led_active_high = -1;
60 MODULE_PARM_DESC(btcoex_enable, "Enable wifi-BT coexistence");
88 { .throughput = 5 * 1024, .blink_time = 220 },
108 .ident = "Dell Inspiron 24-3460",
111 DMI_MATCH(DMI_PRODUCT_NAME, "Inspiron 24-3460"),
132 .ident = "Dell Vostro 15-3572",
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H A Dmac.c2 * Copyright (c) 2008-2011 Atheros Communications Inc.
18 #include "hw-ops.h"
21 static void ath9k_hw_set_txq_interrupts(struct ath_hw *ah, in ath9k_hw_set_txq_interrupts() argument
24 ath_dbg(ath9k_hw_common(ah), INTERRUPT, in ath9k_hw_set_txq_interrupts()
26 ah->txok_interrupt_mask, ah->txerr_interrupt_mask, in ath9k_hw_set_txq_interrupts()
27 ah->txdesc_interrupt_mask, ah->txeol_interrupt_mask, in ath9k_hw_set_txq_interrupts()
28 ah->txurn_interrupt_mask); in ath9k_hw_set_txq_interrupts()
30 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_set_txq_interrupts()
32 REG_WRITE(ah, AR_IMR_S0, in ath9k_hw_set_txq_interrupts()
33 SM(ah->txok_interrupt_mask, AR_IMR_S0_QCU_TXOK) in ath9k_hw_set_txq_interrupts()
[all …]
H A Dmain.c2 * Copyright (c) 2008-2011 Atheros Communications Inc.
34 * 5 for 4 us in ath9k_parse_mpdudensity()
49 case 5: in ath9k_parse_mpdudensity()
65 spin_lock_bh(&txq->axq_lock); in ath9k_has_pending_frames()
67 if (txq->axq_depth) { in ath9k_has_pending_frames()
75 if (txq->mac80211_qnum >= 0) { in ath9k_has_pending_frames()
78 acq = &sc->cur_chan->acq[txq->mac80211_qnum]; in ath9k_has_pending_frames()
79 if (!list_empty(&acq->acq_new) || !list_empty(&acq->acq_old)) in ath9k_has_pending_frames()
83 spin_unlock_bh(&txq->axq_lock); in ath9k_has_pending_frames()
92 spin_lock_irqsave(&sc->sc_pm_lock, flags); in ath9k_setpower()
[all …]
/linux/drivers/net/wireless/ath/ath5k/
H A Dath5k.h2 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com>
22 * working on reg. control code using all available eeprom information
62 #define PCI_DEVICE_ID_ATHEROS_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
63 #define PCI_DEVICE_ID_ATHEROS_AR5312_REV8 0x0058 /* AR5312 WMAC (AP43-030) */
70 #define PCI_DEVICE_ID_ATHEROS_AR2413 0x001a /* AR2413 (Griffin-lite) */
72 #define PCI_DEVICE_ID_ATHEROS_AR5424 0x001c /* AR5424 (Condor PCI-E) */
84 _ath5k_printk(const struct ath5k_hw *ah, const char *level,
124 #define AR5K_REG_WRITE_BITS(ah, _reg, _flags, _val) \ argument
125 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & ~(_flags)) | \
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H A Dphy.c2 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com>
4 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
5 * Copyright (c) 2008-2009 Felix Fietkau <nbd@openwrt.org>
33 #include "reg.h"
42 * Here we handle the low-level functions related to baseband
48 * - Channel setting/switching
50 * - Automatic Gain Control (AGC) calibration
52 * - Noise Floor calibration
54 * - I/Q imbalance calibration (QAM correction)
[all …]
H A Dcaps.c2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
4 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
25 #include "reg.h"
33 int ath5k_hw_set_capabilities(struct ath5k_hw *ah) in ath5k_hw_set_capabilities() argument
35 struct ath5k_capabilities *caps = &ah->ah_capabilities; in ath5k_hw_set_capabilities()
39 ee_header = caps->cap_eeprom.ee_header; in ath5k_hw_set_capabilities()
41 if (ah->ah_version == AR5K_AR5210) { in ath5k_hw_set_capabilities()
44 * (The AR5110 only supports the middle 5GHz band) in ath5k_hw_set_capabilities()
46 caps->cap_range.range_5ghz_min = 5120; in ath5k_hw_set_capabilities()
[all …]
H A Dpcu.c2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
4 * Copyright (c) 2007-2008 Matthew W. S. Bell <mentor@madwifi.org>
5 * Copyright (c) 2007-2008 Luis Rodriguez <mcgrof@winlab.rutgers.edu>
6 * Copyright (c) 2007-2008 Pavel Roskin <proski@gnu.org>
7 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
30 #include "reg.h"
40 * - Buffering of RX and TX frames (after QCU/DCUs)
42 * - Encrypting and decrypting (using the built-in engine)
44 * - Generating ACKs, RTS/CTS frames
[all …]
H A Ddebug.c2 * Copyright (c) 2007-2008 Bruno Randolf <bruno@thinktube.com>
21 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
22 * Copyright (c) 2004-2005 Atheros Communications, Inc.
39 * 3. Neither the names of the above-listed copyright holders nor the names
71 #include "reg.h"
80 struct reg { struct
88 static const struct reg regs[] = { argument
157 struct ath5k_hw *ah = seq->private; in reg_show() local
158 struct reg *r = p; in reg_show()
159 seq_printf(seq, "%-25s0x%08x\n", r->name, in reg_show()
[all …]
H A Dani.c20 #include "reg.h"
33 * - "noise immunity"
35 * - "spur immunity"
37 * - "firstep level"
39 * - "OFDM weak signal detection"
41 * - "CCK weak signal detection"
61 * ath5k_ani_set_noise_immunity_level() - Set noise immunity level
62 * @ah: The &struct ath5k_hw
66 ath5k_ani_set_noise_immunity_level(struct ath5k_hw *ah, int level) in ath5k_ani_set_noise_immunity_level() argument
75 static const s8 lo[] = { -52, -56, -60, -64, -70 }; in ath5k_ani_set_noise_immunity_level()
[all …]
H A Deeprom.c2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com>
4 * Copyright (c) 2008-2009 Felix Fietkau <nbd@openwrt.org>
29 #include "reg.h"
49 if (ee->ee_version > AR5K_EEPROM_VERSION_3_2) in ath5k_eeprom_bin2freq()
50 val = (5 * bin) + 4800; in ath5k_eeprom_bin2freq()
52 val = bin > 62 ? (10 * 62) + (5 * (bin - 62)) + 5100 : in ath5k_eeprom_bin2freq()
55 if (ee->ee_version > AR5K_EEPROM_VERSION_3_2) in ath5k_eeprom_bin2freq()
73 ath5k_eeprom_init_header(struct ath5k_hw *ah) in ath5k_eeprom_init_header() argument
75 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; in ath5k_eeprom_init_header()
[all …]
H A Dbase.c1 /*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
20 * 3. Neither the names of the above-listed copyright holders nor the names
47 #include <linux/dma-mapping.h>
66 #include "reg.h"
92 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
96 static int ath5k_reset(struct ath5k_hw *ah, struct ieee80211_channel *chan,
200 static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp) in ath5k_extend_tsf() argument
202 u64 tsf = ath5k_hw_get_tsf64(ah); in ath5k_extend_tsf()
[all …]
H A Dmac80211-ops.c1 /*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
21 * 3. Neither the names of the above-listed copyright holders nor the names
51 #include "reg.h"
61 struct ath5k_hw *ah = hw->priv; in ath5k_tx() local
64 if (WARN_ON(qnum >= ah->ah_capabilities.cap_queues.q_tx_num)) { in ath5k_tx()
69 ath5k_tx_queue(hw, skb, &ah->txqs[qnum], control); in ath5k_tx()
76 struct ath5k_hw *ah = hw->priv; in ath5k_add_interface() local
78 struct ath5k_vif *avf = (void *)vif->drv_priv; in ath5k_add_interface()
[all …]
H A Dinitvals.c4 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
5 * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com>
6 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
25 #include "reg.h"
29 * struct ath5k_ini - Mode-independent initial register writes
45 * struct ath5k_ini_mode - Mode specific initial register values
96 { AR5K_PHY(5), 0x0000076b },
132 { AR5K_BB_GAIN(5), 0x00000028 },
197 { AR5K_RF_GAIN(5), 0x00000021 },
283 { AR5K_QUEUE_TXDP(5), 0x00000000 },
[all …]
/linux/arch/x86/pci/
H A Dpcbios.c1 // SPDX-License-Identifier: GPL-2.0
16 #include <asm/pci-functions.h>
36 * - AH: return code
51 * We could make the 0xe0000-0x100000 range rox, but this can break
61 set_memory_x(PAGE_OFFSET + BIOS_BEGIN, (BIOS_END - BIOS_BEGIN) >> PAGE_SHIFT); in set_bios_x()
69 * Standard BIOS 32-bit Service Directory Proposal
83 unsigned char reserved[5]; /* Must be zero */
130 printk(KERN_WARNING "bios32_service(0x%lx): returned 0x%x -- BIOS bug!\n", in bios32_service()
159 "xor %%ah, %%ah\n" in check_pcibios()
197 unsigned int devfn, int reg, int len, u32 *value) in pci_bios_read() argument
[all …]
/linux/drivers/net/wireless/ath/ath12k/
H A Dreg.c1 // SPDX-License-Identifier: BSD-3-Clause-Clear
3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved.
12 #define ATH12K_2GHZ_CH01_11 REG_RULE(2412 - 10, 2462 + 10, 40, 0, 20, 0)
13 #define ATH12K_5GHZ_5150_5350 REG_RULE(5150 - 10, 5350 + 10, 80, 0, 30,\
15 #define ATH12K_5GHZ_5725_5850 REG_RULE(5725 - 10, 5850 + 10, 80, 0, 30,\
36 regd = rcu_dereference_rtnl(hw->wiphy->regd); in ath12k_regdom_changes()
44 return memcmp(regd->alpha2, alpha2, 2) != 0; in ath12k_regdom_changes()
53 struct ath12k_hw *ah = ath12k_hw_to_ah(hw); in ath12k_reg_notifier() local
54 struct ath12k *ar = ath12k_ah_to_ar(ah, 0); in ath12k_reg_notifier()
[all …]
H A Ddebugfs.c1 // SPDX-License-Identifier: BSD-3-Clause-Clear
3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved.
17 struct ath12k *ar = file->private_data; in ath12k_write_simulate_radar()
20 wiphy_lock(ath12k_ar_to_hw(ar)->wiphy); in ath12k_write_simulate_radar()
27 wiphy_unlock(ath12k_ar_to_hw(ar)->wiphy); in ath12k_write_simulate_radar()
42 "`assert` - send WMI_FORCE_FW_HANG_CMDID to firmware to cause assert.\n"; in ath12k_read_simulate_fw_crash()
52 struct ath12k_base *ab = file->private_data; in ath12k_write_simulate_fw_crash()
61 return -EINVAL; in ath12k_write_simulate_fw_crash()
63 rc = simple_write_to_buffer(buf, sizeof(buf) - 1, ppos, user_buf, count); in ath12k_write_simulate_fw_crash()
[all …]
/linux/include/xen/interface/
H A Dplatform.h1 /* SPDX-License-Identifier: MIT */
5 * Hardware platform operations. Intended for use by domain-0 kernel.
7 * Copyright (c) 2002-2006, K Fraser
40 * Request memory range (@mfn, @mfn+@nr_mfns-1) to have type @type.
41 * On x86, @type is an architecture-defined MTRR memory type.
42 * On success, returns the MTRR that was used (@reg) and a handle that can
44 * (x86-specific).
54 uint32_t reg; member
59 * Tear down an existing memory-range type. If @handle is remembered then it
62 * then @handle should be set to zero. In all cases @reg must be set.
[all …]

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