Lines Matching +full:reg +full:- +full:5 +full:ah
2 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com>
22 * working on reg. control code using all available eeprom information
62 #define PCI_DEVICE_ID_ATHEROS_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
63 #define PCI_DEVICE_ID_ATHEROS_AR5312_REV8 0x0058 /* AR5312 WMAC (AP43-030) */
70 #define PCI_DEVICE_ID_ATHEROS_AR2413 0x001a /* AR2413 (Griffin-lite) */
72 #define PCI_DEVICE_ID_ATHEROS_AR5424 0x001c /* AR5424 (Condor PCI-E) */
84 _ath5k_printk(const struct ath5k_hw *ah, const char *level,
124 #define AR5K_REG_WRITE_BITS(ah, _reg, _flags, _val) \ argument
125 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & ~(_flags)) | \
128 #define AR5K_REG_MASKED_BITS(ah, _reg, _flags, _mask) \ argument
129 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & \
132 #define AR5K_REG_ENABLE_BITS(ah, _reg, _flags) \ argument
133 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) | (_flags), _reg)
135 #define AR5K_REG_DISABLE_BITS(ah, _reg, _flags) \ argument
136 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) & ~(_flags), _reg)
139 #define AR5K_REG_READ_Q(ah, _reg, _queue) \ argument
140 (ath5k_hw_reg_read(ah, _reg) & (1 << _queue)) \
142 #define AR5K_REG_WRITE_Q(ah, _reg, _queue) \ argument
143 ath5k_hw_reg_write(ah, (1 << _queue), _reg)
189 #define AR5K_TUNE_NOISE_FLOOR -72
190 #define AR5K_TUNE_CCA_MAX_GOOD_VALUE -95
232 /* Used to calculate tx time for non 5/10/40MHz
241 /* Rx latency for 5 and 10MHz operation (max ?) */
274 * enum ath5k_version - MAC Chips
286 * enum ath5k_radio - PHY Chips
290 * @AR5K_RF2413: RF2413/2414 (Griffin/Griffin-Lite)
302 AR5K_RF2316 = 5,
327 #define AR5K_SREV_AR2315_R6 0x86 /* AP51-Light */
328 #define AR5K_SREV_AR2315_R7 0x87 /* AP51-Full */
330 #define AR5K_SREV_AR2317_R1 0x90 /* AP61-Light */
331 #define AR5K_SREV_AR2317_R2 0x91 /* AP61-Full */
335 #define AR5K_SREV_AR5416 0xc0 /* PCI-E */
336 #define AR5K_SREV_AR5418 0xca /* PCI-E */
366 /* TODO add support to mac80211 for vendor-specific rates and modes */
373 * http://madwifi-project.org/wiki/ChipsetFeatures/SuperAG
375 * Atheros' eXtended Range - range enhancing extension is a modulation scheme
376 * that is supposed to double the link distance between an Atheros XR-enabled
377 * client device with an Atheros XR-enabled access point. This is achieved
378 * by increasing the receiver sensitivity up to, -105dBm, which is about 20dB
386 * get a mode similar to XR by using 5MHz bwmode.
395 * -60Mbit/s at a 108Mbit/s signaling rate achieved through the bonding of two
399 * - Static: is the dumb version: devices set to this mode stick to it until
402 * - Dynamic: is the intelligent version, the network decides itself if it
404 * (which would get used in turbo mode), or when a non-turbo station joins
410 * This article claims Super G sticks to bonding of channels 5 and 6 for
413 * https://www.pcworld.com/article/id,113428-page,1/article.html
418 * greater speed-up:
420 * - Bursting: allows multiple frames to be sent at once, rather than pausing
421 * after each frame. Bursting is a standards-compliant feature that can be
424 * - Fast frames: increases the amount of information that can be sent per
428 * - Compression: data frames are compressed in real time using a Lempel Ziv
439 * enum ath5k_driver_mode - PHY operation mode
456 * enum ath5k_ant_mode - Antenna operation mode
463 * @AR5K_ANTMODE_DEBUG: Debug mode -A -> Rx, B-> Tx-
474 AR5K_ANTMODE_SECTOR_STA = 5,
480 * enum ath5k_bw_mode - Bandwidth operation mode
500 * struct ath5k_tx_status - TX Status descriptor
532 * enum ath5k_tx_queue - Queue types used to classify tx queues.
533 * @AR5K_TX_QUEUE_INACTIVE: q is unused -- see ath5k_hw_release_tx_queue
536 * @AR5K_TX_QUEUE_CAB: The after-beacon queue
551 * enum ath5k_tx_queue_subtype - Queue sub-types to classify normal data queues
553 * @AR5K_WME_AC_BE: Best-effort (normal) traffic
570 * enum ath5k_tx_queue_id - Queue ID numbers as returned by the hw functions
597 #define AR5K_TXQ_FLAG_TXEOLINT_ENABLE 0x0004 /* Enable TXEOL interrupt -not used- */
598 #define AR5K_TXQ_FLAG_TXDESCINT_ENABLE 0x0008 /* Enable TXDESC interrupt -not used- */
604 #define AR5K_TXQ_FLAG_BACKOFF_DISABLE 0x0200 /* Disable random post-backoff */
608 #define AR5K_TXQ_FLAG_COMPRESSION_ENABLE 0x2000 /* Enable hw compression -not implemented-*/
611 * struct ath5k_txq - Transmit queue state
642 * struct ath5k_txq_info - A struct to hold TX queue's parameters
646 * @tqi_aifs: Arbitrated Inter-frame Space
666 * enum ath5k_pkt_type - Transmit packet types
669 * @AR5K_PKT_TYPE_PSPOLL: PS-Poll
681 AR5K_PKT_TYPE_PIFS = 5,
689 (((ah->ah_txpower.txp_rates_power_table[(_r)]) & 0x3f) << (_v)) \
693 (ah->ah_txpower.txp_rates_power_table[(_r)] & 0x3f) << (_v) \
703 * struct ath5k_rx_status - RX Status descriptor
731 #define AR5K_RXKEYIX_INVALID ((u8) -1)
732 #define AR5K_TXKEYIX_INVALID ((u32) -1)
760 * enum ath5k_rfgain - RF Gain optimization engine state
774 * struct ath5k_gain - RF Gain optimization engine state data
804 * struct ath5k_athchan_2ghz - 2GHz to 5GHZ map for RF5111
809 * 5GHz Atheros channels on 2111 frequency converter
819 * enum ath5k_dmasize - DMA size definitions (2^(n+2))
854 * Seems the ar5xxx hardware supports up to 32 rates, indexed by 1-32.
863 * --------- -----------
867 * 0x04 - 05 -Reserved-
878 * 0x10 - 17 -Reserved-
886 * 0x1F -Reserved-
942 * enum ath5k_int - Hardware interrupt masks helpers
972 * @AR5K_INT_SWBA: SoftWare Beacon Alert - indicates its time to send a
1082 * enum ath5k_calibration_mask - Mask which calibration is active at the moment
1096 * enum ath5k_power_mode - Power management modes
1127 /* GPIO-controlled software LED */
1182 struct ath5k_hw *ah; /* driver state */ member
1199 unsigned int antenna_rx[5]; /* frames count per antenna RX */
1200 unsigned int antenna_tx[5]; /* frames count per antenna TX */
1266 struct mutex lock; /* dev-level lock */
1463 int (*eeprom_read_mac)(struct ath5k_hw *ah, u8 *mac);
1472 int ath5k_hw_init(struct ath5k_hw *ah);
1473 void ath5k_hw_deinit(struct ath5k_hw *ah);
1475 int ath5k_sysfs_register(struct ath5k_hw *ah);
1476 void ath5k_sysfs_unregister(struct ath5k_hw *ah);
1479 int ath5k_hw_read_srev(struct ath5k_hw *ah);
1482 int ath5k_init_leds(struct ath5k_hw *ah);
1483 void ath5k_led_enable(struct ath5k_hw *ah);
1484 void ath5k_led_off(struct ath5k_hw *ah);
1485 void ath5k_unregister_leds(struct ath5k_hw *ah);
1489 int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, struct ieee80211_channel *channel);
1490 int ath5k_hw_on_hold(struct ath5k_hw *ah);
1491 int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
1493 int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val,
1499 unsigned int ath5k_hw_htoclock(struct ath5k_hw *ah, unsigned int usec);
1500 unsigned int ath5k_hw_clocktoh(struct ath5k_hw *ah, unsigned int clock);
1501 void ath5k_hw_set_clockrate(struct ath5k_hw *ah);
1505 void ath5k_hw_start_rx_dma(struct ath5k_hw *ah);
1506 u32 ath5k_hw_get_rxdp(struct ath5k_hw *ah);
1507 int ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr);
1508 int ath5k_hw_start_tx_dma(struct ath5k_hw *ah, unsigned int queue);
1509 int ath5k_hw_stop_beacon_queue(struct ath5k_hw *ah, unsigned int queue);
1510 u32 ath5k_hw_get_txdp(struct ath5k_hw *ah, unsigned int queue);
1511 int ath5k_hw_set_txdp(struct ath5k_hw *ah, unsigned int queue,
1513 int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, bool increase);
1515 bool ath5k_hw_is_intr_pending(struct ath5k_hw *ah);
1516 int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask);
1517 enum ath5k_int ath5k_hw_set_imr(struct ath5k_hw *ah, enum ath5k_int new_mask);
1518 void ath5k_hw_update_mib_counters(struct ath5k_hw *ah);
1520 void ath5k_hw_dma_init(struct ath5k_hw *ah);
1521 int ath5k_hw_dma_stop(struct ath5k_hw *ah);
1524 int ath5k_eeprom_init(struct ath5k_hw *ah);
1525 void ath5k_eeprom_detach(struct ath5k_hw *ah);
1526 int ath5k_eeprom_mode_from_channel(struct ath5k_hw *ah,
1531 int ath5k_hw_get_frame_duration(struct ath5k_hw *ah, enum nl80211_band band,
1533 unsigned int ath5k_hw_get_default_slottime(struct ath5k_hw *ah);
1534 unsigned int ath5k_hw_get_default_sifs(struct ath5k_hw *ah);
1535 int ath5k_hw_set_opmode(struct ath5k_hw *ah, enum nl80211_iftype opmode);
1536 void ath5k_hw_set_coverage_class(struct ath5k_hw *ah, u8 coverage_class);
1538 int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac);
1539 void ath5k_hw_set_bssid(struct ath5k_hw *ah);
1540 void ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask);
1541 void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1);
1542 u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah);
1543 void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter);
1545 void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah);
1546 void ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah);
1548 u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah);
1549 void ath5k_hw_set_tsf64(struct ath5k_hw *ah, u64 tsf64);
1550 void ath5k_hw_reset_tsf(struct ath5k_hw *ah);
1551 void ath5k_hw_init_beacon_timers(struct ath5k_hw *ah, u32 next_beacon,
1553 bool ath5k_hw_check_beacon_timers(struct ath5k_hw *ah, int intval);
1555 void ath5k_hw_pcu_init(struct ath5k_hw *ah, enum nl80211_iftype op_mode);
1558 int ath5k_hw_get_tx_queueprops(struct ath5k_hw *ah, int queue,
1560 int ath5k_hw_set_tx_queueprops(struct ath5k_hw *ah, int queue,
1562 int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah,
1565 void ath5k_hw_set_tx_retry_limits(struct ath5k_hw *ah,
1567 u32 ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue);
1568 void ath5k_hw_release_tx_queue(struct ath5k_hw *ah, unsigned int queue);
1569 int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue);
1570 int ath5k_hw_set_ifs_intervals(struct ath5k_hw *ah, unsigned int slot_time);
1572 int ath5k_hw_init_queues(struct ath5k_hw *ah);
1575 int ath5k_hw_init_desc_functions(struct ath5k_hw *ah);
1576 int ath5k_hw_setup_rx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
1578 int ath5k_hw_setup_mrr_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
1584 void ath5k_hw_set_ledstate(struct ath5k_hw *ah, unsigned int state);
1585 int ath5k_hw_set_gpio_input(struct ath5k_hw *ah, u32 gpio);
1586 int ath5k_hw_set_gpio_output(struct ath5k_hw *ah, u32 gpio);
1587 u32 ath5k_hw_get_gpio(struct ath5k_hw *ah, u32 gpio);
1588 int ath5k_hw_set_gpio(struct ath5k_hw *ah, u32 gpio, u32 val);
1589 void ath5k_hw_set_gpio_intr(struct ath5k_hw *ah, unsigned int gpio,
1594 void ath5k_rfkill_hw_start(struct ath5k_hw *ah);
1595 void ath5k_rfkill_hw_stop(struct ath5k_hw *ah);
1599 int ath5k_hw_set_capabilities(struct ath5k_hw *ah);
1600 int ath5k_hw_enable_pspoll(struct ath5k_hw *ah, u8 *bssid, u16 assoc_id);
1601 int ath5k_hw_disable_pspoll(struct ath5k_hw *ah);
1605 int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel);
1610 u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, enum nl80211_band band);
1611 int ath5k_hw_phy_disable(struct ath5k_hw *ah);
1613 enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah);
1614 int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah);
1616 bool ath5k_channel_ok(struct ath5k_hw *ah, struct ieee80211_channel *channel);
1618 void ath5k_hw_init_nfcal_hist(struct ath5k_hw *ah);
1619 int ath5k_hw_phy_calibrate(struct ath5k_hw *ah,
1621 void ath5k_hw_update_noise_floor(struct ath5k_hw *ah);
1623 bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah,
1626 void ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode);
1627 void ath5k_hw_set_antenna_switch(struct ath5k_hw *ah, u8 ee_mode);
1629 int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower);
1631 int ath5k_hw_phy_init(struct ath5k_hw *ah, struct ieee80211_channel *channel,
1638 static inline struct ath_common *ath5k_hw_common(struct ath5k_hw *ah) in ath5k_hw_common() argument
1640 return &ah->common; in ath5k_hw_common()
1643 static inline struct ath_regulatory *ath5k_hw_regulatory(struct ath5k_hw *ah) in ath5k_hw_regulatory() argument
1645 return &(ath5k_hw_common(ah)->regulatory); in ath5k_hw_regulatory()
1651 static inline void __iomem *ath5k_ahb_reg(struct ath5k_hw *ah, u16 reg) in ath5k_ahb_reg() argument
1655 if (unlikely((reg >= 0x4000) && (reg < 0x5000) && in ath5k_ahb_reg()
1656 (ah->ah_mac_srev >= AR5K_SREV_AR2315_R6))) in ath5k_ahb_reg()
1657 return AR5K_AR2315_PCI_BASE + reg; in ath5k_ahb_reg()
1659 return ah->iobase + reg; in ath5k_ahb_reg()
1662 static inline u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg) in ath5k_hw_reg_read() argument
1664 return ioread32(ath5k_ahb_reg(ah, reg)); in ath5k_hw_reg_read()
1667 static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg) in ath5k_hw_reg_write() argument
1669 iowrite32(val, ath5k_ahb_reg(ah, reg)); in ath5k_hw_reg_write()
1674 static inline u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg) in ath5k_hw_reg_read() argument
1676 return ioread32(ah->iobase + reg); in ath5k_hw_reg_read()
1679 static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg) in ath5k_hw_reg_write() argument
1681 iowrite32(val, ah->iobase + reg); in ath5k_hw_reg_write()
1686 static inline enum ath_bus_type ath5k_get_bus_type(struct ath5k_hw *ah) in ath5k_get_bus_type() argument
1688 return ath5k_hw_common(ah)->bus_ops->ath_bus_type; in ath5k_get_bus_type()
1693 common->bus_ops->read_cachesize(common, csz); in ath5k_read_cachesize()
1696 static inline bool ath5k_hw_nvram_read(struct ath5k_hw *ah, u32 off, u16 *data) in ath5k_hw_nvram_read() argument
1698 struct ath_common *common = ath5k_hw_common(ah); in ath5k_hw_nvram_read()
1699 return common->bus_ops->eeprom_read(common, off, data); in ath5k_hw_nvram_read()