xref: /linux/drivers/net/wireless/ath/ath12k/reg.c (revision a1ff5a7d78a036d6c2178ee5acd6ba4946243800)
1d8899132SKalle Valo // SPDX-License-Identifier: BSD-3-Clause-Clear
2d8899132SKalle Valo /*
3d8899132SKalle Valo  * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
4b856f023SKarthikeyan Periyasamy  * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
5d8899132SKalle Valo  */
6d8899132SKalle Valo #include <linux/rtnetlink.h>
7d8899132SKalle Valo #include "core.h"
8d8899132SKalle Valo #include "debug.h"
9d8899132SKalle Valo 
10d8899132SKalle Valo /* World regdom to be used in case default regd from fw is unavailable */
11d8899132SKalle Valo #define ATH12K_2GHZ_CH01_11      REG_RULE(2412 - 10, 2462 + 10, 40, 0, 20, 0)
12d8899132SKalle Valo #define ATH12K_5GHZ_5150_5350    REG_RULE(5150 - 10, 5350 + 10, 80, 0, 30,\
13d8899132SKalle Valo 					  NL80211_RRF_NO_IR)
14d8899132SKalle Valo #define ATH12K_5GHZ_5725_5850    REG_RULE(5725 - 10, 5850 + 10, 80, 0, 30,\
15d8899132SKalle Valo 					  NL80211_RRF_NO_IR)
16d8899132SKalle Valo 
17d8899132SKalle Valo #define ETSI_WEATHER_RADAR_BAND_LOW		5590
18d8899132SKalle Valo #define ETSI_WEATHER_RADAR_BAND_HIGH		5650
19d8899132SKalle Valo #define ETSI_WEATHER_RADAR_BAND_CAC_TIMEOUT	600000
20d8899132SKalle Valo 
21d8899132SKalle Valo static const struct ieee80211_regdomain ath12k_world_regd = {
22d8899132SKalle Valo 	.n_reg_rules = 3,
23d8899132SKalle Valo 	.alpha2 = "00",
24d8899132SKalle Valo 	.reg_rules = {
25d8899132SKalle Valo 		ATH12K_2GHZ_CH01_11,
26d8899132SKalle Valo 		ATH12K_5GHZ_5150_5350,
27d8899132SKalle Valo 		ATH12K_5GHZ_5725_5850,
28d8899132SKalle Valo 	}
29d8899132SKalle Valo };
30d8899132SKalle Valo 
ath12k_regdom_changes(struct ieee80211_hw * hw,char * alpha2)31842addaeSKarthikeyan Periyasamy static bool ath12k_regdom_changes(struct ieee80211_hw *hw, char *alpha2)
32d8899132SKalle Valo {
33d8899132SKalle Valo 	const struct ieee80211_regdomain *regd;
34d8899132SKalle Valo 
35842addaeSKarthikeyan Periyasamy 	regd = rcu_dereference_rtnl(hw->wiphy->regd);
36d8899132SKalle Valo 	/* This can happen during wiphy registration where the previous
37d8899132SKalle Valo 	 * user request is received before we update the regd received
38d8899132SKalle Valo 	 * from firmware.
39d8899132SKalle Valo 	 */
40d8899132SKalle Valo 	if (!regd)
41d8899132SKalle Valo 		return true;
42d8899132SKalle Valo 
43d8899132SKalle Valo 	return memcmp(regd->alpha2, alpha2, 2) != 0;
44d8899132SKalle Valo }
45d8899132SKalle Valo 
46d8899132SKalle Valo static void
ath12k_reg_notifier(struct wiphy * wiphy,struct regulatory_request * request)47d8899132SKalle Valo ath12k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
48d8899132SKalle Valo {
49d8899132SKalle Valo 	struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
50d8899132SKalle Valo 	struct ath12k_wmi_init_country_arg arg;
516db6e70aSKarthikeyan Periyasamy 	struct ath12k_hw *ah = ath12k_hw_to_ah(hw);
52ba12f08fSKarthikeyan Periyasamy 	struct ath12k *ar = ath12k_ah_to_ar(ah, 0);
530da00e45SSriram R 	int ret, i;
54d8899132SKalle Valo 
55d8899132SKalle Valo 	ath12k_dbg(ar->ab, ATH12K_DBG_REG,
56d8899132SKalle Valo 		   "Regulatory Notification received for %s\n", wiphy_name(wiphy));
57d8899132SKalle Valo 
58d8899132SKalle Valo 	/* Currently supporting only General User Hints. Cell base user
59d8899132SKalle Valo 	 * hints to be handled later.
60d8899132SKalle Valo 	 * Hints from other sources like Core, Beacons are not expected for
61d8899132SKalle Valo 	 * self managed wiphy's
62d8899132SKalle Valo 	 */
63d8899132SKalle Valo 	if (!(request->initiator == NL80211_REGDOM_SET_BY_USER &&
64d8899132SKalle Valo 	      request->user_reg_hint_type == NL80211_USER_REG_HINT_USER)) {
65d8899132SKalle Valo 		ath12k_warn(ar->ab, "Unexpected Regulatory event for this wiphy\n");
66d8899132SKalle Valo 		return;
67d8899132SKalle Valo 	}
68d8899132SKalle Valo 
69d8899132SKalle Valo 	if (!IS_ENABLED(CONFIG_ATH_REG_DYNAMIC_USER_REG_HINTS)) {
70d8899132SKalle Valo 		ath12k_dbg(ar->ab, ATH12K_DBG_REG,
71d8899132SKalle Valo 			   "Country Setting is not allowed\n");
72d8899132SKalle Valo 		return;
73d8899132SKalle Valo 	}
74d8899132SKalle Valo 
75842addaeSKarthikeyan Periyasamy 	if (!ath12k_regdom_changes(hw, request->alpha2)) {
76d8899132SKalle Valo 		ath12k_dbg(ar->ab, ATH12K_DBG_REG, "Country is already set\n");
77d8899132SKalle Valo 		return;
78d8899132SKalle Valo 	}
79d8899132SKalle Valo 
80d8899132SKalle Valo 	/* Set the country code to the firmware and wait for
81d8899132SKalle Valo 	 * the WMI_REG_CHAN_LIST_CC EVENT for updating the
82d8899132SKalle Valo 	 * reg info
83d8899132SKalle Valo 	 */
84d8899132SKalle Valo 	arg.flags = ALPHA_IS_SET;
85d8899132SKalle Valo 	memcpy(&arg.cc_info.alpha2, request->alpha2, 2);
86d8899132SKalle Valo 	arg.cc_info.alpha2[2] = 0;
87d8899132SKalle Valo 
880da00e45SSriram R 	/* Allow fresh updates to wiphy regd */
890da00e45SSriram R 	ah->regd_updated = false;
900da00e45SSriram R 
910da00e45SSriram R 	/* Send the reg change request to all the radios */
920da00e45SSriram R 	for_each_ar(ah, ar, i) {
93d8899132SKalle Valo 		ret = ath12k_wmi_send_init_country_cmd(ar, &arg);
94d8899132SKalle Valo 		if (ret)
95d8899132SKalle Valo 			ath12k_warn(ar->ab,
96d8899132SKalle Valo 				    "INIT Country code set to fw failed : %d\n", ret);
97d8899132SKalle Valo 	}
980da00e45SSriram R }
99d8899132SKalle Valo 
ath12k_reg_update_chan_list(struct ath12k * ar)100d8899132SKalle Valo int ath12k_reg_update_chan_list(struct ath12k *ar)
101d8899132SKalle Valo {
102d8899132SKalle Valo 	struct ieee80211_supported_band **bands;
103d8899132SKalle Valo 	struct ath12k_wmi_scan_chan_list_arg *arg;
104d8899132SKalle Valo 	struct ieee80211_channel *channel;
105b856f023SKarthikeyan Periyasamy 	struct ieee80211_hw *hw = ath12k_ar_to_hw(ar);
106d8899132SKalle Valo 	struct ath12k_wmi_channel_arg *ch;
107d8899132SKalle Valo 	enum nl80211_band band;
108d8899132SKalle Valo 	int num_channels = 0;
109d8899132SKalle Valo 	int i, ret;
110d8899132SKalle Valo 
111d8899132SKalle Valo 	bands = hw->wiphy->bands;
112d8899132SKalle Valo 	for (band = 0; band < NUM_NL80211_BANDS; band++) {
11367a48d93SSriram R 		if (!(ar->mac.sbands[band].channels && bands[band]))
114d8899132SKalle Valo 			continue;
115d8899132SKalle Valo 
116d8899132SKalle Valo 		for (i = 0; i < bands[band]->n_channels; i++) {
117d8899132SKalle Valo 			if (bands[band]->channels[i].flags &
118d8899132SKalle Valo 			    IEEE80211_CHAN_DISABLED)
119d8899132SKalle Valo 				continue;
120d8899132SKalle Valo 
121d8899132SKalle Valo 			num_channels++;
122d8899132SKalle Valo 		}
123d8899132SKalle Valo 	}
124d8899132SKalle Valo 
125d8899132SKalle Valo 	if (WARN_ON(!num_channels))
126d8899132SKalle Valo 		return -EINVAL;
127d8899132SKalle Valo 
128d8899132SKalle Valo 	arg = kzalloc(struct_size(arg, channel, num_channels), GFP_KERNEL);
129d8899132SKalle Valo 
130d8899132SKalle Valo 	if (!arg)
131d8899132SKalle Valo 		return -ENOMEM;
132d8899132SKalle Valo 
133d8899132SKalle Valo 	arg->pdev_id = ar->pdev->pdev_id;
134d8899132SKalle Valo 	arg->nallchans = num_channels;
135d8899132SKalle Valo 
136d8899132SKalle Valo 	ch = arg->channel;
137d8899132SKalle Valo 
138d8899132SKalle Valo 	for (band = 0; band < NUM_NL80211_BANDS; band++) {
13967a48d93SSriram R 		if (!(ar->mac.sbands[band].channels && bands[band]))
140d8899132SKalle Valo 			continue;
141d8899132SKalle Valo 
142d8899132SKalle Valo 		for (i = 0; i < bands[band]->n_channels; i++) {
143d8899132SKalle Valo 			channel = &bands[band]->channels[i];
144d8899132SKalle Valo 
145d8899132SKalle Valo 			if (channel->flags & IEEE80211_CHAN_DISABLED)
146d8899132SKalle Valo 				continue;
147d8899132SKalle Valo 
148d8899132SKalle Valo 			/* TODO: Set to true/false based on some condition? */
149d8899132SKalle Valo 			ch->allow_ht = true;
150d8899132SKalle Valo 			ch->allow_vht = true;
151d8899132SKalle Valo 			ch->allow_he = true;
152d8899132SKalle Valo 
153d8899132SKalle Valo 			ch->dfs_set =
154d8899132SKalle Valo 				!!(channel->flags & IEEE80211_CHAN_RADAR);
155d8899132SKalle Valo 			ch->is_chan_passive = !!(channel->flags &
156d8899132SKalle Valo 						IEEE80211_CHAN_NO_IR);
157d8899132SKalle Valo 			ch->is_chan_passive |= ch->dfs_set;
158d8899132SKalle Valo 			ch->mhz = channel->center_freq;
159d8899132SKalle Valo 			ch->cfreq1 = channel->center_freq;
160d8899132SKalle Valo 			ch->minpower = 0;
161d8899132SKalle Valo 			ch->maxpower = channel->max_power * 2;
162d8899132SKalle Valo 			ch->maxregpower = channel->max_reg_power * 2;
163d8899132SKalle Valo 			ch->antennamax = channel->max_antenna_gain * 2;
164d8899132SKalle Valo 
165d8899132SKalle Valo 			/* TODO: Use appropriate phymodes */
166d8899132SKalle Valo 			if (channel->band == NL80211_BAND_2GHZ)
167d8899132SKalle Valo 				ch->phy_mode = MODE_11G;
168d8899132SKalle Valo 			else
169d8899132SKalle Valo 				ch->phy_mode = MODE_11A;
170d8899132SKalle Valo 
171d8899132SKalle Valo 			if (channel->band == NL80211_BAND_6GHZ &&
172d8899132SKalle Valo 			    cfg80211_channel_is_psc(channel))
173d8899132SKalle Valo 				ch->psc_channel = true;
174d8899132SKalle Valo 
175d8899132SKalle Valo 			ath12k_dbg(ar->ab, ATH12K_DBG_WMI,
176d8899132SKalle Valo 				   "mac channel [%d/%d] freq %d maxpower %d regpower %d antenna %d mode %d\n",
177d8899132SKalle Valo 				   i, arg->nallchans,
178d8899132SKalle Valo 				   ch->mhz, ch->maxpower, ch->maxregpower,
179d8899132SKalle Valo 				   ch->antennamax, ch->phy_mode);
180d8899132SKalle Valo 
181d8899132SKalle Valo 			ch++;
182d8899132SKalle Valo 			/* TODO: use quarrter/half rate, cfreq12, dfs_cfreq2
183d8899132SKalle Valo 			 * set_agile, reg_class_idx
184d8899132SKalle Valo 			 */
185d8899132SKalle Valo 		}
186d8899132SKalle Valo 	}
187d8899132SKalle Valo 
188d8899132SKalle Valo 	ret = ath12k_wmi_send_scan_chan_list_cmd(ar, arg);
189d8899132SKalle Valo 	kfree(arg);
190d8899132SKalle Valo 
191d8899132SKalle Valo 	return ret;
192d8899132SKalle Valo }
193d8899132SKalle Valo 
ath12k_copy_regd(struct ieee80211_regdomain * regd_orig,struct ieee80211_regdomain * regd_copy)194d8899132SKalle Valo static void ath12k_copy_regd(struct ieee80211_regdomain *regd_orig,
195d8899132SKalle Valo 			     struct ieee80211_regdomain *regd_copy)
196d8899132SKalle Valo {
197d8899132SKalle Valo 	u8 i;
198d8899132SKalle Valo 
199d8899132SKalle Valo 	/* The caller should have checked error conditions */
200d8899132SKalle Valo 	memcpy(regd_copy, regd_orig, sizeof(*regd_orig));
201d8899132SKalle Valo 
202d8899132SKalle Valo 	for (i = 0; i < regd_orig->n_reg_rules; i++)
203d8899132SKalle Valo 		memcpy(&regd_copy->reg_rules[i], &regd_orig->reg_rules[i],
204d8899132SKalle Valo 		       sizeof(struct ieee80211_reg_rule));
205d8899132SKalle Valo }
206d8899132SKalle Valo 
ath12k_regd_update(struct ath12k * ar,bool init)207d8899132SKalle Valo int ath12k_regd_update(struct ath12k *ar, bool init)
208d8899132SKalle Valo {
209*9b4e5caaSKarthikeyan Periyasamy 	struct ath12k_hw *ah = ath12k_ar_to_ah(ar);
210*9b4e5caaSKarthikeyan Periyasamy 	struct ieee80211_hw *hw = ah->hw;
211d8899132SKalle Valo 	struct ieee80211_regdomain *regd, *regd_copy = NULL;
212d8899132SKalle Valo 	int ret, regd_len, pdev_id;
213d8899132SKalle Valo 	struct ath12k_base *ab;
2140da00e45SSriram R 	int i;
215d8899132SKalle Valo 
216d8899132SKalle Valo 	ab = ar->ab;
2170da00e45SSriram R 
2180da00e45SSriram R 	/* If one of the radios within ah has already updated the regd for
2190da00e45SSriram R 	 * the wiphy, then avoid setting regd again
2200da00e45SSriram R 	 */
2210da00e45SSriram R 	if (ah->regd_updated)
2220da00e45SSriram R 		return 0;
2230da00e45SSriram R 
2240da00e45SSriram R 	/* firmware provides reg rules which are similar for 2 GHz and 5 GHz
2250da00e45SSriram R 	 * pdev but 6 GHz pdev has superset of all rules including rules for
2260da00e45SSriram R 	 * all bands, we prefer 6 GHz pdev's rules to be used for setup of
2270da00e45SSriram R 	 * the wiphy regd.
2280da00e45SSriram R 	 * If 6 GHz pdev was part of the ath12k_hw, wait for the 6 GHz pdev,
2290da00e45SSriram R 	 * else pick the first pdev which calls this function and use its
2300da00e45SSriram R 	 * regd to update global hw regd.
2310da00e45SSriram R 	 * The regd_updated flag set at the end will not allow any further
2320da00e45SSriram R 	 * updates.
2330da00e45SSriram R 	 */
2340da00e45SSriram R 	if (ah->use_6ghz_regd && !ar->supports_6ghz)
2350da00e45SSriram R 		return 0;
2360da00e45SSriram R 
237d8899132SKalle Valo 	pdev_id = ar->pdev_idx;
238d8899132SKalle Valo 
239d8899132SKalle Valo 	spin_lock_bh(&ab->base_lock);
240d8899132SKalle Valo 
241d8899132SKalle Valo 	if (init) {
242d8899132SKalle Valo 		/* Apply the regd received during init through
243d8899132SKalle Valo 		 * WMI_REG_CHAN_LIST_CC event. In case of failure to
244d8899132SKalle Valo 		 * receive the regd, initialize with a default world
245d8899132SKalle Valo 		 * regulatory.
246d8899132SKalle Valo 		 */
247d8899132SKalle Valo 		if (ab->default_regd[pdev_id]) {
248d8899132SKalle Valo 			regd = ab->default_regd[pdev_id];
249d8899132SKalle Valo 		} else {
250d8899132SKalle Valo 			ath12k_warn(ab,
251d8899132SKalle Valo 				    "failed to receive default regd during init\n");
252d8899132SKalle Valo 			regd = (struct ieee80211_regdomain *)&ath12k_world_regd;
253d8899132SKalle Valo 		}
254d8899132SKalle Valo 	} else {
255d8899132SKalle Valo 		regd = ab->new_regd[pdev_id];
256d8899132SKalle Valo 	}
257d8899132SKalle Valo 
258d8899132SKalle Valo 	if (!regd) {
259d8899132SKalle Valo 		ret = -EINVAL;
260d8899132SKalle Valo 		spin_unlock_bh(&ab->base_lock);
261d8899132SKalle Valo 		goto err;
262d8899132SKalle Valo 	}
263d8899132SKalle Valo 
264d8899132SKalle Valo 	regd_len = sizeof(*regd) + (regd->n_reg_rules *
265d8899132SKalle Valo 		sizeof(struct ieee80211_reg_rule));
266d8899132SKalle Valo 
267d8899132SKalle Valo 	regd_copy = kzalloc(regd_len, GFP_ATOMIC);
268d8899132SKalle Valo 	if (regd_copy)
269d8899132SKalle Valo 		ath12k_copy_regd(regd, regd_copy);
270d8899132SKalle Valo 
271d8899132SKalle Valo 	spin_unlock_bh(&ab->base_lock);
272d8899132SKalle Valo 
273d8899132SKalle Valo 	if (!regd_copy) {
274d8899132SKalle Valo 		ret = -ENOMEM;
275d8899132SKalle Valo 		goto err;
276d8899132SKalle Valo 	}
277d8899132SKalle Valo 
278d8899132SKalle Valo 	rtnl_lock();
279940b57fdSKarthikeyan Periyasamy 	wiphy_lock(hw->wiphy);
280940b57fdSKarthikeyan Periyasamy 	ret = regulatory_set_wiphy_regd_sync(hw->wiphy, regd_copy);
281940b57fdSKarthikeyan Periyasamy 	wiphy_unlock(hw->wiphy);
282d8899132SKalle Valo 	rtnl_unlock();
283d8899132SKalle Valo 
284d8899132SKalle Valo 	kfree(regd_copy);
285d8899132SKalle Valo 
286d8899132SKalle Valo 	if (ret)
287d8899132SKalle Valo 		goto err;
288d8899132SKalle Valo 
289*9b4e5caaSKarthikeyan Periyasamy 	if (ah->state != ATH12K_HW_STATE_ON)
290*9b4e5caaSKarthikeyan Periyasamy 		goto skip;
291*9b4e5caaSKarthikeyan Periyasamy 
2920da00e45SSriram R 	ah->regd_updated = true;
2930da00e45SSriram R 	/* Apply the new regd to all the radios, this is expected to be received only once
2940da00e45SSriram R 	 * since we check for ah->regd_updated and allow here only once.
2950da00e45SSriram R 	 */
2960da00e45SSriram R 	for_each_ar(ah, ar, i) {
2970da00e45SSriram R 		ab = ar->ab;
298d8899132SKalle Valo 		ret = ath12k_reg_update_chan_list(ar);
299d8899132SKalle Valo 		if (ret)
300d8899132SKalle Valo 			goto err;
301d8899132SKalle Valo 	}
302*9b4e5caaSKarthikeyan Periyasamy skip:
303d8899132SKalle Valo 	return 0;
304d8899132SKalle Valo err:
305d8899132SKalle Valo 	ath12k_warn(ab, "failed to perform regd update : %d\n", ret);
306d8899132SKalle Valo 	return ret;
307d8899132SKalle Valo }
308d8899132SKalle Valo 
309d8899132SKalle Valo static enum nl80211_dfs_regions
ath12k_map_fw_dfs_region(enum ath12k_dfs_region dfs_region)310d8899132SKalle Valo ath12k_map_fw_dfs_region(enum ath12k_dfs_region dfs_region)
311d8899132SKalle Valo {
312d8899132SKalle Valo 	switch (dfs_region) {
313d8899132SKalle Valo 	case ATH12K_DFS_REG_FCC:
314d8899132SKalle Valo 	case ATH12K_DFS_REG_CN:
315d8899132SKalle Valo 		return NL80211_DFS_FCC;
316d8899132SKalle Valo 	case ATH12K_DFS_REG_ETSI:
317d8899132SKalle Valo 	case ATH12K_DFS_REG_KR:
318d8899132SKalle Valo 		return NL80211_DFS_ETSI;
319d8899132SKalle Valo 	case ATH12K_DFS_REG_MKK:
320d8899132SKalle Valo 	case ATH12K_DFS_REG_MKK_N:
321d8899132SKalle Valo 		return NL80211_DFS_JP;
322d8899132SKalle Valo 	default:
323d8899132SKalle Valo 		return NL80211_DFS_UNSET;
324d8899132SKalle Valo 	}
325d8899132SKalle Valo }
326d8899132SKalle Valo 
ath12k_map_fw_reg_flags(u16 reg_flags)327d8899132SKalle Valo static u32 ath12k_map_fw_reg_flags(u16 reg_flags)
328d8899132SKalle Valo {
329d8899132SKalle Valo 	u32 flags = 0;
330d8899132SKalle Valo 
331d8899132SKalle Valo 	if (reg_flags & REGULATORY_CHAN_NO_IR)
332d8899132SKalle Valo 		flags = NL80211_RRF_NO_IR;
333d8899132SKalle Valo 
334d8899132SKalle Valo 	if (reg_flags & REGULATORY_CHAN_RADAR)
335d8899132SKalle Valo 		flags |= NL80211_RRF_DFS;
336d8899132SKalle Valo 
337d8899132SKalle Valo 	if (reg_flags & REGULATORY_CHAN_NO_OFDM)
338d8899132SKalle Valo 		flags |= NL80211_RRF_NO_OFDM;
339d8899132SKalle Valo 
340d8899132SKalle Valo 	if (reg_flags & REGULATORY_CHAN_INDOOR_ONLY)
341d8899132SKalle Valo 		flags |= NL80211_RRF_NO_OUTDOOR;
342d8899132SKalle Valo 
343d8899132SKalle Valo 	if (reg_flags & REGULATORY_CHAN_NO_HT40)
344d8899132SKalle Valo 		flags |= NL80211_RRF_NO_HT40;
345d8899132SKalle Valo 
346d8899132SKalle Valo 	if (reg_flags & REGULATORY_CHAN_NO_80MHZ)
347d8899132SKalle Valo 		flags |= NL80211_RRF_NO_80MHZ;
348d8899132SKalle Valo 
349d8899132SKalle Valo 	if (reg_flags & REGULATORY_CHAN_NO_160MHZ)
350d8899132SKalle Valo 		flags |= NL80211_RRF_NO_160MHZ;
351d8899132SKalle Valo 
352d8899132SKalle Valo 	return flags;
353d8899132SKalle Valo }
354d8899132SKalle Valo 
ath12k_map_fw_phy_flags(u32 phy_flags)35529ea0d40SAditya Kumar Singh static u32 ath12k_map_fw_phy_flags(u32 phy_flags)
35629ea0d40SAditya Kumar Singh {
35729ea0d40SAditya Kumar Singh 	u32 flags = 0;
35829ea0d40SAditya Kumar Singh 
35929ea0d40SAditya Kumar Singh 	if (phy_flags & ATH12K_REG_PHY_BITMAP_NO11AX)
36029ea0d40SAditya Kumar Singh 		flags |= NL80211_RRF_NO_HE;
36129ea0d40SAditya Kumar Singh 
36229ea0d40SAditya Kumar Singh 	if (phy_flags & ATH12K_REG_PHY_BITMAP_NO11BE)
36329ea0d40SAditya Kumar Singh 		flags |= NL80211_RRF_NO_EHT;
36429ea0d40SAditya Kumar Singh 
36529ea0d40SAditya Kumar Singh 	return flags;
36629ea0d40SAditya Kumar Singh }
36729ea0d40SAditya Kumar Singh 
368d8899132SKalle Valo static bool
ath12k_reg_can_intersect(struct ieee80211_reg_rule * rule1,struct ieee80211_reg_rule * rule2)369d8899132SKalle Valo ath12k_reg_can_intersect(struct ieee80211_reg_rule *rule1,
370d8899132SKalle Valo 			 struct ieee80211_reg_rule *rule2)
371d8899132SKalle Valo {
372d8899132SKalle Valo 	u32 start_freq1, end_freq1;
373d8899132SKalle Valo 	u32 start_freq2, end_freq2;
374d8899132SKalle Valo 
375d8899132SKalle Valo 	start_freq1 = rule1->freq_range.start_freq_khz;
376d8899132SKalle Valo 	start_freq2 = rule2->freq_range.start_freq_khz;
377d8899132SKalle Valo 
378d8899132SKalle Valo 	end_freq1 = rule1->freq_range.end_freq_khz;
379d8899132SKalle Valo 	end_freq2 = rule2->freq_range.end_freq_khz;
380d8899132SKalle Valo 
381d8899132SKalle Valo 	if ((start_freq1 >= start_freq2 &&
382d8899132SKalle Valo 	     start_freq1 < end_freq2) ||
383d8899132SKalle Valo 	    (start_freq2 > start_freq1 &&
384d8899132SKalle Valo 	     start_freq2 < end_freq1))
385d8899132SKalle Valo 		return true;
386d8899132SKalle Valo 
387d8899132SKalle Valo 	/* TODO: Should we restrict intersection feasibility
388d8899132SKalle Valo 	 *  based on min bandwidth of the intersected region also,
389d8899132SKalle Valo 	 *  say the intersected rule should have a  min bandwidth
390d8899132SKalle Valo 	 * of 20MHz?
391d8899132SKalle Valo 	 */
392d8899132SKalle Valo 
393d8899132SKalle Valo 	return false;
394d8899132SKalle Valo }
395d8899132SKalle Valo 
ath12k_reg_intersect_rules(struct ieee80211_reg_rule * rule1,struct ieee80211_reg_rule * rule2,struct ieee80211_reg_rule * new_rule)396d8899132SKalle Valo static void ath12k_reg_intersect_rules(struct ieee80211_reg_rule *rule1,
397d8899132SKalle Valo 				       struct ieee80211_reg_rule *rule2,
398d8899132SKalle Valo 				       struct ieee80211_reg_rule *new_rule)
399d8899132SKalle Valo {
400d8899132SKalle Valo 	u32 start_freq1, end_freq1;
401d8899132SKalle Valo 	u32 start_freq2, end_freq2;
402d8899132SKalle Valo 	u32 freq_diff, max_bw;
403d8899132SKalle Valo 
404d8899132SKalle Valo 	start_freq1 = rule1->freq_range.start_freq_khz;
405d8899132SKalle Valo 	start_freq2 = rule2->freq_range.start_freq_khz;
406d8899132SKalle Valo 
407d8899132SKalle Valo 	end_freq1 = rule1->freq_range.end_freq_khz;
408d8899132SKalle Valo 	end_freq2 = rule2->freq_range.end_freq_khz;
409d8899132SKalle Valo 
410d8899132SKalle Valo 	new_rule->freq_range.start_freq_khz = max_t(u32, start_freq1,
411d8899132SKalle Valo 						    start_freq2);
412d8899132SKalle Valo 	new_rule->freq_range.end_freq_khz = min_t(u32, end_freq1, end_freq2);
413d8899132SKalle Valo 
414d8899132SKalle Valo 	freq_diff = new_rule->freq_range.end_freq_khz -
415d8899132SKalle Valo 			new_rule->freq_range.start_freq_khz;
416d8899132SKalle Valo 	max_bw = min_t(u32, rule1->freq_range.max_bandwidth_khz,
417d8899132SKalle Valo 		       rule2->freq_range.max_bandwidth_khz);
418d8899132SKalle Valo 	new_rule->freq_range.max_bandwidth_khz = min_t(u32, max_bw, freq_diff);
419d8899132SKalle Valo 
420d8899132SKalle Valo 	new_rule->power_rule.max_antenna_gain =
421d8899132SKalle Valo 		min_t(u32, rule1->power_rule.max_antenna_gain,
422d8899132SKalle Valo 		      rule2->power_rule.max_antenna_gain);
423d8899132SKalle Valo 
424d8899132SKalle Valo 	new_rule->power_rule.max_eirp = min_t(u32, rule1->power_rule.max_eirp,
425d8899132SKalle Valo 					      rule2->power_rule.max_eirp);
426d8899132SKalle Valo 
427d8899132SKalle Valo 	/* Use the flags of both the rules */
428d8899132SKalle Valo 	new_rule->flags = rule1->flags | rule2->flags;
429d8899132SKalle Valo 
430d8899132SKalle Valo 	/* To be safe, lts use the max cac timeout of both rules */
431d8899132SKalle Valo 	new_rule->dfs_cac_ms = max_t(u32, rule1->dfs_cac_ms,
432d8899132SKalle Valo 				     rule2->dfs_cac_ms);
433d8899132SKalle Valo }
434d8899132SKalle Valo 
435d8899132SKalle Valo static struct ieee80211_regdomain *
ath12k_regd_intersect(struct ieee80211_regdomain * default_regd,struct ieee80211_regdomain * curr_regd)436d8899132SKalle Valo ath12k_regd_intersect(struct ieee80211_regdomain *default_regd,
437d8899132SKalle Valo 		      struct ieee80211_regdomain *curr_regd)
438d8899132SKalle Valo {
439d8899132SKalle Valo 	u8 num_old_regd_rules, num_curr_regd_rules, num_new_regd_rules;
440d8899132SKalle Valo 	struct ieee80211_reg_rule *old_rule, *curr_rule, *new_rule;
441d8899132SKalle Valo 	struct ieee80211_regdomain *new_regd = NULL;
442d8899132SKalle Valo 	u8 i, j, k;
443d8899132SKalle Valo 
444d8899132SKalle Valo 	num_old_regd_rules = default_regd->n_reg_rules;
445d8899132SKalle Valo 	num_curr_regd_rules = curr_regd->n_reg_rules;
446d8899132SKalle Valo 	num_new_regd_rules = 0;
447d8899132SKalle Valo 
448d8899132SKalle Valo 	/* Find the number of intersecting rules to allocate new regd memory */
449d8899132SKalle Valo 	for (i = 0; i < num_old_regd_rules; i++) {
450d8899132SKalle Valo 		old_rule = default_regd->reg_rules + i;
451d8899132SKalle Valo 		for (j = 0; j < num_curr_regd_rules; j++) {
452d8899132SKalle Valo 			curr_rule = curr_regd->reg_rules + j;
453d8899132SKalle Valo 
454d8899132SKalle Valo 			if (ath12k_reg_can_intersect(old_rule, curr_rule))
455d8899132SKalle Valo 				num_new_regd_rules++;
456d8899132SKalle Valo 		}
457d8899132SKalle Valo 	}
458d8899132SKalle Valo 
459d8899132SKalle Valo 	if (!num_new_regd_rules)
460d8899132SKalle Valo 		return NULL;
461d8899132SKalle Valo 
462d8899132SKalle Valo 	new_regd = kzalloc(sizeof(*new_regd) + (num_new_regd_rules *
463d8899132SKalle Valo 			sizeof(struct ieee80211_reg_rule)),
464d8899132SKalle Valo 			GFP_ATOMIC);
465d8899132SKalle Valo 
466d8899132SKalle Valo 	if (!new_regd)
467d8899132SKalle Valo 		return NULL;
468d8899132SKalle Valo 
469d8899132SKalle Valo 	/* We set the new country and dfs region directly and only trim
470d8899132SKalle Valo 	 * the freq, power, antenna gain by intersecting with the
471d8899132SKalle Valo 	 * default regdomain. Also MAX of the dfs cac timeout is selected.
472d8899132SKalle Valo 	 */
473d8899132SKalle Valo 	new_regd->n_reg_rules = num_new_regd_rules;
474d8899132SKalle Valo 	memcpy(new_regd->alpha2, curr_regd->alpha2, sizeof(new_regd->alpha2));
475d8899132SKalle Valo 	new_regd->dfs_region = curr_regd->dfs_region;
476d8899132SKalle Valo 	new_rule = new_regd->reg_rules;
477d8899132SKalle Valo 
478d8899132SKalle Valo 	for (i = 0, k = 0; i < num_old_regd_rules; i++) {
479d8899132SKalle Valo 		old_rule = default_regd->reg_rules + i;
480d8899132SKalle Valo 		for (j = 0; j < num_curr_regd_rules; j++) {
481d8899132SKalle Valo 			curr_rule = curr_regd->reg_rules + j;
482d8899132SKalle Valo 
483d8899132SKalle Valo 			if (ath12k_reg_can_intersect(old_rule, curr_rule))
484d8899132SKalle Valo 				ath12k_reg_intersect_rules(old_rule, curr_rule,
485d8899132SKalle Valo 							   (new_rule + k++));
486d8899132SKalle Valo 		}
487d8899132SKalle Valo 	}
488d8899132SKalle Valo 	return new_regd;
489d8899132SKalle Valo }
490d8899132SKalle Valo 
491d8899132SKalle Valo static const char *
ath12k_reg_get_regdom_str(enum nl80211_dfs_regions dfs_region)492d8899132SKalle Valo ath12k_reg_get_regdom_str(enum nl80211_dfs_regions dfs_region)
493d8899132SKalle Valo {
494d8899132SKalle Valo 	switch (dfs_region) {
495d8899132SKalle Valo 	case NL80211_DFS_FCC:
496d8899132SKalle Valo 		return "FCC";
497d8899132SKalle Valo 	case NL80211_DFS_ETSI:
498d8899132SKalle Valo 		return "ETSI";
499d8899132SKalle Valo 	case NL80211_DFS_JP:
500d8899132SKalle Valo 		return "JP";
501d8899132SKalle Valo 	default:
502d8899132SKalle Valo 		return "UNSET";
503d8899132SKalle Valo 	}
504d8899132SKalle Valo }
505d8899132SKalle Valo 
506d8899132SKalle Valo static u16
ath12k_reg_adjust_bw(u16 start_freq,u16 end_freq,u16 max_bw)507d8899132SKalle Valo ath12k_reg_adjust_bw(u16 start_freq, u16 end_freq, u16 max_bw)
508d8899132SKalle Valo {
509d8899132SKalle Valo 	u16 bw;
510d8899132SKalle Valo 
511d8899132SKalle Valo 	bw = end_freq - start_freq;
512d8899132SKalle Valo 	bw = min_t(u16, bw, max_bw);
513d8899132SKalle Valo 
514d8899132SKalle Valo 	if (bw >= 80 && bw < 160)
515d8899132SKalle Valo 		bw = 80;
516d8899132SKalle Valo 	else if (bw >= 40 && bw < 80)
517d8899132SKalle Valo 		bw = 40;
518d8899132SKalle Valo 	else if (bw < 40)
519d8899132SKalle Valo 		bw = 20;
520d8899132SKalle Valo 
521d8899132SKalle Valo 	return bw;
522d8899132SKalle Valo }
523d8899132SKalle Valo 
524d8899132SKalle Valo static void
ath12k_reg_update_rule(struct ieee80211_reg_rule * reg_rule,u32 start_freq,u32 end_freq,u32 bw,u32 ant_gain,u32 reg_pwr,u32 reg_flags)525d8899132SKalle Valo ath12k_reg_update_rule(struct ieee80211_reg_rule *reg_rule, u32 start_freq,
526d8899132SKalle Valo 		       u32 end_freq, u32 bw, u32 ant_gain, u32 reg_pwr,
527d8899132SKalle Valo 		       u32 reg_flags)
528d8899132SKalle Valo {
529d8899132SKalle Valo 	reg_rule->freq_range.start_freq_khz = MHZ_TO_KHZ(start_freq);
530d8899132SKalle Valo 	reg_rule->freq_range.end_freq_khz = MHZ_TO_KHZ(end_freq);
531d8899132SKalle Valo 	reg_rule->freq_range.max_bandwidth_khz = MHZ_TO_KHZ(bw);
532d8899132SKalle Valo 	reg_rule->power_rule.max_antenna_gain = DBI_TO_MBI(ant_gain);
533d8899132SKalle Valo 	reg_rule->power_rule.max_eirp = DBM_TO_MBM(reg_pwr);
534d8899132SKalle Valo 	reg_rule->flags = reg_flags;
535d8899132SKalle Valo }
536d8899132SKalle Valo 
537d8899132SKalle Valo static void
ath12k_reg_update_weather_radar_band(struct ath12k_base * ab,struct ieee80211_regdomain * regd,struct ath12k_reg_rule * reg_rule,u8 * rule_idx,u32 flags,u16 max_bw)538d8899132SKalle Valo ath12k_reg_update_weather_radar_band(struct ath12k_base *ab,
539d8899132SKalle Valo 				     struct ieee80211_regdomain *regd,
540d8899132SKalle Valo 				     struct ath12k_reg_rule *reg_rule,
541d8899132SKalle Valo 				     u8 *rule_idx, u32 flags, u16 max_bw)
542d8899132SKalle Valo {
543d8899132SKalle Valo 	u32 end_freq;
544d8899132SKalle Valo 	u16 bw;
545d8899132SKalle Valo 	u8 i;
546d8899132SKalle Valo 
547d8899132SKalle Valo 	i = *rule_idx;
548d8899132SKalle Valo 
549d8899132SKalle Valo 	bw = ath12k_reg_adjust_bw(reg_rule->start_freq,
550d8899132SKalle Valo 				  ETSI_WEATHER_RADAR_BAND_LOW, max_bw);
551d8899132SKalle Valo 
552d8899132SKalle Valo 	ath12k_reg_update_rule(regd->reg_rules + i, reg_rule->start_freq,
553d8899132SKalle Valo 			       ETSI_WEATHER_RADAR_BAND_LOW, bw,
554d8899132SKalle Valo 			       reg_rule->ant_gain, reg_rule->reg_power,
555d8899132SKalle Valo 			       flags);
556d8899132SKalle Valo 
557d8899132SKalle Valo 	ath12k_dbg(ab, ATH12K_DBG_REG,
558d8899132SKalle Valo 		   "\t%d. (%d - %d @ %d) (%d, %d) (%d ms) (FLAGS %d)\n",
559d8899132SKalle Valo 		   i + 1, reg_rule->start_freq, ETSI_WEATHER_RADAR_BAND_LOW,
560d8899132SKalle Valo 		   bw, reg_rule->ant_gain, reg_rule->reg_power,
561d8899132SKalle Valo 		   regd->reg_rules[i].dfs_cac_ms,
562d8899132SKalle Valo 		   flags);
563d8899132SKalle Valo 
564d8899132SKalle Valo 	if (reg_rule->end_freq > ETSI_WEATHER_RADAR_BAND_HIGH)
565d8899132SKalle Valo 		end_freq = ETSI_WEATHER_RADAR_BAND_HIGH;
566d8899132SKalle Valo 	else
567d8899132SKalle Valo 		end_freq = reg_rule->end_freq;
568d8899132SKalle Valo 
569d8899132SKalle Valo 	bw = ath12k_reg_adjust_bw(ETSI_WEATHER_RADAR_BAND_LOW, end_freq,
570d8899132SKalle Valo 				  max_bw);
571d8899132SKalle Valo 
572d8899132SKalle Valo 	i++;
573d8899132SKalle Valo 
574d8899132SKalle Valo 	ath12k_reg_update_rule(regd->reg_rules + i,
575d8899132SKalle Valo 			       ETSI_WEATHER_RADAR_BAND_LOW, end_freq, bw,
576d8899132SKalle Valo 			       reg_rule->ant_gain, reg_rule->reg_power,
577d8899132SKalle Valo 			       flags);
578d8899132SKalle Valo 
579d8899132SKalle Valo 	regd->reg_rules[i].dfs_cac_ms = ETSI_WEATHER_RADAR_BAND_CAC_TIMEOUT;
580d8899132SKalle Valo 
581d8899132SKalle Valo 	ath12k_dbg(ab, ATH12K_DBG_REG,
582d8899132SKalle Valo 		   "\t%d. (%d - %d @ %d) (%d, %d) (%d ms) (FLAGS %d)\n",
583d8899132SKalle Valo 		   i + 1, ETSI_WEATHER_RADAR_BAND_LOW, end_freq,
584d8899132SKalle Valo 		   bw, reg_rule->ant_gain, reg_rule->reg_power,
585d8899132SKalle Valo 		   regd->reg_rules[i].dfs_cac_ms,
586d8899132SKalle Valo 		   flags);
587d8899132SKalle Valo 
588d8899132SKalle Valo 	if (end_freq == reg_rule->end_freq) {
589d8899132SKalle Valo 		regd->n_reg_rules--;
590d8899132SKalle Valo 		*rule_idx = i;
591d8899132SKalle Valo 		return;
592d8899132SKalle Valo 	}
593d8899132SKalle Valo 
594d8899132SKalle Valo 	bw = ath12k_reg_adjust_bw(ETSI_WEATHER_RADAR_BAND_HIGH,
595d8899132SKalle Valo 				  reg_rule->end_freq, max_bw);
596d8899132SKalle Valo 
597d8899132SKalle Valo 	i++;
598d8899132SKalle Valo 
599d8899132SKalle Valo 	ath12k_reg_update_rule(regd->reg_rules + i, ETSI_WEATHER_RADAR_BAND_HIGH,
600d8899132SKalle Valo 			       reg_rule->end_freq, bw,
601d8899132SKalle Valo 			       reg_rule->ant_gain, reg_rule->reg_power,
602d8899132SKalle Valo 			       flags);
603d8899132SKalle Valo 
604d8899132SKalle Valo 	ath12k_dbg(ab, ATH12K_DBG_REG,
605d8899132SKalle Valo 		   "\t%d. (%d - %d @ %d) (%d, %d) (%d ms) (FLAGS %d)\n",
606d8899132SKalle Valo 		   i + 1, ETSI_WEATHER_RADAR_BAND_HIGH, reg_rule->end_freq,
607d8899132SKalle Valo 		   bw, reg_rule->ant_gain, reg_rule->reg_power,
608d8899132SKalle Valo 		   regd->reg_rules[i].dfs_cac_ms,
609d8899132SKalle Valo 		   flags);
610d8899132SKalle Valo 
611d8899132SKalle Valo 	*rule_idx = i;
612d8899132SKalle Valo }
613d8899132SKalle Valo 
614d8899132SKalle Valo struct ieee80211_regdomain *
ath12k_reg_build_regd(struct ath12k_base * ab,struct ath12k_reg_info * reg_info,bool intersect)615d8899132SKalle Valo ath12k_reg_build_regd(struct ath12k_base *ab,
616d8899132SKalle Valo 		      struct ath12k_reg_info *reg_info, bool intersect)
617d8899132SKalle Valo {
618d8899132SKalle Valo 	struct ieee80211_regdomain *tmp_regd, *default_regd, *new_regd = NULL;
619d8899132SKalle Valo 	struct ath12k_reg_rule *reg_rule;
620d8899132SKalle Valo 	u8 i = 0, j = 0, k = 0;
621d8899132SKalle Valo 	u8 num_rules;
622d8899132SKalle Valo 	u16 max_bw;
623d8899132SKalle Valo 	u32 flags;
624d8899132SKalle Valo 	char alpha2[3];
625d8899132SKalle Valo 
626d8899132SKalle Valo 	num_rules = reg_info->num_5g_reg_rules + reg_info->num_2g_reg_rules;
627d8899132SKalle Valo 
628d8899132SKalle Valo 	/* FIXME: Currently taking reg rules for 6G only from Indoor AP mode list.
629d8899132SKalle Valo 	 * This can be updated to choose the combination dynamically based on AP
630d8899132SKalle Valo 	 * type and client type, after complete 6G regulatory support is added.
631d8899132SKalle Valo 	 */
632d8899132SKalle Valo 	if (reg_info->is_ext_reg_event)
633d8899132SKalle Valo 		num_rules += reg_info->num_6g_reg_rules_ap[WMI_REG_INDOOR_AP];
634d8899132SKalle Valo 
635d8899132SKalle Valo 	if (!num_rules)
636d8899132SKalle Valo 		goto ret;
637d8899132SKalle Valo 
638d8899132SKalle Valo 	/* Add max additional rules to accommodate weather radar band */
639d8899132SKalle Valo 	if (reg_info->dfs_region == ATH12K_DFS_REG_ETSI)
640d8899132SKalle Valo 		num_rules += 2;
641d8899132SKalle Valo 
642d8899132SKalle Valo 	tmp_regd = kzalloc(sizeof(*tmp_regd) +
643d8899132SKalle Valo 			   (num_rules * sizeof(struct ieee80211_reg_rule)),
644d8899132SKalle Valo 			   GFP_ATOMIC);
645d8899132SKalle Valo 	if (!tmp_regd)
646d8899132SKalle Valo 		goto ret;
647d8899132SKalle Valo 
648d8899132SKalle Valo 	memcpy(tmp_regd->alpha2, reg_info->alpha2, REG_ALPHA2_LEN + 1);
649d8899132SKalle Valo 	memcpy(alpha2, reg_info->alpha2, REG_ALPHA2_LEN + 1);
650d8899132SKalle Valo 	alpha2[2] = '\0';
651d8899132SKalle Valo 	tmp_regd->dfs_region = ath12k_map_fw_dfs_region(reg_info->dfs_region);
652d8899132SKalle Valo 
653d8899132SKalle Valo 	ath12k_dbg(ab, ATH12K_DBG_REG,
654d8899132SKalle Valo 		   "\r\nCountry %s, CFG Regdomain %s FW Regdomain %d, num_reg_rules %d\n",
655d8899132SKalle Valo 		   alpha2, ath12k_reg_get_regdom_str(tmp_regd->dfs_region),
656d8899132SKalle Valo 		   reg_info->dfs_region, num_rules);
657d8899132SKalle Valo 	/* Update reg_rules[] below. Firmware is expected to
658d8899132SKalle Valo 	 * send these rules in order(2G rules first and then 5G)
659d8899132SKalle Valo 	 */
660d8899132SKalle Valo 	for (; i < num_rules; i++) {
661d8899132SKalle Valo 		if (reg_info->num_2g_reg_rules &&
662d8899132SKalle Valo 		    (i < reg_info->num_2g_reg_rules)) {
663d8899132SKalle Valo 			reg_rule = reg_info->reg_rules_2g_ptr + i;
664d8899132SKalle Valo 			max_bw = min_t(u16, reg_rule->max_bw,
665d8899132SKalle Valo 				       reg_info->max_bw_2g);
666d8899132SKalle Valo 			flags = 0;
667d8899132SKalle Valo 		} else if (reg_info->num_5g_reg_rules &&
668d8899132SKalle Valo 			   (j < reg_info->num_5g_reg_rules)) {
669d8899132SKalle Valo 			reg_rule = reg_info->reg_rules_5g_ptr + j++;
670d8899132SKalle Valo 			max_bw = min_t(u16, reg_rule->max_bw,
671d8899132SKalle Valo 				       reg_info->max_bw_5g);
672d8899132SKalle Valo 
673d8899132SKalle Valo 			/* FW doesn't pass NL80211_RRF_AUTO_BW flag for
674d8899132SKalle Valo 			 * BW Auto correction, we can enable this by default
675d8899132SKalle Valo 			 * for all 5G rules here. The regulatory core performs
676d8899132SKalle Valo 			 * BW correction if required and applies flags as
677d8899132SKalle Valo 			 * per other BW rule flags we pass from here
678d8899132SKalle Valo 			 */
679d8899132SKalle Valo 			flags = NL80211_RRF_AUTO_BW;
680d8899132SKalle Valo 		} else if (reg_info->is_ext_reg_event &&
681d8899132SKalle Valo 			   reg_info->num_6g_reg_rules_ap[WMI_REG_INDOOR_AP] &&
682d8899132SKalle Valo 			(k < reg_info->num_6g_reg_rules_ap[WMI_REG_INDOOR_AP])) {
683d8899132SKalle Valo 			reg_rule = reg_info->reg_rules_6g_ap_ptr[WMI_REG_INDOOR_AP] + k++;
684d8899132SKalle Valo 			max_bw = min_t(u16, reg_rule->max_bw,
685d8899132SKalle Valo 				       reg_info->max_bw_6g_ap[WMI_REG_INDOOR_AP]);
686d8899132SKalle Valo 			flags = NL80211_RRF_AUTO_BW;
687d8899132SKalle Valo 		} else {
688d8899132SKalle Valo 			break;
689d8899132SKalle Valo 		}
690d8899132SKalle Valo 
691d8899132SKalle Valo 		flags |= ath12k_map_fw_reg_flags(reg_rule->flags);
69229ea0d40SAditya Kumar Singh 		flags |= ath12k_map_fw_phy_flags(reg_info->phybitmap);
693d8899132SKalle Valo 
694d8899132SKalle Valo 		ath12k_reg_update_rule(tmp_regd->reg_rules + i,
695d8899132SKalle Valo 				       reg_rule->start_freq,
696d8899132SKalle Valo 				       reg_rule->end_freq, max_bw,
697d8899132SKalle Valo 				       reg_rule->ant_gain, reg_rule->reg_power,
698d8899132SKalle Valo 				       flags);
699d8899132SKalle Valo 
700d8899132SKalle Valo 		/* Update dfs cac timeout if the dfs domain is ETSI and the
701d8899132SKalle Valo 		 * new rule covers weather radar band.
702d8899132SKalle Valo 		 * Default value of '0' corresponds to 60s timeout, so no
703d8899132SKalle Valo 		 * need to update that for other rules.
704d8899132SKalle Valo 		 */
705d8899132SKalle Valo 		if (flags & NL80211_RRF_DFS &&
706d8899132SKalle Valo 		    reg_info->dfs_region == ATH12K_DFS_REG_ETSI &&
707d8899132SKalle Valo 		    (reg_rule->end_freq > ETSI_WEATHER_RADAR_BAND_LOW &&
708d8899132SKalle Valo 		    reg_rule->start_freq < ETSI_WEATHER_RADAR_BAND_HIGH)){
709d8899132SKalle Valo 			ath12k_reg_update_weather_radar_band(ab, tmp_regd,
710d8899132SKalle Valo 							     reg_rule, &i,
711d8899132SKalle Valo 							     flags, max_bw);
712d8899132SKalle Valo 			continue;
713d8899132SKalle Valo 		}
714d8899132SKalle Valo 
715d8899132SKalle Valo 		if (reg_info->is_ext_reg_event) {
716d8899132SKalle Valo 			ath12k_dbg(ab, ATH12K_DBG_REG, "\t%d. (%d - %d @ %d) (%d, %d) (%d ms) (FLAGS %d) (%d, %d)\n",
717d8899132SKalle Valo 				   i + 1, reg_rule->start_freq, reg_rule->end_freq,
718d8899132SKalle Valo 				   max_bw, reg_rule->ant_gain, reg_rule->reg_power,
719d8899132SKalle Valo 				   tmp_regd->reg_rules[i].dfs_cac_ms,
720d8899132SKalle Valo 				   flags, reg_rule->psd_flag, reg_rule->psd_eirp);
721d8899132SKalle Valo 		} else {
722d8899132SKalle Valo 			ath12k_dbg(ab, ATH12K_DBG_REG,
723d8899132SKalle Valo 				   "\t%d. (%d - %d @ %d) (%d, %d) (%d ms) (FLAGS %d)\n",
724d8899132SKalle Valo 				   i + 1, reg_rule->start_freq, reg_rule->end_freq,
725d8899132SKalle Valo 				   max_bw, reg_rule->ant_gain, reg_rule->reg_power,
726d8899132SKalle Valo 				   tmp_regd->reg_rules[i].dfs_cac_ms,
727d8899132SKalle Valo 				   flags);
728d8899132SKalle Valo 		}
729d8899132SKalle Valo 	}
730d8899132SKalle Valo 
731d8899132SKalle Valo 	tmp_regd->n_reg_rules = i;
732d8899132SKalle Valo 
733d8899132SKalle Valo 	if (intersect) {
734d8899132SKalle Valo 		default_regd = ab->default_regd[reg_info->phy_id];
735d8899132SKalle Valo 
736d8899132SKalle Valo 		/* Get a new regd by intersecting the received regd with
737d8899132SKalle Valo 		 * our default regd.
738d8899132SKalle Valo 		 */
739d8899132SKalle Valo 		new_regd = ath12k_regd_intersect(default_regd, tmp_regd);
740d8899132SKalle Valo 		kfree(tmp_regd);
741d8899132SKalle Valo 		if (!new_regd) {
742d8899132SKalle Valo 			ath12k_warn(ab, "Unable to create intersected regdomain\n");
743d8899132SKalle Valo 			goto ret;
744d8899132SKalle Valo 		}
745d8899132SKalle Valo 	} else {
746d8899132SKalle Valo 		new_regd = tmp_regd;
747d8899132SKalle Valo 	}
748d8899132SKalle Valo 
749d8899132SKalle Valo ret:
750d8899132SKalle Valo 	return new_regd;
751d8899132SKalle Valo }
752d8899132SKalle Valo 
ath12k_regd_update_work(struct work_struct * work)753d8899132SKalle Valo void ath12k_regd_update_work(struct work_struct *work)
754d8899132SKalle Valo {
755d8899132SKalle Valo 	struct ath12k *ar = container_of(work, struct ath12k,
756d8899132SKalle Valo 					 regd_update_work);
757d8899132SKalle Valo 	int ret;
758d8899132SKalle Valo 
759d8899132SKalle Valo 	ret = ath12k_regd_update(ar, false);
760d8899132SKalle Valo 	if (ret) {
761d8899132SKalle Valo 		/* Firmware has already moved to the new regd. We need
762d8899132SKalle Valo 		 * to maintain channel consistency across FW, Host driver
763d8899132SKalle Valo 		 * and userspace. Hence as a fallback mechanism we can set
764d8899132SKalle Valo 		 * the prev or default country code to the firmware.
765d8899132SKalle Valo 		 */
766d8899132SKalle Valo 		/* TODO: Implement Fallback Mechanism */
767d8899132SKalle Valo 	}
768d8899132SKalle Valo }
769d8899132SKalle Valo 
ath12k_reg_init(struct ieee80211_hw * hw)770940b57fdSKarthikeyan Periyasamy void ath12k_reg_init(struct ieee80211_hw *hw)
771d8899132SKalle Valo {
772940b57fdSKarthikeyan Periyasamy 	hw->wiphy->regulatory_flags = REGULATORY_WIPHY_SELF_MANAGED;
773940b57fdSKarthikeyan Periyasamy 	hw->wiphy->reg_notifier = ath12k_reg_notifier;
774d8899132SKalle Valo }
775d8899132SKalle Valo 
ath12k_reg_free(struct ath12k_base * ab)776d8899132SKalle Valo void ath12k_reg_free(struct ath12k_base *ab)
777d8899132SKalle Valo {
778d8899132SKalle Valo 	int i;
779d8899132SKalle Valo 
780d8899132SKalle Valo 	for (i = 0; i < ab->hw_params->max_radios; i++) {
781d8899132SKalle Valo 		kfree(ab->default_regd[i]);
782d8899132SKalle Valo 		kfree(ab->new_regd[i]);
783d8899132SKalle Valo 	}
784d8899132SKalle Valo }
785