Lines Matching +full:reg +full:- +full:5 +full:ah
4 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
5 * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com>
6 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
25 #include "reg.h"
29 * struct ath5k_ini - Mode-independent initial register writes
45 * struct ath5k_ini_mode - Mode specific initial register values
96 { AR5K_PHY(5), 0x0000076b },
132 { AR5K_BB_GAIN(5), 0x00000028 },
197 { AR5K_RF_GAIN(5), 0x00000021 },
283 { AR5K_QUEUE_TXDP(5), 0x00000000 },
309 { AR5K_PHY(5), 0x00000f6b },
347 * data etc. so next write is non-common */
352 { AR5K_PHY_PCDAC_TXPOWER(5), 0x0aff0aff },
392 /* Initial mode-specific settings for AR5211
393 * 5211 supports OFDM-only g (draft g) but we
409 { AR5K_QUEUE_DFS_LOCAL_IFS(5),
482 { AR5K_QUEUE_TXDP(5), 0x00000000 },
495 { AR5K_DCU_TX_FILTER_0(5), 0x00000000 },
510 { AR5K_DCU_TX_FILTER_0(20), 0x00000000 }, /* DCU 5 */
528 { AR5K_DCU_TX_FILTER_1(5), 0x00000000 },
578 { AR5K_RATE_DUR(5), 0x00000000 },
611 /* Rate -> db table
612 * notice ...03<-02<-01<-00 ! */
618 { AR5K_RATE2DB(5), 0x17161514 },
621 /* Db -> Rate table */
627 { AR5K_DB2RATE(5), 0x17161514 },
678 /* Initial mode-specific settings for AR5212 (Written before ar5212_ini) */
691 { AR5K_QUEUE_DFS_LOCAL_IFS(5),
731 /* Initial mode-specific settings for AR5212 + RF5111
784 /* Initial mode-specific settings for AR5212 + RF5112
837 /* Initial mode-specific settings for RF5413/5414
976 /* Initial mode-specific settings for RF2413/2414
1099 /* Initial mode-specific settings for RF2425
1242 { AR5K_BB_GAIN(5), 0x00000028 },
1310 { AR5K_BB_GAIN(5), 0x00000005 },
1373 * ath5k_hw_ini_registers() - Write initial register dump common for all modes
1374 * @ah: The &struct ath5k_hw
1380 ath5k_hw_ini_registers(struct ath5k_hw *ah, unsigned int size, in ath5k_hw_ini_registers() argument
1397 ath5k_hw_reg_read(ah, ini_regs[i].ini_register); in ath5k_hw_ini_registers()
1402 ath5k_hw_reg_write(ah, ini_regs[i].ini_value, in ath5k_hw_ini_registers()
1409 * ath5k_hw_ini_mode_registers() - Write initial mode-specific register dump
1410 * @ah: The &struct ath5k_hw
1416 ath5k_hw_ini_mode_registers(struct ath5k_hw *ah, in ath5k_hw_ini_mode_registers() argument
1424 ath5k_hw_reg_write(ah, ini_mode[i].mode_value[mode], in ath5k_hw_ini_mode_registers()
1431 * ath5k_hw_write_initvals() - Write initial chip-specific register dump
1432 * @ah: The &struct ath5k_hw
1436 * Write initial chip-specific register dump, to get the chipset on a
1437 * clean and ready-to-work state after warm reset.
1440 ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool skip_pcu) in ath5k_hw_write_initvals() argument
1447 if (ah->ah_version == AR5K_AR5212) { in ath5k_hw_write_initvals()
1449 /* First set of mode-specific settings */ in ath5k_hw_write_initvals()
1450 ath5k_hw_ini_mode_registers(ah, in ath5k_hw_write_initvals()
1457 ath5k_hw_ini_registers(ah, ARRAY_SIZE(ar5212_ini_common_start), in ath5k_hw_write_initvals()
1460 /* Second set of mode-specific settings */ in ath5k_hw_write_initvals()
1461 switch (ah->ah_radio) { in ath5k_hw_write_initvals()
1464 ath5k_hw_ini_mode_registers(ah, in ath5k_hw_write_initvals()
1468 ath5k_hw_ini_registers(ah, in ath5k_hw_write_initvals()
1473 ath5k_hw_ini_registers(ah, in ath5k_hw_write_initvals()
1480 ath5k_hw_ini_mode_registers(ah, in ath5k_hw_write_initvals()
1484 ath5k_hw_ini_registers(ah, in ath5k_hw_write_initvals()
1488 ath5k_hw_ini_registers(ah, in ath5k_hw_write_initvals()
1495 ath5k_hw_ini_mode_registers(ah, in ath5k_hw_write_initvals()
1499 ath5k_hw_ini_registers(ah, in ath5k_hw_write_initvals()
1503 ath5k_hw_ini_registers(ah, in ath5k_hw_write_initvals()
1511 ath5k_hw_ini_mode_registers(ah, in ath5k_hw_write_initvals()
1515 ath5k_hw_ini_registers(ah, in ath5k_hw_write_initvals()
1520 if (ah->ah_radio == AR5K_RF2316) { in ath5k_hw_write_initvals()
1521 ath5k_hw_reg_write(ah, 0x00004000, in ath5k_hw_write_initvals()
1523 ath5k_hw_reg_write(ah, 0x081b7caa, in ath5k_hw_write_initvals()
1527 ath5k_hw_ini_registers(ah, in ath5k_hw_write_initvals()
1533 ath5k_hw_ini_mode_registers(ah, in ath5k_hw_write_initvals()
1537 ath5k_hw_ini_registers(ah, in ath5k_hw_write_initvals()
1542 ath5k_hw_reg_write(ah, 0x00180a65, AR5K_PHY_GAIN); in ath5k_hw_write_initvals()
1545 ath5k_hw_reg_write(ah, 0x00004000, AR5K_PHY_AGC); in ath5k_hw_write_initvals()
1546 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TPC_RG5, in ath5k_hw_write_initvals()
1548 ath5k_hw_reg_write(ah, 0x800000a8, 0x8140); in ath5k_hw_write_initvals()
1549 ath5k_hw_reg_write(ah, 0x000000ff, 0x9958); in ath5k_hw_write_initvals()
1551 ath5k_hw_ini_registers(ah, in ath5k_hw_write_initvals()
1557 ath5k_hw_ini_mode_registers(ah, in ath5k_hw_write_initvals()
1561 ath5k_hw_ini_registers(ah, in ath5k_hw_write_initvals()
1565 ath5k_hw_ini_registers(ah, in ath5k_hw_write_initvals()
1570 return -EINVAL; in ath5k_hw_write_initvals()
1575 } else if (ah->ah_version == AR5K_AR5211) { in ath5k_hw_write_initvals()
1579 ATH5K_ERR(ah, "unsupported channel mode: %d\n", mode); in ath5k_hw_write_initvals()
1580 return -EINVAL; in ath5k_hw_write_initvals()
1583 /* Mode-specific settings */ in ath5k_hw_write_initvals()
1584 ath5k_hw_ini_mode_registers(ah, ARRAY_SIZE(ar5211_ini_mode), in ath5k_hw_write_initvals()
1590 ath5k_hw_ini_registers(ah, ARRAY_SIZE(ar5211_ini), in ath5k_hw_write_initvals()
1596 ath5k_hw_ini_registers(ah, ARRAY_SIZE(rf5111_ini_bbgain), in ath5k_hw_write_initvals()
1599 } else if (ah->ah_version == AR5K_AR5210) { in ath5k_hw_write_initvals()
1600 ath5k_hw_ini_registers(ah, ARRAY_SIZE(ar5210_ini), in ath5k_hw_write_initvals()