Lines Matching +full:reg +full:- +full:5 +full:ah
1 /*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
20 * 3. Neither the names of the above-listed copyright holders nor the names
47 #include <linux/dma-mapping.h>
66 #include "reg.h"
92 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
96 static int ath5k_reset(struct ath5k_hw *ah, struct ieee80211_channel *chan,
200 static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp) in ath5k_extend_tsf() argument
202 u64 tsf = ath5k_hw_get_tsf64(ah); in ath5k_extend_tsf()
205 tsf -= 0x8000; in ath5k_extend_tsf()
233 struct ath5k_hw *ah = hw_priv; in ath5k_ioread32() local
234 return ath5k_hw_reg_read(ah, reg_offset); in ath5k_ioread32()
239 struct ath5k_hw *ah = hw_priv; in ath5k_iowrite32() local
240 ath5k_hw_reg_write(ah, val, reg_offset); in ath5k_iowrite32()
256 struct ath5k_hw *ah = hw->priv; in ath5k_reg_notifier() local
257 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah); in ath5k_reg_notifier()
285 /* UNII-3 */ in ath5k_is_standard_channel()
287 /* 802.11j 5.030-5.080 GHz (20MHz) */ in ath5k_is_standard_channel()
295 ath5k_setup_channels(struct ath5k_hw *ah, struct ieee80211_channel *channels, in ath5k_setup_channels() argument
313 ATH5K_WARN(ah, "bad mode, not copying channels\n"); in ath5k_setup_channels()
321 if (freq == 0) /* mapping failed - not a standard channel */ in ath5k_setup_channels()
330 if (!ath5k_channel_ok(ah, &channels[count])) in ath5k_setup_channels()
343 ath5k_setup_rate_idx(struct ath5k_hw *ah, struct ieee80211_supported_band *b) in ath5k_setup_rate_idx() argument
348 ah->rate_idx[b->band][i] = -1; in ath5k_setup_rate_idx()
350 for (i = 0; i < b->n_bitrates; i++) { in ath5k_setup_rate_idx()
351 ah->rate_idx[b->band][b->bitrates[i].hw_value] = i; in ath5k_setup_rate_idx()
352 if (b->bitrates[i].hw_value_short) in ath5k_setup_rate_idx()
353 ah->rate_idx[b->band][b->bitrates[i].hw_value_short] = i; in ath5k_setup_rate_idx()
360 struct ath5k_hw *ah = hw->priv; in ath5k_setup_bands() local
365 BUILD_BUG_ON(ARRAY_SIZE(ah->sbands) < NUM_NL80211_BANDS); in ath5k_setup_bands()
366 max_c = ARRAY_SIZE(ah->channels); in ath5k_setup_bands()
369 sband = &ah->sbands[NL80211_BAND_2GHZ]; in ath5k_setup_bands()
370 sband->band = NL80211_BAND_2GHZ; in ath5k_setup_bands()
371 sband->bitrates = &ah->rates[NL80211_BAND_2GHZ][0]; in ath5k_setup_bands()
373 if (test_bit(AR5K_MODE_11G, ah->ah_capabilities.cap_mode)) { in ath5k_setup_bands()
375 memcpy(sband->bitrates, &ath5k_rates[0], in ath5k_setup_bands()
377 sband->n_bitrates = 12; in ath5k_setup_bands()
379 sband->channels = ah->channels; in ath5k_setup_bands()
380 sband->n_channels = ath5k_setup_channels(ah, sband->channels, in ath5k_setup_bands()
383 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband; in ath5k_setup_bands()
384 count_c = sband->n_channels; in ath5k_setup_bands()
385 max_c -= count_c; in ath5k_setup_bands()
386 } else if (test_bit(AR5K_MODE_11B, ah->ah_capabilities.cap_mode)) { in ath5k_setup_bands()
388 memcpy(sband->bitrates, &ath5k_rates[0], in ath5k_setup_bands()
390 sband->n_bitrates = 4; in ath5k_setup_bands()
396 if (ah->ah_version == AR5K_AR5211) { in ath5k_setup_bands()
398 sband->bitrates[i].hw_value = in ath5k_setup_bands()
399 sband->bitrates[i].hw_value & 0xF; in ath5k_setup_bands()
400 sband->bitrates[i].hw_value_short = in ath5k_setup_bands()
401 sband->bitrates[i].hw_value_short & 0xF; in ath5k_setup_bands()
405 sband->channels = ah->channels; in ath5k_setup_bands()
406 sband->n_channels = ath5k_setup_channels(ah, sband->channels, in ath5k_setup_bands()
409 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband; in ath5k_setup_bands()
410 count_c = sband->n_channels; in ath5k_setup_bands()
411 max_c -= count_c; in ath5k_setup_bands()
413 ath5k_setup_rate_idx(ah, sband); in ath5k_setup_bands()
415 /* 5GHz band, A mode */ in ath5k_setup_bands()
416 if (test_bit(AR5K_MODE_11A, ah->ah_capabilities.cap_mode)) { in ath5k_setup_bands()
417 sband = &ah->sbands[NL80211_BAND_5GHZ]; in ath5k_setup_bands()
418 sband->band = NL80211_BAND_5GHZ; in ath5k_setup_bands()
419 sband->bitrates = &ah->rates[NL80211_BAND_5GHZ][0]; in ath5k_setup_bands()
421 memcpy(sband->bitrates, &ath5k_rates[4], in ath5k_setup_bands()
423 sband->n_bitrates = 8; in ath5k_setup_bands()
425 sband->channels = &ah->channels[count_c]; in ath5k_setup_bands()
426 sband->n_channels = ath5k_setup_channels(ah, sband->channels, in ath5k_setup_bands()
429 hw->wiphy->bands[NL80211_BAND_5GHZ] = sband; in ath5k_setup_bands()
431 ath5k_setup_rate_idx(ah, sband); in ath5k_setup_bands()
433 ath5k_debug_dump_bands(ah); in ath5k_setup_bands()
443 * Called with ah->lock.
446 ath5k_chan_set(struct ath5k_hw *ah, struct cfg80211_chan_def *chandef) in ath5k_chan_set() argument
448 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, in ath5k_chan_set()
449 "channel set, resetting (%u -> %u MHz)\n", in ath5k_chan_set()
450 ah->curchan->center_freq, chandef->chan->center_freq); in ath5k_chan_set()
452 switch (chandef->width) { in ath5k_chan_set()
455 ah->ah_bwmode = AR5K_BWMODE_DEFAULT; in ath5k_chan_set()
458 ah->ah_bwmode = AR5K_BWMODE_5MHZ; in ath5k_chan_set()
461 ah->ah_bwmode = AR5K_BWMODE_10MHZ; in ath5k_chan_set()
465 return -EINVAL; in ath5k_chan_set()
471 * hardware at the new frequency, and then re-enable in ath5k_chan_set()
474 return ath5k_reset(ah, chandef->chan, true); in ath5k_chan_set()
481 struct ath5k_vif *avf = (void *)vif->drv_priv; in ath5k_vif_iter()
483 if (iter_data->hw_macaddr) in ath5k_vif_iter()
485 iter_data->mask[i] &= in ath5k_vif_iter()
486 ~(iter_data->hw_macaddr[i] ^ mac[i]); in ath5k_vif_iter()
488 if (!iter_data->found_active) { in ath5k_vif_iter()
489 iter_data->found_active = true; in ath5k_vif_iter()
490 memcpy(iter_data->active_mac, mac, ETH_ALEN); in ath5k_vif_iter()
493 if (iter_data->need_set_hw_addr && iter_data->hw_macaddr) in ath5k_vif_iter()
494 if (ether_addr_equal(iter_data->hw_macaddr, mac)) in ath5k_vif_iter()
495 iter_data->need_set_hw_addr = false; in ath5k_vif_iter()
497 if (!iter_data->any_assoc) { in ath5k_vif_iter()
498 if (avf->assoc) in ath5k_vif_iter()
499 iter_data->any_assoc = true; in ath5k_vif_iter()
502 /* Calculate combined mode - when APs are active, operate in AP mode. in ath5k_vif_iter()
504 * only deal with combinations of APs and STAs. Only one ad-hoc in ath5k_vif_iter()
507 if (avf->opmode == NL80211_IFTYPE_AP) in ath5k_vif_iter()
508 iter_data->opmode = NL80211_IFTYPE_AP; in ath5k_vif_iter()
510 if (avf->opmode == NL80211_IFTYPE_STATION) in ath5k_vif_iter()
511 iter_data->n_stas++; in ath5k_vif_iter()
512 if (iter_data->opmode == NL80211_IFTYPE_UNSPECIFIED) in ath5k_vif_iter()
513 iter_data->opmode = avf->opmode; in ath5k_vif_iter()
518 ath5k_update_bssid_mask_and_opmode(struct ath5k_hw *ah, in ath5k_update_bssid_mask_and_opmode() argument
521 struct ath_common *common = ath5k_hw_common(ah); in ath5k_update_bssid_mask_and_opmode()
529 iter_data.hw_macaddr = common->macaddr; in ath5k_update_bssid_mask_and_opmode()
537 ath5k_vif_iter(&iter_data, vif->addr, vif); in ath5k_update_bssid_mask_and_opmode()
541 ah->hw, IEEE80211_IFACE_ITER_RESUME_ALL, in ath5k_update_bssid_mask_and_opmode()
543 memcpy(ah->bssidmask, iter_data.mask, ETH_ALEN); in ath5k_update_bssid_mask_and_opmode()
545 ah->opmode = iter_data.opmode; in ath5k_update_bssid_mask_and_opmode()
546 if (ah->opmode == NL80211_IFTYPE_UNSPECIFIED) in ath5k_update_bssid_mask_and_opmode()
548 ah->opmode = NL80211_IFTYPE_STATION; in ath5k_update_bssid_mask_and_opmode()
550 ath5k_hw_set_opmode(ah, ah->opmode); in ath5k_update_bssid_mask_and_opmode()
551 ATH5K_DBG(ah, ATH5K_DEBUG_MODE, "mode setup opmode %d (%s)\n", in ath5k_update_bssid_mask_and_opmode()
552 ah->opmode, ath_opmode_to_string(ah->opmode)); in ath5k_update_bssid_mask_and_opmode()
555 ath5k_hw_set_lladdr(ah, iter_data.active_mac); in ath5k_update_bssid_mask_and_opmode()
557 if (ath5k_hw_hasbssidmask(ah)) in ath5k_update_bssid_mask_and_opmode()
558 ath5k_hw_set_bssid_mask(ah, ah->bssidmask); in ath5k_update_bssid_mask_and_opmode()
566 ah->filter_flags |= AR5K_RX_FILTER_PROM; in ath5k_update_bssid_mask_and_opmode()
569 rfilt = ah->filter_flags; in ath5k_update_bssid_mask_and_opmode()
570 ath5k_hw_set_rx_filter(ah, rfilt); in ath5k_update_bssid_mask_and_opmode()
571 ATH5K_DBG(ah, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt); in ath5k_update_bssid_mask_and_opmode()
575 ath5k_hw_to_driver_rix(struct ath5k_hw *ah, int hw_rix) in ath5k_hw_to_driver_rix() argument
584 rix = ah->rate_idx[ah->curchan->band][hw_rix]; in ath5k_hw_to_driver_rix()
596 struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_hw *ah, dma_addr_t *skb_addr) in ath5k_rx_skb_alloc() argument
598 struct ath_common *common = ath5k_hw_common(ah); in ath5k_rx_skb_alloc()
606 common->rx_bufsize, in ath5k_rx_skb_alloc()
610 ATH5K_ERR(ah, "can't alloc skbuff of size %u\n", in ath5k_rx_skb_alloc()
611 common->rx_bufsize); in ath5k_rx_skb_alloc()
615 *skb_addr = dma_map_single(ah->dev, in ath5k_rx_skb_alloc()
616 skb->data, common->rx_bufsize, in ath5k_rx_skb_alloc()
619 if (unlikely(dma_mapping_error(ah->dev, *skb_addr))) { in ath5k_rx_skb_alloc()
620 ATH5K_ERR(ah, "%s: DMA mapping failed\n", __func__); in ath5k_rx_skb_alloc()
628 ath5k_rxbuf_setup(struct ath5k_hw *ah, struct ath5k_buf *bf) in ath5k_rxbuf_setup() argument
630 struct sk_buff *skb = bf->skb; in ath5k_rxbuf_setup()
635 skb = ath5k_rx_skb_alloc(ah, &bf->skbaddr); in ath5k_rxbuf_setup()
637 return -ENOMEM; in ath5k_rxbuf_setup()
638 bf->skb = skb; in ath5k_rxbuf_setup()
643 * the descriptor list with a self-linked entry so we'll in ath5k_rxbuf_setup()
647 * To ensure the last descriptor is self-linked we create in ath5k_rxbuf_setup()
648 * each descriptor as self-linked and add it to the end. As in ath5k_rxbuf_setup()
649 * each additional descriptor is added the previous self-linked in ath5k_rxbuf_setup()
652 * never remove/process the last, self-linked, entry on the in ath5k_rxbuf_setup()
656 ds = bf->desc; in ath5k_rxbuf_setup()
657 ds->ds_link = bf->daddr; /* link to self */ in ath5k_rxbuf_setup()
658 ds->ds_data = bf->skbaddr; in ath5k_rxbuf_setup()
659 ret = ath5k_hw_setup_rx_desc(ah, ds, ah->common.rx_bufsize, 0); in ath5k_rxbuf_setup()
661 ATH5K_ERR(ah, "%s: could not setup RX desc\n", __func__); in ath5k_rxbuf_setup()
665 if (ah->rxlink != NULL) in ath5k_rxbuf_setup()
666 *ah->rxlink = bf->daddr; in ath5k_rxbuf_setup()
667 ah->rxlink = &ds->ds_link; in ath5k_rxbuf_setup()
677 hdr = (struct ieee80211_hdr *)skb->data; in get_hw_packet_type()
678 fc = hdr->frame_control; in get_hw_packet_type()
700 * convert a ieee80211_tx_rate RC-table entry to in ath5k_get_rate()
703 if (bf->rates[idx].idx < 0) { in ath5k_get_rate()
707 return &hw->wiphy->bands[info->band]->bitrates[ bf->rates[idx].idx ]; in ath5k_get_rate()
723 rc_flags = bf->rates[idx].flags; in ath5k_get_rate_hw_value()
725 rate->hw_value_short : rate->hw_value; in ath5k_get_rate_hw_value()
740 ratetbl = rcu_dereference(sta->rates); in ath5k_merge_ratetbl()
744 if (tx_info->control.rates[0].idx < 0 || in ath5k_merge_ratetbl()
745 tx_info->control.rates[0].count == 0) in ath5k_merge_ratetbl()
749 bf->rates[0] = tx_info->control.rates[0]; in ath5k_merge_ratetbl()
754 bf->rates[i].idx = ratetbl->rate[i].idx; in ath5k_merge_ratetbl()
755 bf->rates[i].flags = ratetbl->rate[i].flags; in ath5k_merge_ratetbl()
756 if (tx_info->control.use_rts) in ath5k_merge_ratetbl()
757 bf->rates[i].count = ratetbl->rate[i].count_rts; in ath5k_merge_ratetbl()
758 else if (tx_info->control.use_cts_prot) in ath5k_merge_ratetbl()
759 bf->rates[i].count = ratetbl->rate[i].count_cts; in ath5k_merge_ratetbl()
761 bf->rates[i].count = ratetbl->rate[i].count; in ath5k_merge_ratetbl()
768 ath5k_txbuf_setup(struct ath5k_hw *ah, struct ath5k_buf *bf, in ath5k_txbuf_setup() argument
772 struct ath5k_desc *ds = bf->desc; in ath5k_txbuf_setup()
773 struct sk_buff *skb = bf->skb; in ath5k_txbuf_setup()
788 bf->skbaddr = dma_map_single(ah->dev, skb->data, skb->len, in ath5k_txbuf_setup()
791 if (dma_mapping_error(ah->dev, bf->skbaddr)) in ath5k_txbuf_setup()
792 return -ENOSPC; in ath5k_txbuf_setup()
795 sta = control->sta; in ath5k_txbuf_setup()
800 ieee80211_get_tx_rates(info->control.vif, in ath5k_txbuf_setup()
801 sta, skb, bf->rates, in ath5k_txbuf_setup()
802 ARRAY_SIZE(bf->rates)); in ath5k_txbuf_setup()
805 rate = ath5k_get_rate(ah->hw, info, bf, 0); in ath5k_txbuf_setup()
808 ret = -EINVAL; in ath5k_txbuf_setup()
812 if (info->flags & IEEE80211_TX_CTL_NO_ACK) in ath5k_txbuf_setup()
815 rc_flags = bf->rates[0].flags; in ath5k_txbuf_setup()
817 hw_rate = ath5k_get_rate_hw_value(ah->hw, info, bf, 0); in ath5k_txbuf_setup()
819 pktlen = skb->len; in ath5k_txbuf_setup()
822 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta in ath5k_txbuf_setup()
824 if (info->control.hw_key) { in ath5k_txbuf_setup()
825 keyidx = info->control.hw_key->hw_key_idx; in ath5k_txbuf_setup()
826 pktlen += info->control.hw_key->icv_len; in ath5k_txbuf_setup()
830 cts_rate = ieee80211_get_rts_cts_rate(ah->hw, info)->hw_value; in ath5k_txbuf_setup()
831 duration = le16_to_cpu(ieee80211_rts_duration(ah->hw, in ath5k_txbuf_setup()
832 info->control.vif, pktlen, info)); in ath5k_txbuf_setup()
836 cts_rate = ieee80211_get_rts_cts_rate(ah->hw, info)->hw_value; in ath5k_txbuf_setup()
837 duration = le16_to_cpu(ieee80211_ctstoself_duration(ah->hw, in ath5k_txbuf_setup()
838 info->control.vif, pktlen, info)); in ath5k_txbuf_setup()
841 ret = ah->ah_setup_tx_desc(ah, ds, pktlen, in ath5k_txbuf_setup()
844 (ah->ah_txpower.txp_requested * 2), in ath5k_txbuf_setup()
846 bf->rates[0].count, keyidx, ah->ah_tx_ant, flags, in ath5k_txbuf_setup()
852 if (ah->ah_capabilities.cap_has_mrr_support) { in ath5k_txbuf_setup()
858 rate = ath5k_get_rate(ah->hw, info, bf, i); in ath5k_txbuf_setup()
862 mrr_rate[i] = ath5k_get_rate_hw_value(ah->hw, info, bf, i); in ath5k_txbuf_setup()
863 mrr_tries[i] = bf->rates[i].count; in ath5k_txbuf_setup()
866 ath5k_hw_setup_mrr_tx_desc(ah, ds, in ath5k_txbuf_setup()
872 ds->ds_link = 0; in ath5k_txbuf_setup()
873 ds->ds_data = bf->skbaddr; in ath5k_txbuf_setup()
875 spin_lock_bh(&txq->lock); in ath5k_txbuf_setup()
876 list_add_tail(&bf->list, &txq->q); in ath5k_txbuf_setup()
877 txq->txq_len++; in ath5k_txbuf_setup()
878 if (txq->link == NULL) /* is this first packet? */ in ath5k_txbuf_setup()
879 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr); in ath5k_txbuf_setup()
881 *txq->link = bf->daddr; in ath5k_txbuf_setup()
883 txq->link = &ds->ds_link; in ath5k_txbuf_setup()
884 ath5k_hw_start_tx_dma(ah, txq->qnum); in ath5k_txbuf_setup()
885 spin_unlock_bh(&txq->lock); in ath5k_txbuf_setup()
889 dma_unmap_single(ah->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE); in ath5k_txbuf_setup()
898 ath5k_desc_alloc(struct ath5k_hw *ah) in ath5k_desc_alloc() argument
907 ah->desc_len = sizeof(struct ath5k_desc) * in ath5k_desc_alloc()
910 ah->desc = dma_alloc_coherent(ah->dev, ah->desc_len, in ath5k_desc_alloc()
911 &ah->desc_daddr, GFP_KERNEL); in ath5k_desc_alloc()
912 if (ah->desc == NULL) { in ath5k_desc_alloc()
913 ATH5K_ERR(ah, "can't allocate descriptors\n"); in ath5k_desc_alloc()
914 ret = -ENOMEM; in ath5k_desc_alloc()
917 ds = ah->desc; in ath5k_desc_alloc()
918 da = ah->desc_daddr; in ath5k_desc_alloc()
919 ATH5K_DBG(ah, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n", in ath5k_desc_alloc()
920 ds, ah->desc_len, (unsigned long long)ah->desc_daddr); in ath5k_desc_alloc()
925 ATH5K_ERR(ah, "can't allocate bufptr\n"); in ath5k_desc_alloc()
926 ret = -ENOMEM; in ath5k_desc_alloc()
929 ah->bufptr = bf; in ath5k_desc_alloc()
931 INIT_LIST_HEAD(&ah->rxbuf); in ath5k_desc_alloc()
933 bf->desc = ds; in ath5k_desc_alloc()
934 bf->daddr = da; in ath5k_desc_alloc()
935 list_add_tail(&bf->list, &ah->rxbuf); in ath5k_desc_alloc()
938 INIT_LIST_HEAD(&ah->txbuf); in ath5k_desc_alloc()
939 ah->txbuf_len = ATH_TXBUF; in ath5k_desc_alloc()
941 bf->desc = ds; in ath5k_desc_alloc()
942 bf->daddr = da; in ath5k_desc_alloc()
943 list_add_tail(&bf->list, &ah->txbuf); in ath5k_desc_alloc()
947 INIT_LIST_HEAD(&ah->bcbuf); in ath5k_desc_alloc()
949 bf->desc = ds; in ath5k_desc_alloc()
950 bf->daddr = da; in ath5k_desc_alloc()
951 list_add_tail(&bf->list, &ah->bcbuf); in ath5k_desc_alloc()
956 dma_free_coherent(ah->dev, ah->desc_len, ah->desc, ah->desc_daddr); in ath5k_desc_alloc()
958 ah->desc = NULL; in ath5k_desc_alloc()
963 ath5k_txbuf_free_skb(struct ath5k_hw *ah, struct ath5k_buf *bf) in ath5k_txbuf_free_skb() argument
966 if (!bf->skb) in ath5k_txbuf_free_skb()
968 dma_unmap_single(ah->dev, bf->skbaddr, bf->skb->len, in ath5k_txbuf_free_skb()
970 ieee80211_free_txskb(ah->hw, bf->skb); in ath5k_txbuf_free_skb()
971 bf->skb = NULL; in ath5k_txbuf_free_skb()
972 bf->skbaddr = 0; in ath5k_txbuf_free_skb()
973 bf->desc->ds_data = 0; in ath5k_txbuf_free_skb()
977 ath5k_rxbuf_free_skb(struct ath5k_hw *ah, struct ath5k_buf *bf) in ath5k_rxbuf_free_skb() argument
979 struct ath_common *common = ath5k_hw_common(ah); in ath5k_rxbuf_free_skb()
982 if (!bf->skb) in ath5k_rxbuf_free_skb()
984 dma_unmap_single(ah->dev, bf->skbaddr, common->rx_bufsize, in ath5k_rxbuf_free_skb()
986 dev_kfree_skb_any(bf->skb); in ath5k_rxbuf_free_skb()
987 bf->skb = NULL; in ath5k_rxbuf_free_skb()
988 bf->skbaddr = 0; in ath5k_rxbuf_free_skb()
989 bf->desc->ds_data = 0; in ath5k_rxbuf_free_skb()
993 ath5k_desc_free(struct ath5k_hw *ah) in ath5k_desc_free() argument
997 list_for_each_entry(bf, &ah->txbuf, list) in ath5k_desc_free()
998 ath5k_txbuf_free_skb(ah, bf); in ath5k_desc_free()
999 list_for_each_entry(bf, &ah->rxbuf, list) in ath5k_desc_free()
1000 ath5k_rxbuf_free_skb(ah, bf); in ath5k_desc_free()
1001 list_for_each_entry(bf, &ah->bcbuf, list) in ath5k_desc_free()
1002 ath5k_txbuf_free_skb(ah, bf); in ath5k_desc_free()
1005 dma_free_coherent(ah->dev, ah->desc_len, ah->desc, ah->desc_daddr); in ath5k_desc_free()
1006 ah->desc = NULL; in ath5k_desc_free()
1007 ah->desc_daddr = 0; in ath5k_desc_free()
1009 kfree(ah->bufptr); in ath5k_desc_free()
1010 ah->bufptr = NULL; in ath5k_desc_free()
1019 ath5k_txq_setup(struct ath5k_hw *ah, in ath5k_txq_setup() argument
1047 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi); in ath5k_txq_setup()
1055 txq = &ah->txqs[qnum]; in ath5k_txq_setup()
1056 if (!txq->setup) { in ath5k_txq_setup()
1057 txq->qnum = qnum; in ath5k_txq_setup()
1058 txq->link = NULL; in ath5k_txq_setup()
1059 INIT_LIST_HEAD(&txq->q); in ath5k_txq_setup()
1060 spin_lock_init(&txq->lock); in ath5k_txq_setup()
1061 txq->setup = true; in ath5k_txq_setup()
1062 txq->txq_len = 0; in ath5k_txq_setup()
1063 txq->txq_max = ATH5K_TXQ_LEN_MAX; in ath5k_txq_setup()
1064 txq->txq_poll_mark = false; in ath5k_txq_setup()
1065 txq->txq_stuck = 0; in ath5k_txq_setup()
1067 return &ah->txqs[qnum]; in ath5k_txq_setup()
1071 ath5k_beaconq_setup(struct ath5k_hw *ah) in ath5k_beaconq_setup() argument
1083 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi); in ath5k_beaconq_setup()
1087 ath5k_beaconq_config(struct ath5k_hw *ah) in ath5k_beaconq_config() argument
1092 ret = ath5k_hw_get_tx_queueprops(ah, ah->bhalq, &qi); in ath5k_beaconq_config()
1096 if (ah->opmode == NL80211_IFTYPE_AP || in ath5k_beaconq_config()
1097 ah->opmode == NL80211_IFTYPE_MESH_POINT) { in ath5k_beaconq_config()
1105 } else if (ah->opmode == NL80211_IFTYPE_ADHOC) { in ath5k_beaconq_config()
1114 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, in ath5k_beaconq_config()
1118 ret = ath5k_hw_set_tx_queueprops(ah, ah->bhalq, &qi); in ath5k_beaconq_config()
1120 ATH5K_ERR(ah, "%s: unable to update parameters for beacon " in ath5k_beaconq_config()
1124 ret = ath5k_hw_reset_tx_queue(ah, ah->bhalq); /* push to h/w */ in ath5k_beaconq_config()
1129 ret = ath5k_hw_get_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi); in ath5k_beaconq_config()
1133 qi.tqi_ready_time = (ah->bintval * 80) / 100; in ath5k_beaconq_config()
1134 ret = ath5k_hw_set_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi); in ath5k_beaconq_config()
1138 ret = ath5k_hw_reset_tx_queue(ah, AR5K_TX_QUEUE_ID_CAB); in ath5k_beaconq_config()
1144 * ath5k_drain_tx_buffs - Empty tx buffers
1146 * @ah: The &struct ath5k_hw
1155 ath5k_drain_tx_buffs(struct ath5k_hw *ah) in ath5k_drain_tx_buffs() argument
1161 for (i = 0; i < ARRAY_SIZE(ah->txqs); i++) { in ath5k_drain_tx_buffs()
1162 if (ah->txqs[i].setup) { in ath5k_drain_tx_buffs()
1163 txq = &ah->txqs[i]; in ath5k_drain_tx_buffs()
1164 spin_lock_bh(&txq->lock); in ath5k_drain_tx_buffs()
1165 list_for_each_entry_safe(bf, bf0, &txq->q, list) { in ath5k_drain_tx_buffs()
1166 ath5k_debug_printtxbuf(ah, bf); in ath5k_drain_tx_buffs()
1168 ath5k_txbuf_free_skb(ah, bf); in ath5k_drain_tx_buffs()
1170 spin_lock(&ah->txbuflock); in ath5k_drain_tx_buffs()
1171 list_move_tail(&bf->list, &ah->txbuf); in ath5k_drain_tx_buffs()
1172 ah->txbuf_len++; in ath5k_drain_tx_buffs()
1173 txq->txq_len--; in ath5k_drain_tx_buffs()
1174 spin_unlock(&ah->txbuflock); in ath5k_drain_tx_buffs()
1176 txq->link = NULL; in ath5k_drain_tx_buffs()
1177 txq->txq_poll_mark = false; in ath5k_drain_tx_buffs()
1178 spin_unlock_bh(&txq->lock); in ath5k_drain_tx_buffs()
1184 ath5k_txq_release(struct ath5k_hw *ah) in ath5k_txq_release() argument
1186 struct ath5k_txq *txq = ah->txqs; in ath5k_txq_release()
1189 for (i = 0; i < ARRAY_SIZE(ah->txqs); i++, txq++) in ath5k_txq_release()
1190 if (txq->setup) { in ath5k_txq_release()
1191 ath5k_hw_release_tx_queue(ah, txq->qnum); in ath5k_txq_release()
1192 txq->setup = false; in ath5k_txq_release()
1205 ath5k_rx_start(struct ath5k_hw *ah) in ath5k_rx_start() argument
1207 struct ath_common *common = ath5k_hw_common(ah); in ath5k_rx_start()
1211 common->rx_bufsize = roundup(IEEE80211_MAX_FRAME_LEN, common->cachelsz); in ath5k_rx_start()
1213 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n", in ath5k_rx_start()
1214 common->cachelsz, common->rx_bufsize); in ath5k_rx_start()
1216 spin_lock_bh(&ah->rxbuflock); in ath5k_rx_start()
1217 ah->rxlink = NULL; in ath5k_rx_start()
1218 list_for_each_entry(bf, &ah->rxbuf, list) { in ath5k_rx_start()
1219 ret = ath5k_rxbuf_setup(ah, bf); in ath5k_rx_start()
1221 spin_unlock_bh(&ah->rxbuflock); in ath5k_rx_start()
1225 bf = list_first_entry(&ah->rxbuf, struct ath5k_buf, list); in ath5k_rx_start()
1226 ath5k_hw_set_rxdp(ah, bf->daddr); in ath5k_rx_start()
1227 spin_unlock_bh(&ah->rxbuflock); in ath5k_rx_start()
1229 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */ in ath5k_rx_start()
1230 ath5k_update_bssid_mask_and_opmode(ah, NULL); /* set filters, etc. */ in ath5k_rx_start()
1231 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */ in ath5k_rx_start()
1246 ath5k_rx_stop(struct ath5k_hw *ah) in ath5k_rx_stop() argument
1249 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */ in ath5k_rx_stop()
1250 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */ in ath5k_rx_stop()
1252 ath5k_debug_printrxbuffs(ah); in ath5k_rx_stop()
1256 ath5k_rx_decrypted(struct ath5k_hw *ah, struct sk_buff *skb, in ath5k_rx_decrypted() argument
1259 struct ath_common *common = ath5k_hw_common(ah); in ath5k_rx_decrypted()
1260 struct ieee80211_hdr *hdr = (void *)skb->data; in ath5k_rx_decrypted()
1263 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) && in ath5k_rx_decrypted()
1264 rs->rs_keyix != AR5K_RXKEYIX_INVALID) in ath5k_rx_decrypted()
1270 hlen = ieee80211_hdrlen(hdr->frame_control); in ath5k_rx_decrypted()
1271 if (ieee80211_has_protected(hdr->frame_control) && in ath5k_rx_decrypted()
1272 !(rs->rs_status & AR5K_RXERR_DECRYPT) && in ath5k_rx_decrypted()
1273 skb->len >= hlen + 4) { in ath5k_rx_decrypted()
1274 keyix = skb->data[hlen + 3] >> 6; in ath5k_rx_decrypted()
1276 if (test_bit(keyix, common->keymap)) in ath5k_rx_decrypted()
1285 ath5k_check_ibss_tsf(struct ath5k_hw *ah, struct sk_buff *skb, in ath5k_check_ibss_tsf() argument
1290 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data; in ath5k_check_ibss_tsf()
1292 if (le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS) { in ath5k_check_ibss_tsf()
1298 tsf = ath5k_hw_get_tsf64(ah); in ath5k_check_ibss_tsf()
1299 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp); in ath5k_check_ibss_tsf()
1302 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, in ath5k_check_ibss_tsf()
1305 (unsigned long long)rxs->mactime, in ath5k_check_ibss_tsf()
1306 (unsigned long long)(rxs->mactime - bc_tstamp), in ath5k_check_ibss_tsf()
1320 if (bc_tstamp > rxs->mactime) { in ath5k_check_ibss_tsf()
1321 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, in ath5k_check_ibss_tsf()
1323 (unsigned long long)rxs->mactime, in ath5k_check_ibss_tsf()
1325 rxs->mactime = tsf; in ath5k_check_ibss_tsf()
1334 if (hw_tu >= ah->nexttbtt) in ath5k_check_ibss_tsf()
1335 ath5k_beacon_update_timers(ah, bc_tstamp); in ath5k_check_ibss_tsf()
1338 * update might have created a window between them - for a in ath5k_check_ibss_tsf()
1340 if (!ath5k_hw_check_beacon_timers(ah, ah->bintval)) { in ath5k_check_ibss_tsf()
1341 ath5k_beacon_update_timers(ah, bc_tstamp); in ath5k_check_ibss_tsf()
1342 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, in ath5k_check_ibss_tsf()
1353 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; in ath5k_common_padpos()
1354 __le16 frame_control = hdr->frame_control; in ath5k_common_padpos()
1368 * bytes added, or -1 if we don't have enough header room.
1375 if (padsize && skb->len > padpos) { in ath5k_add_padding()
1378 return -1; in ath5k_add_padding()
1381 memmove(skb->data, skb->data + padsize, padpos); in ath5k_add_padding()
1389 * The MAC header is padded to have 32-bit boundary if the
1390 * packet payload is non-zero. The general calculation for
1392 * padsize = 4 - (hdrlen & 3); however, since only
1393 * even-length headers are used, padding can only be 0 or 2
1406 if (padsize && skb->len >= padpos + padsize) { in ath5k_remove_padding()
1407 memmove(skb->data + padsize, skb->data, padpos); in ath5k_remove_padding()
1416 ath5k_receive_frame(struct ath5k_hw *ah, struct sk_buff *skb, in ath5k_receive_frame() argument
1420 struct ath_common *common = ath5k_hw_common(ah); in ath5k_receive_frame()
1426 rxs->flag = 0; in ath5k_receive_frame()
1427 if (unlikely(rs->rs_status & AR5K_RXERR_MIC)) in ath5k_receive_frame()
1428 rxs->flag |= RX_FLAG_MMIC_ERROR; in ath5k_receive_frame()
1429 if (unlikely(rs->rs_status & AR5K_RXERR_CRC)) in ath5k_receive_frame()
1430 rxs->flag |= RX_FLAG_FAILED_FCS_CRC; in ath5k_receive_frame()
1442 rxs->mactime = ath5k_extend_tsf(ah, rs->rs_tstamp); in ath5k_receive_frame()
1443 rxs->flag |= RX_FLAG_MACTIME_END; in ath5k_receive_frame()
1445 rxs->freq = ah->curchan->center_freq; in ath5k_receive_frame()
1446 rxs->band = ah->curchan->band; in ath5k_receive_frame()
1448 rxs->signal = ah->ah_noise_floor + rs->rs_rssi; in ath5k_receive_frame()
1450 rxs->antenna = rs->rs_antenna; in ath5k_receive_frame()
1452 if (rs->rs_antenna > 0 && rs->rs_antenna < 5) in ath5k_receive_frame()
1453 ah->stats.antenna_rx[rs->rs_antenna]++; in ath5k_receive_frame()
1455 ah->stats.antenna_rx[0]++; /* invalid */ in ath5k_receive_frame()
1457 rxs->rate_idx = ath5k_hw_to_driver_rix(ah, rs->rs_rate); in ath5k_receive_frame()
1458 rxs->flag |= ath5k_rx_decrypted(ah, skb, rs); in ath5k_receive_frame()
1459 switch (ah->ah_bwmode) { in ath5k_receive_frame()
1461 rxs->bw = RATE_INFO_BW_5; in ath5k_receive_frame()
1464 rxs->bw = RATE_INFO_BW_10; in ath5k_receive_frame()
1470 if (rs->rs_rate == in ath5k_receive_frame()
1471 ah->sbands[ah->curchan->band].bitrates[rxs->rate_idx].hw_value_short) in ath5k_receive_frame()
1472 rxs->enc_flags |= RX_ENC_FLAG_SHORTPRE; in ath5k_receive_frame()
1474 trace_ath5k_rx(ah, skb); in ath5k_receive_frame()
1476 if (ath_is_mybeacon(common, (struct ieee80211_hdr *)skb->data)) { in ath5k_receive_frame()
1477 ewma_beacon_rssi_add(&ah->ah_beacon_rssi_avg, rs->rs_rssi); in ath5k_receive_frame()
1480 if (ah->opmode == NL80211_IFTYPE_ADHOC) in ath5k_receive_frame()
1481 ath5k_check_ibss_tsf(ah, skb, rxs); in ath5k_receive_frame()
1484 ieee80211_rx(ah->hw, skb); in ath5k_receive_frame()
1487 /** ath5k_frame_receive_ok() - Do we want to receive this frame or not?
1493 ath5k_receive_frame_ok(struct ath5k_hw *ah, struct ath5k_rx_status *rs) in ath5k_receive_frame_ok() argument
1495 ah->stats.rx_all_count++; in ath5k_receive_frame_ok()
1496 ah->stats.rx_bytes_count += rs->rs_datalen; in ath5k_receive_frame_ok()
1498 if (unlikely(rs->rs_status)) { in ath5k_receive_frame_ok()
1501 if (rs->rs_status & AR5K_RXERR_CRC) in ath5k_receive_frame_ok()
1502 ah->stats.rxerr_crc++; in ath5k_receive_frame_ok()
1503 if (rs->rs_status & AR5K_RXERR_FIFO) in ath5k_receive_frame_ok()
1504 ah->stats.rxerr_fifo++; in ath5k_receive_frame_ok()
1505 if (rs->rs_status & AR5K_RXERR_PHY) { in ath5k_receive_frame_ok()
1506 ah->stats.rxerr_phy++; in ath5k_receive_frame_ok()
1507 if (rs->rs_phyerr > 0 && rs->rs_phyerr < 32) in ath5k_receive_frame_ok()
1508 ah->stats.rxerr_phy_code[rs->rs_phyerr]++; in ath5k_receive_frame_ok()
1516 if (rs->rs_phyerr == AR5K_RX_PHY_ERROR_OFDM_RESTART || in ath5k_receive_frame_ok()
1517 rs->rs_phyerr == AR5K_RX_PHY_ERROR_CCK_RESTART) { in ath5k_receive_frame_ok()
1518 rs->rs_status |= AR5K_RXERR_CRC; in ath5k_receive_frame_ok()
1519 rs->rs_status &= ~AR5K_RXERR_PHY; in ath5k_receive_frame_ok()
1524 if (rs->rs_status & AR5K_RXERR_DECRYPT) { in ath5k_receive_frame_ok()
1535 ah->stats.rxerr_decrypt++; in ath5k_receive_frame_ok()
1536 if (rs->rs_keyix == AR5K_RXKEYIX_INVALID && in ath5k_receive_frame_ok()
1537 !(rs->rs_status & AR5K_RXERR_CRC)) in ath5k_receive_frame_ok()
1540 if (rs->rs_status & AR5K_RXERR_MIC) { in ath5k_receive_frame_ok()
1541 ah->stats.rxerr_mic++; in ath5k_receive_frame_ok()
1546 * Reject any frames with non-crypto errors, and take into account the in ath5k_receive_frame_ok()
1550 if (ah->fif_filter_flags & FIF_FCSFAIL) in ath5k_receive_frame_ok()
1553 if (rs->rs_status & ~filters) in ath5k_receive_frame_ok()
1557 if (unlikely(rs->rs_more)) { in ath5k_receive_frame_ok()
1558 ah->stats.rxerr_jumbo++; in ath5k_receive_frame_ok()
1565 ath5k_set_current_imask(struct ath5k_hw *ah) in ath5k_set_current_imask() argument
1570 if (test_bit(ATH_STAT_RESET, ah->status)) in ath5k_set_current_imask()
1573 spin_lock_irqsave(&ah->irqlock, flags); in ath5k_set_current_imask()
1574 imask = ah->imask; in ath5k_set_current_imask()
1575 if (ah->rx_pending) in ath5k_set_current_imask()
1577 if (ah->tx_pending) in ath5k_set_current_imask()
1579 ath5k_hw_set_imr(ah, imask); in ath5k_set_current_imask()
1580 spin_unlock_irqrestore(&ah->irqlock, flags); in ath5k_set_current_imask()
1589 struct ath5k_hw *ah = from_tasklet(ah, t, rxtq); in ath5k_tasklet_rx() local
1590 struct ath_common *common = ath5k_hw_common(ah); in ath5k_tasklet_rx()
1595 spin_lock(&ah->rxbuflock); in ath5k_tasklet_rx()
1596 if (list_empty(&ah->rxbuf)) { in ath5k_tasklet_rx()
1597 ATH5K_WARN(ah, "empty rx buf pool\n"); in ath5k_tasklet_rx()
1601 bf = list_first_entry(&ah->rxbuf, struct ath5k_buf, list); in ath5k_tasklet_rx()
1602 BUG_ON(bf->skb == NULL); in ath5k_tasklet_rx()
1603 skb = bf->skb; in ath5k_tasklet_rx()
1604 ds = bf->desc; in ath5k_tasklet_rx()
1606 /* bail if HW is still using self-linked descriptor */ in ath5k_tasklet_rx()
1607 if (ath5k_hw_get_rxdp(ah) == bf->daddr) in ath5k_tasklet_rx()
1610 ret = ah->ah_proc_rx_desc(ah, ds, &rs); in ath5k_tasklet_rx()
1611 if (unlikely(ret == -EINPROGRESS)) in ath5k_tasklet_rx()
1614 ATH5K_ERR(ah, "error in processing rx descriptor\n"); in ath5k_tasklet_rx()
1615 ah->stats.rxerr_proc++; in ath5k_tasklet_rx()
1619 if (ath5k_receive_frame_ok(ah, &rs)) { in ath5k_tasklet_rx()
1620 next_skb = ath5k_rx_skb_alloc(ah, &next_skb_addr); in ath5k_tasklet_rx()
1623 * If we can't replace bf->skb with a new skb under in ath5k_tasklet_rx()
1629 dma_unmap_single(ah->dev, bf->skbaddr, in ath5k_tasklet_rx()
1630 common->rx_bufsize, in ath5k_tasklet_rx()
1635 ath5k_receive_frame(ah, skb, &rs); in ath5k_tasklet_rx()
1637 bf->skb = next_skb; in ath5k_tasklet_rx()
1638 bf->skbaddr = next_skb_addr; in ath5k_tasklet_rx()
1641 list_move_tail(&bf->list, &ah->rxbuf); in ath5k_tasklet_rx()
1642 } while (ath5k_rxbuf_setup(ah, bf) == 0); in ath5k_tasklet_rx()
1644 spin_unlock(&ah->rxbuflock); in ath5k_tasklet_rx()
1645 ah->rx_pending = false; in ath5k_tasklet_rx()
1646 ath5k_set_current_imask(ah); in ath5k_tasklet_rx()
1658 struct ath5k_hw *ah = hw->priv; in ath5k_tx_queue() local
1663 trace_ath5k_tx(ah, skb, txq); in ath5k_tx_queue()
1671 ATH5K_ERR(ah, "tx hdrlen not %%4: not enough" in ath5k_tx_queue()
1676 if (txq->txq_len >= txq->txq_max && in ath5k_tx_queue()
1677 txq->qnum <= AR5K_TX_QUEUE_ID_DATA_MAX) in ath5k_tx_queue()
1678 ieee80211_stop_queue(hw, txq->qnum); in ath5k_tx_queue()
1680 spin_lock_irqsave(&ah->txbuflock, flags); in ath5k_tx_queue()
1681 if (list_empty(&ah->txbuf)) { in ath5k_tx_queue()
1682 ATH5K_ERR(ah, "no further txbuf available, dropping packet\n"); in ath5k_tx_queue()
1683 spin_unlock_irqrestore(&ah->txbuflock, flags); in ath5k_tx_queue()
1687 bf = list_first_entry(&ah->txbuf, struct ath5k_buf, list); in ath5k_tx_queue()
1688 list_del(&bf->list); in ath5k_tx_queue()
1689 ah->txbuf_len--; in ath5k_tx_queue()
1690 if (list_empty(&ah->txbuf)) in ath5k_tx_queue()
1692 spin_unlock_irqrestore(&ah->txbuflock, flags); in ath5k_tx_queue()
1694 bf->skb = skb; in ath5k_tx_queue()
1696 if (ath5k_txbuf_setup(ah, bf, txq, padsize, control)) { in ath5k_tx_queue()
1697 bf->skb = NULL; in ath5k_tx_queue()
1698 spin_lock_irqsave(&ah->txbuflock, flags); in ath5k_tx_queue()
1699 list_add_tail(&bf->list, &ah->txbuf); in ath5k_tx_queue()
1700 ah->txbuf_len++; in ath5k_tx_queue()
1701 spin_unlock_irqrestore(&ah->txbuflock, flags); in ath5k_tx_queue()
1711 ath5k_tx_frame_completed(struct ath5k_hw *ah, struct sk_buff *skb, in ath5k_tx_frame_completed() argument
1720 ah->stats.tx_all_count++; in ath5k_tx_frame_completed()
1721 ah->stats.tx_bytes_count += skb->len; in ath5k_tx_frame_completed()
1724 size = min_t(int, sizeof(info->status.rates), sizeof(bf->rates)); in ath5k_tx_frame_completed()
1725 memcpy(info->status.rates, bf->rates, size); in ath5k_tx_frame_completed()
1727 tries[0] = info->status.rates[0].count; in ath5k_tx_frame_completed()
1728 tries[1] = info->status.rates[1].count; in ath5k_tx_frame_completed()
1729 tries[2] = info->status.rates[2].count; in ath5k_tx_frame_completed()
1733 for (i = 0; i < ts->ts_final_idx; i++) { in ath5k_tx_frame_completed()
1735 &info->status.rates[i]; in ath5k_tx_frame_completed()
1737 r->count = tries[i]; in ath5k_tx_frame_completed()
1740 info->status.rates[ts->ts_final_idx].count = ts->ts_final_retry; in ath5k_tx_frame_completed()
1741 info->status.rates[ts->ts_final_idx + 1].idx = -1; in ath5k_tx_frame_completed()
1743 if (unlikely(ts->ts_status)) { in ath5k_tx_frame_completed()
1744 ah->stats.ack_fail++; in ath5k_tx_frame_completed()
1745 if (ts->ts_status & AR5K_TXERR_FILT) { in ath5k_tx_frame_completed()
1746 info->flags |= IEEE80211_TX_STAT_TX_FILTERED; in ath5k_tx_frame_completed()
1747 ah->stats.txerr_filt++; in ath5k_tx_frame_completed()
1749 if (ts->ts_status & AR5K_TXERR_XRETRY) in ath5k_tx_frame_completed()
1750 ah->stats.txerr_retry++; in ath5k_tx_frame_completed()
1751 if (ts->ts_status & AR5K_TXERR_FIFO) in ath5k_tx_frame_completed()
1752 ah->stats.txerr_fifo++; in ath5k_tx_frame_completed()
1754 info->flags |= IEEE80211_TX_STAT_ACK; in ath5k_tx_frame_completed()
1755 info->status.ack_signal = ts->ts_rssi; in ath5k_tx_frame_completed()
1758 info->status.rates[ts->ts_final_idx].count++; in ath5k_tx_frame_completed()
1767 if (ts->ts_antenna > 0 && ts->ts_antenna < 5) in ath5k_tx_frame_completed()
1768 ah->stats.antenna_tx[ts->ts_antenna]++; in ath5k_tx_frame_completed()
1770 ah->stats.antenna_tx[0]++; /* invalid */ in ath5k_tx_frame_completed()
1772 trace_ath5k_tx_complete(ah, skb, txq, ts); in ath5k_tx_frame_completed()
1773 ieee80211_tx_status_skb(ah->hw, skb); in ath5k_tx_frame_completed()
1777 ath5k_tx_processq(struct ath5k_hw *ah, struct ath5k_txq *txq) in ath5k_tx_processq() argument
1785 spin_lock(&txq->lock); in ath5k_tx_processq()
1786 list_for_each_entry_safe(bf, bf0, &txq->q, list) { in ath5k_tx_processq()
1788 txq->txq_poll_mark = false; in ath5k_tx_processq()
1791 if (bf->skb != NULL) { in ath5k_tx_processq()
1792 ds = bf->desc; in ath5k_tx_processq()
1794 ret = ah->ah_proc_tx_desc(ah, ds, &ts); in ath5k_tx_processq()
1795 if (unlikely(ret == -EINPROGRESS)) in ath5k_tx_processq()
1798 ATH5K_ERR(ah, in ath5k_tx_processq()
1800 "queue %u\n", ret, txq->qnum); in ath5k_tx_processq()
1804 skb = bf->skb; in ath5k_tx_processq()
1805 bf->skb = NULL; in ath5k_tx_processq()
1807 dma_unmap_single(ah->dev, bf->skbaddr, skb->len, in ath5k_tx_processq()
1809 ath5k_tx_frame_completed(ah, skb, txq, &ts, bf); in ath5k_tx_processq()
1818 if (ath5k_hw_get_txdp(ah, txq->qnum) != bf->daddr) { in ath5k_tx_processq()
1819 spin_lock(&ah->txbuflock); in ath5k_tx_processq()
1820 list_move_tail(&bf->list, &ah->txbuf); in ath5k_tx_processq()
1821 ah->txbuf_len++; in ath5k_tx_processq()
1822 txq->txq_len--; in ath5k_tx_processq()
1823 spin_unlock(&ah->txbuflock); in ath5k_tx_processq()
1826 spin_unlock(&txq->lock); in ath5k_tx_processq()
1827 if (txq->txq_len < ATH5K_TXQ_LEN_LOW && txq->qnum < 4) in ath5k_tx_processq()
1828 ieee80211_wake_queue(ah->hw, txq->qnum); in ath5k_tx_processq()
1835 struct ath5k_hw *ah = from_tasklet(ah, t, txtq); in ath5k_tasklet_tx() local
1838 if (ah->txqs[i].setup && (ah->ah_txq_isr_txok_all & BIT(i))) in ath5k_tasklet_tx()
1839 ath5k_tx_processq(ah, &ah->txqs[i]); in ath5k_tasklet_tx()
1841 ah->tx_pending = false; in ath5k_tasklet_tx()
1842 ath5k_set_current_imask(ah); in ath5k_tasklet_tx()
1854 ath5k_beacon_setup(struct ath5k_hw *ah, struct ath5k_buf *bf) in ath5k_beacon_setup() argument
1856 struct sk_buff *skb = bf->skb; in ath5k_beacon_setup()
1864 bf->skbaddr = dma_map_single(ah->dev, skb->data, skb->len, in ath5k_beacon_setup()
1866 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] " in ath5k_beacon_setup()
1867 "skbaddr %llx\n", skb, skb->data, skb->len, in ath5k_beacon_setup()
1868 (unsigned long long)bf->skbaddr); in ath5k_beacon_setup()
1870 if (dma_mapping_error(ah->dev, bf->skbaddr)) { in ath5k_beacon_setup()
1871 ATH5K_ERR(ah, "beacon DMA mapping failed\n"); in ath5k_beacon_setup()
1873 bf->skb = NULL; in ath5k_beacon_setup()
1874 return -EIO; in ath5k_beacon_setup()
1877 ds = bf->desc; in ath5k_beacon_setup()
1878 antenna = ah->ah_tx_ant; in ath5k_beacon_setup()
1881 if (ah->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) { in ath5k_beacon_setup()
1882 ds->ds_link = bf->daddr; /* self-linked */ in ath5k_beacon_setup()
1885 ds->ds_link = 0; in ath5k_beacon_setup()
1899 * multiple antennas (1 omni -- the default -- and 14 in ath5k_beacon_setup()
1905 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP) in ath5k_beacon_setup()
1906 antenna = ah->bsent & 4 ? 2 : 1; in ath5k_beacon_setup()
1910 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta in ath5k_beacon_setup()
1912 ds->ds_data = bf->skbaddr; in ath5k_beacon_setup()
1913 ret = ah->ah_setup_tx_desc(ah, ds, skb->len, in ath5k_beacon_setup()
1916 (ah->ah_txpower.txp_requested * 2), in ath5k_beacon_setup()
1917 ieee80211_get_tx_rate(ah->hw, info)->hw_value, in ath5k_beacon_setup()
1925 dma_unmap_single(ah->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE); in ath5k_beacon_setup()
1940 struct ath5k_hw *ah = hw->priv; in ath5k_beacon_update() local
1945 ret = -EINVAL; in ath5k_beacon_update()
1952 ret = -ENOMEM; in ath5k_beacon_update()
1956 avf = (void *)vif->drv_priv; in ath5k_beacon_update()
1957 ath5k_txbuf_free_skb(ah, avf->bbuf); in ath5k_beacon_update()
1958 avf->bbuf->skb = skb; in ath5k_beacon_update()
1959 ret = ath5k_beacon_setup(ah, avf->bbuf); in ath5k_beacon_update()
1973 ath5k_beacon_send(struct ath5k_hw *ah) in ath5k_beacon_send() argument
1981 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, "in beacon_send\n"); in ath5k_beacon_send()
1990 if (unlikely(ath5k_hw_num_tx_pending(ah, ah->bhalq) != 0)) { in ath5k_beacon_send()
1991 ah->bmisscount++; in ath5k_beacon_send()
1992 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, in ath5k_beacon_send()
1993 "missed %u consecutive beacons\n", ah->bmisscount); in ath5k_beacon_send()
1994 if (ah->bmisscount > 10) { /* NB: 10 is a guess */ in ath5k_beacon_send()
1995 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, in ath5k_beacon_send()
1997 ah->bmisscount); in ath5k_beacon_send()
1998 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, in ath5k_beacon_send()
2000 ieee80211_queue_work(ah->hw, &ah->reset_work); in ath5k_beacon_send()
2004 if (unlikely(ah->bmisscount != 0)) { in ath5k_beacon_send()
2005 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, in ath5k_beacon_send()
2007 ah->bmisscount); in ath5k_beacon_send()
2008 ah->bmisscount = 0; in ath5k_beacon_send()
2011 if ((ah->opmode == NL80211_IFTYPE_AP && ah->num_ap_vifs + in ath5k_beacon_send()
2012 ah->num_mesh_vifs > 1) || in ath5k_beacon_send()
2013 ah->opmode == NL80211_IFTYPE_MESH_POINT) { in ath5k_beacon_send()
2014 u64 tsf = ath5k_hw_get_tsf64(ah); in ath5k_beacon_send()
2016 int slot = ((tsftu % ah->bintval) * ATH_BCBUF) / ah->bintval; in ath5k_beacon_send()
2017 vif = ah->bslot[(slot + 1) % ATH_BCBUF]; in ath5k_beacon_send()
2018 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, in ath5k_beacon_send()
2020 (unsigned long long)tsf, tsftu, ah->bintval, slot, vif); in ath5k_beacon_send()
2022 vif = ah->bslot[0]; in ath5k_beacon_send()
2027 avf = (void *)vif->drv_priv; in ath5k_beacon_send()
2028 bf = avf->bbuf; in ath5k_beacon_send()
2035 if (unlikely(ath5k_hw_stop_beacon_queue(ah, ah->bhalq))) { in ath5k_beacon_send()
2036 ATH5K_WARN(ah, "beacon queue %u didn't start/stop ?\n", ah->bhalq); in ath5k_beacon_send()
2041 if (ah->opmode == NL80211_IFTYPE_AP || in ath5k_beacon_send()
2042 ah->opmode == NL80211_IFTYPE_MESH_POINT) { in ath5k_beacon_send()
2043 err = ath5k_beacon_update(ah->hw, vif); in ath5k_beacon_send()
2048 if (unlikely(bf->skb == NULL || ah->opmode == NL80211_IFTYPE_STATION || in ath5k_beacon_send()
2049 ah->opmode == NL80211_IFTYPE_MONITOR)) { in ath5k_beacon_send()
2050 ATH5K_WARN(ah, "bf=%p bf_skb=%p\n", bf, bf->skb); in ath5k_beacon_send()
2054 trace_ath5k_tx(ah, bf->skb, &ah->txqs[ah->bhalq]); in ath5k_beacon_send()
2056 ath5k_hw_set_txdp(ah, ah->bhalq, bf->daddr); in ath5k_beacon_send()
2057 ath5k_hw_start_tx_dma(ah, ah->bhalq); in ath5k_beacon_send()
2058 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n", in ath5k_beacon_send()
2059 ah->bhalq, (unsigned long long)bf->daddr, bf->desc); in ath5k_beacon_send()
2061 skb = ieee80211_get_buffered_bc(ah->hw, vif); in ath5k_beacon_send()
2063 ath5k_tx_queue(ah->hw, skb, ah->cabq, NULL); in ath5k_beacon_send()
2065 if (ah->cabq->txq_len >= ah->cabq->txq_max) in ath5k_beacon_send()
2068 skb = ieee80211_get_buffered_bc(ah->hw, vif); in ath5k_beacon_send()
2071 ah->bsent++; in ath5k_beacon_send()
2075 * ath5k_beacon_update_timers - update beacon timers
2077 * @ah: struct ath5k_hw pointer we are operating on
2078 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2091 ath5k_beacon_update_timers(struct ath5k_hw *ah, u64 bc_tsf) in ath5k_beacon_update_timers() argument
2096 intval = ah->bintval & AR5K_BEACON_PERIOD; in ath5k_beacon_update_timers()
2097 if (ah->opmode == NL80211_IFTYPE_AP && ah->num_ap_vifs in ath5k_beacon_update_timers()
2098 + ah->num_mesh_vifs > 1) { in ath5k_beacon_update_timers()
2099 intval /= ATH_BCBUF; /* staggered multi-bss beacons */ in ath5k_beacon_update_timers()
2101 ATH5K_WARN(ah, "intval %u is too low, min 15\n", in ath5k_beacon_update_timers()
2111 hw_tsf = ath5k_hw_get_tsf64(ah); in ath5k_beacon_update_timers()
2119 if (bc_tsf == -1) { in ath5k_beacon_update_timers()
2140 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, in ath5k_beacon_update_timers()
2151 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval); in ath5k_beacon_update_timers()
2155 ah->nexttbtt = nexttbtt; in ath5k_beacon_update_timers()
2158 ath5k_hw_init_beacon_timers(ah, nexttbtt, intval); in ath5k_beacon_update_timers()
2164 if (bc_tsf == -1) in ath5k_beacon_update_timers()
2165 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, in ath5k_beacon_update_timers()
2168 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, in ath5k_beacon_update_timers()
2171 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, in ath5k_beacon_update_timers()
2174 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, in ath5k_beacon_update_timers()
2178 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, "intval %u %s %s\n", in ath5k_beacon_update_timers()
2185 * ath5k_beacon_config - Configure the beacon queues and interrupts
2187 * @ah: struct ath5k_hw pointer we are operating on
2189 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2193 ath5k_beacon_config(struct ath5k_hw *ah) in ath5k_beacon_config() argument
2195 spin_lock_bh(&ah->block); in ath5k_beacon_config()
2196 ah->bmisscount = 0; in ath5k_beacon_config()
2197 ah->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA); in ath5k_beacon_config()
2199 if (ah->enable_beacon) { in ath5k_beacon_config()
2201 * In IBSS mode we use a self-linked tx descriptor and let the in ath5k_beacon_config()
2207 ath5k_beaconq_config(ah); in ath5k_beacon_config()
2209 ah->imask |= AR5K_INT_SWBA; in ath5k_beacon_config()
2211 if (ah->opmode == NL80211_IFTYPE_ADHOC) { in ath5k_beacon_config()
2212 if (ath5k_hw_hasveol(ah)) in ath5k_beacon_config()
2213 ath5k_beacon_send(ah); in ath5k_beacon_config()
2215 ath5k_beacon_update_timers(ah, -1); in ath5k_beacon_config()
2217 ath5k_hw_stop_beacon_queue(ah, ah->bhalq); in ath5k_beacon_config()
2220 ath5k_hw_set_imr(ah, ah->imask); in ath5k_beacon_config()
2221 spin_unlock_bh(&ah->block); in ath5k_beacon_config()
2226 struct ath5k_hw *ah = from_tasklet(ah, t, beacontq); in ath5k_tasklet_beacon() local
2229 * Software beacon alert--time to send a beacon. in ath5k_tasklet_beacon()
2236 if (ah->opmode == NL80211_IFTYPE_ADHOC) { in ath5k_tasklet_beacon()
2238 u64 tsf = ath5k_hw_get_tsf64(ah); in ath5k_tasklet_beacon()
2239 ah->nexttbtt += ah->bintval; in ath5k_tasklet_beacon()
2240 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, in ath5k_tasklet_beacon()
2243 ah->nexttbtt, in ath5k_tasklet_beacon()
2247 spin_lock(&ah->block); in ath5k_tasklet_beacon()
2248 ath5k_beacon_send(ah); in ath5k_tasklet_beacon()
2249 spin_unlock(&ah->block); in ath5k_tasklet_beacon()
2259 ath5k_intr_calibration_poll(struct ath5k_hw *ah) in ath5k_intr_calibration_poll() argument
2261 if (time_is_before_eq_jiffies(ah->ah_cal_next_ani) && in ath5k_intr_calibration_poll()
2262 !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL) && in ath5k_intr_calibration_poll()
2263 !(ah->ah_cal_mask & AR5K_CALIBRATION_SHORT)) { in ath5k_intr_calibration_poll()
2267 ah->ah_cal_next_ani = jiffies + in ath5k_intr_calibration_poll()
2269 tasklet_schedule(&ah->ani_tasklet); in ath5k_intr_calibration_poll()
2271 } else if (time_is_before_eq_jiffies(ah->ah_cal_next_short) && in ath5k_intr_calibration_poll()
2272 !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL) && in ath5k_intr_calibration_poll()
2273 !(ah->ah_cal_mask & AR5K_CALIBRATION_SHORT)) { in ath5k_intr_calibration_poll()
2282 ah->ah_cal_next_short = jiffies + in ath5k_intr_calibration_poll()
2284 ieee80211_queue_work(ah->hw, &ah->calib_work); in ath5k_intr_calibration_poll()
2288 * AR5K_REG_ENABLE_BITS(ah, AR5K_CR, AR5K_CR_SWI); */ in ath5k_intr_calibration_poll()
2292 ath5k_schedule_rx(struct ath5k_hw *ah) in ath5k_schedule_rx() argument
2294 ah->rx_pending = true; in ath5k_schedule_rx()
2295 tasklet_schedule(&ah->rxtq); in ath5k_schedule_rx()
2299 ath5k_schedule_tx(struct ath5k_hw *ah) in ath5k_schedule_tx() argument
2301 ah->tx_pending = true; in ath5k_schedule_tx()
2302 tasklet_schedule(&ah->txtq); in ath5k_schedule_tx()
2308 struct ath5k_hw *ah = dev_id; in ath5k_intr() local
2323 if (unlikely(test_bit(ATH_STAT_INVALID, ah->status) || in ath5k_intr()
2324 ((ath5k_get_bus_type(ah) != ATH_AHB) && in ath5k_intr()
2325 !ath5k_hw_is_intr_pending(ah)))) in ath5k_intr()
2330 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */ in ath5k_intr()
2332 ATH5K_DBG(ah, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n", in ath5k_intr()
2333 status, ah->imask); in ath5k_intr()
2336 * Fatal hw error -> Log and reset in ath5k_intr()
2344 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, in ath5k_intr()
2346 ieee80211_queue_work(ah->hw, &ah->reset_work); in ath5k_intr()
2349 * RX Overrun -> Count and reset if needed in ath5k_intr()
2363 ah->stats.rxorn_intr++; in ath5k_intr()
2365 if (ah->ah_mac_srev < AR5K_SREV_AR5212) { in ath5k_intr()
2366 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, in ath5k_intr()
2368 ieee80211_queue_work(ah->hw, &ah->reset_work); in ath5k_intr()
2370 ath5k_schedule_rx(ah); in ath5k_intr()
2374 /* Software Beacon Alert -> Schedule beacon tasklet */ in ath5k_intr()
2376 tasklet_hi_schedule(&ah->beacontq); in ath5k_intr()
2379 * No more RX descriptors -> Just count in ath5k_intr()
2381 * NB: the hardware should re-read the link when in ath5k_intr()
2386 ah->stats.rxeol_intr++; in ath5k_intr()
2389 /* TX Underrun -> Bump tx trigger level */ in ath5k_intr()
2391 ath5k_hw_update_tx_triglevel(ah, true); in ath5k_intr()
2393 /* RX -> Schedule rx tasklet */ in ath5k_intr()
2395 ath5k_schedule_rx(ah); in ath5k_intr()
2397 /* TX -> Schedule tx tasklet */ in ath5k_intr()
2402 ath5k_schedule_tx(ah); in ath5k_intr()
2404 /* Missed beacon -> TODO in ath5k_intr()
2408 /* MIB event -> Update counters and notify ANI */ in ath5k_intr()
2410 ah->stats.mib_intr++; in ath5k_intr()
2411 ath5k_hw_update_mib_counters(ah); in ath5k_intr()
2412 ath5k_ani_mib_intr(ah); in ath5k_intr()
2415 /* GPIO -> Notify RFKill layer */ in ath5k_intr()
2417 tasklet_schedule(&ah->rf_kill.toggleq); in ath5k_intr()
2421 if (ath5k_get_bus_type(ah) == ATH_AHB) in ath5k_intr()
2424 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0); in ath5k_intr()
2429 * NOTE: ah->(rx/tx)_pending are set when scheduling the tasklets in ath5k_intr()
2432 if (ah->rx_pending || ah->tx_pending) in ath5k_intr()
2433 ath5k_set_current_imask(ah); in ath5k_intr()
2436 ATH5K_WARN(ah, "too many interrupts, giving up for now\n"); in ath5k_intr()
2439 ath5k_intr_calibration_poll(ah); in ath5k_intr()
2451 struct ath5k_hw *ah = container_of(work, struct ath5k_hw, in ath5k_calibrate_work() local
2455 if (time_is_before_eq_jiffies(ah->ah_cal_next_full)) { in ath5k_calibrate_work()
2457 ah->ah_cal_next_full = jiffies + in ath5k_calibrate_work()
2459 ah->ah_cal_mask |= AR5K_CALIBRATION_FULL; in ath5k_calibrate_work()
2461 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, in ath5k_calibrate_work()
2464 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) { in ath5k_calibrate_work()
2469 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, in ath5k_calibrate_work()
2471 ieee80211_queue_work(ah->hw, &ah->reset_work); in ath5k_calibrate_work()
2474 ah->ah_cal_mask |= AR5K_CALIBRATION_SHORT; in ath5k_calibrate_work()
2477 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n", in ath5k_calibrate_work()
2478 ieee80211_frequency_to_channel(ah->curchan->center_freq), in ath5k_calibrate_work()
2479 ah->curchan->hw_value); in ath5k_calibrate_work()
2481 if (ath5k_hw_phy_calibrate(ah, ah->curchan)) in ath5k_calibrate_work()
2482 ATH5K_ERR(ah, "calibration of channel %u failed\n", in ath5k_calibrate_work()
2484 ah->curchan->center_freq)); in ath5k_calibrate_work()
2487 if (ah->ah_cal_mask & AR5K_CALIBRATION_FULL) in ath5k_calibrate_work()
2488 ah->ah_cal_mask &= ~AR5K_CALIBRATION_FULL; in ath5k_calibrate_work()
2489 else if (ah->ah_cal_mask & AR5K_CALIBRATION_SHORT) in ath5k_calibrate_work()
2490 ah->ah_cal_mask &= ~AR5K_CALIBRATION_SHORT; in ath5k_calibrate_work()
2497 struct ath5k_hw *ah = from_tasklet(ah, t, ani_tasklet); in ath5k_tasklet_ani() local
2499 ah->ah_cal_mask |= AR5K_CALIBRATION_ANI; in ath5k_tasklet_ani()
2500 ath5k_ani_calibration(ah); in ath5k_tasklet_ani()
2501 ah->ah_cal_mask &= ~AR5K_CALIBRATION_ANI; in ath5k_tasklet_ani()
2508 struct ath5k_hw *ah = container_of(work, struct ath5k_hw, in ath5k_tx_complete_poll_work() local
2514 if (!test_bit(ATH_STAT_STARTED, ah->status)) in ath5k_tx_complete_poll_work()
2517 mutex_lock(&ah->lock); in ath5k_tx_complete_poll_work()
2519 for (i = 0; i < ARRAY_SIZE(ah->txqs); i++) { in ath5k_tx_complete_poll_work()
2520 if (ah->txqs[i].setup) { in ath5k_tx_complete_poll_work()
2521 txq = &ah->txqs[i]; in ath5k_tx_complete_poll_work()
2522 spin_lock_bh(&txq->lock); in ath5k_tx_complete_poll_work()
2523 if (txq->txq_len > 1) { in ath5k_tx_complete_poll_work()
2524 if (txq->txq_poll_mark) { in ath5k_tx_complete_poll_work()
2525 ATH5K_DBG(ah, ATH5K_DEBUG_XMIT, in ath5k_tx_complete_poll_work()
2527 txq->qnum); in ath5k_tx_complete_poll_work()
2529 txq->txq_stuck++; in ath5k_tx_complete_poll_work()
2530 spin_unlock_bh(&txq->lock); in ath5k_tx_complete_poll_work()
2533 txq->txq_poll_mark = true; in ath5k_tx_complete_poll_work()
2536 spin_unlock_bh(&txq->lock); in ath5k_tx_complete_poll_work()
2541 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, in ath5k_tx_complete_poll_work()
2543 ath5k_reset(ah, NULL, true); in ath5k_tx_complete_poll_work()
2546 mutex_unlock(&ah->lock); in ath5k_tx_complete_poll_work()
2548 ieee80211_queue_delayed_work(ah->hw, &ah->tx_complete_work, in ath5k_tx_complete_poll_work()
2574 ath5k_init_ah(struct ath5k_hw *ah, const struct ath_bus_ops *bus_ops) in ath5k_init_ah() argument
2576 struct ieee80211_hw *hw = ah->hw; in ath5k_init_ah()
2582 SET_IEEE80211_DEV(hw, ah->dev); in ath5k_init_ah()
2590 hw->wiphy->interface_modes = in ath5k_init_ah()
2596 hw->wiphy->iface_combinations = &if_comb; in ath5k_init_ah()
2597 hw->wiphy->n_iface_combinations = 1; in ath5k_init_ah()
2600 hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN; in ath5k_init_ah()
2602 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_5_10_MHZ; in ath5k_init_ah()
2605 hw->wiphy->available_antennas_tx = 0x3; in ath5k_init_ah()
2606 hw->wiphy->available_antennas_rx = 0x3; in ath5k_init_ah()
2608 hw->extra_tx_headroom = 2; in ath5k_init_ah()
2610 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CQM_RSSI_LIST); in ath5k_init_ah()
2616 __set_bit(ATH_STAT_INVALID, ah->status); in ath5k_init_ah()
2618 ah->opmode = NL80211_IFTYPE_STATION; in ath5k_init_ah()
2619 ah->bintval = 1000; in ath5k_init_ah()
2620 mutex_init(&ah->lock); in ath5k_init_ah()
2621 spin_lock_init(&ah->rxbuflock); in ath5k_init_ah()
2622 spin_lock_init(&ah->txbuflock); in ath5k_init_ah()
2623 spin_lock_init(&ah->block); in ath5k_init_ah()
2624 spin_lock_init(&ah->irqlock); in ath5k_init_ah()
2627 ret = request_irq(ah->irq, ath5k_intr, IRQF_SHARED, "ath", ah); in ath5k_init_ah()
2629 ATH5K_ERR(ah, "request_irq failed\n"); in ath5k_init_ah()
2633 common = ath5k_hw_common(ah); in ath5k_init_ah()
2634 common->ops = &ath5k_common_ops; in ath5k_init_ah()
2635 common->bus_ops = bus_ops; in ath5k_init_ah()
2636 common->ah = ah; in ath5k_init_ah()
2637 common->hw = hw; in ath5k_init_ah()
2638 common->priv = ah; in ath5k_init_ah()
2639 common->clockrate = 40; in ath5k_init_ah()
2646 common->cachelsz = csz << 2; /* convert to bytes */ in ath5k_init_ah()
2648 spin_lock_init(&common->cc_lock); in ath5k_init_ah()
2651 ret = ath5k_hw_init(ah); in ath5k_init_ah()
2655 /* Set up multi-rate retry capabilities */ in ath5k_init_ah()
2656 if (ah->ah_capabilities.cap_has_mrr_support) { in ath5k_init_ah()
2657 hw->max_rates = 4; in ath5k_init_ah()
2658 hw->max_rate_tries = max(AR5K_INIT_RETRY_SHORT, in ath5k_init_ah()
2662 hw->vif_data_size = sizeof(struct ath5k_vif); in ath5k_init_ah()
2669 ATH5K_INFO(ah, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n", in ath5k_init_ah()
2670 ath5k_chip_name(AR5K_VERSION_MAC, ah->ah_mac_srev), in ath5k_init_ah()
2671 ah->ah_mac_srev, in ath5k_init_ah()
2672 ah->ah_phy_revision); in ath5k_init_ah()
2674 if (!ah->ah_single_chip) { in ath5k_init_ah()
2676 if (ah->ah_radio_5ghz_revision && in ath5k_init_ah()
2677 !ah->ah_radio_2ghz_revision) { in ath5k_init_ah()
2678 /* No 5GHz support -> report 2GHz radio */ in ath5k_init_ah()
2680 ah->ah_capabilities.cap_mode)) { in ath5k_init_ah()
2681 ATH5K_INFO(ah, "RF%s 2GHz radio found (0x%x)\n", in ath5k_init_ah()
2683 ah->ah_radio_5ghz_revision), in ath5k_init_ah()
2684 ah->ah_radio_5ghz_revision); in ath5k_init_ah()
2686 * 5GHz only cards) -> report 5GHz radio */ in ath5k_init_ah()
2688 ah->ah_capabilities.cap_mode)) { in ath5k_init_ah()
2689 ATH5K_INFO(ah, "RF%s 5GHz radio found (0x%x)\n", in ath5k_init_ah()
2691 ah->ah_radio_5ghz_revision), in ath5k_init_ah()
2692 ah->ah_radio_5ghz_revision); in ath5k_init_ah()
2695 ATH5K_INFO(ah, "RF%s multiband radio found" in ath5k_init_ah()
2698 ah->ah_radio_5ghz_revision), in ath5k_init_ah()
2699 ah->ah_radio_5ghz_revision); in ath5k_init_ah()
2702 /* Multi chip radio (RF5111 - RF2111) -> in ath5k_init_ah()
2703 * report both 2GHz/5GHz radios */ in ath5k_init_ah()
2704 else if (ah->ah_radio_5ghz_revision && in ath5k_init_ah()
2705 ah->ah_radio_2ghz_revision) { in ath5k_init_ah()
2706 ATH5K_INFO(ah, "RF%s 5GHz radio found (0x%x)\n", in ath5k_init_ah()
2708 ah->ah_radio_5ghz_revision), in ath5k_init_ah()
2709 ah->ah_radio_5ghz_revision); in ath5k_init_ah()
2710 ATH5K_INFO(ah, "RF%s 2GHz radio found (0x%x)\n", in ath5k_init_ah()
2712 ah->ah_radio_2ghz_revision), in ath5k_init_ah()
2713 ah->ah_radio_2ghz_revision); in ath5k_init_ah()
2717 ath5k_debug_init_device(ah); in ath5k_init_ah()
2720 __clear_bit(ATH_STAT_INVALID, ah->status); in ath5k_init_ah()
2724 ath5k_hw_deinit(ah); in ath5k_init_ah()
2726 free_irq(ah->irq, ah); in ath5k_init_ah()
2732 ath5k_stop_locked(struct ath5k_hw *ah) in ath5k_stop_locked() argument
2735 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "invalid %u\n", in ath5k_stop_locked()
2736 test_bit(ATH_STAT_INVALID, ah->status)); in ath5k_stop_locked()
2753 ieee80211_stop_queues(ah->hw); in ath5k_stop_locked()
2755 if (!test_bit(ATH_STAT_INVALID, ah->status)) { in ath5k_stop_locked()
2756 ath5k_led_off(ah); in ath5k_stop_locked()
2757 ath5k_hw_set_imr(ah, 0); in ath5k_stop_locked()
2758 synchronize_irq(ah->irq); in ath5k_stop_locked()
2759 ath5k_rx_stop(ah); in ath5k_stop_locked()
2760 ath5k_hw_dma_stop(ah); in ath5k_stop_locked()
2761 ath5k_drain_tx_buffs(ah); in ath5k_stop_locked()
2762 ath5k_hw_phy_disable(ah); in ath5k_stop_locked()
2770 struct ath5k_hw *ah = hw->priv; in ath5k_start() local
2771 struct ath_common *common = ath5k_hw_common(ah); in ath5k_start()
2774 mutex_lock(&ah->lock); in ath5k_start()
2776 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "mode %d\n", ah->opmode); in ath5k_start()
2782 ath5k_stop_locked(ah); in ath5k_start()
2791 ah->curchan = ah->hw->conf.chandef.chan; in ath5k_start()
2792 ah->imask = AR5K_INT_RXOK in ath5k_start()
2802 ret = ath5k_reset(ah, NULL, false); in ath5k_start()
2807 ath5k_rfkill_hw_start(ah); in ath5k_start()
2813 for (i = 0; i < common->keymax; i++) in ath5k_start()
2818 ah->ah_ack_bitrate_high = true; in ath5k_start()
2820 for (i = 0; i < ARRAY_SIZE(ah->bslot); i++) in ath5k_start()
2821 ah->bslot[i] = NULL; in ath5k_start()
2825 mutex_unlock(&ah->lock); in ath5k_start()
2827 set_bit(ATH_STAT_STARTED, ah->status); in ath5k_start()
2828 ieee80211_queue_delayed_work(ah->hw, &ah->tx_complete_work, in ath5k_start()
2834 static void ath5k_stop_tasklets(struct ath5k_hw *ah) in ath5k_stop_tasklets() argument
2836 ah->rx_pending = false; in ath5k_stop_tasklets()
2837 ah->tx_pending = false; in ath5k_stop_tasklets()
2838 tasklet_kill(&ah->rxtq); in ath5k_stop_tasklets()
2839 tasklet_kill(&ah->txtq); in ath5k_stop_tasklets()
2840 tasklet_kill(&ah->beacontq); in ath5k_stop_tasklets()
2841 tasklet_kill(&ah->ani_tasklet); in ath5k_stop_tasklets()
2845 * Stop the device, grabbing the top-level lock to protect
2852 struct ath5k_hw *ah = hw->priv; in ath5k_stop() local
2855 mutex_lock(&ah->lock); in ath5k_stop()
2856 ret = ath5k_stop_locked(ah); in ath5k_stop()
2857 if (ret == 0 && !test_bit(ATH_STAT_INVALID, ah->status)) { in ath5k_stop()
2878 ret = ath5k_hw_on_hold(ah); in ath5k_stop()
2880 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, in ath5k_stop()
2884 mutex_unlock(&ah->lock); in ath5k_stop()
2886 ath5k_stop_tasklets(ah); in ath5k_stop()
2888 clear_bit(ATH_STAT_STARTED, ah->status); in ath5k_stop()
2889 cancel_delayed_work_sync(&ah->tx_complete_work); in ath5k_stop()
2892 ath5k_rfkill_hw_stop(ah); in ath5k_stop()
2899 * This should be called with ah->lock.
2902 ath5k_reset(struct ath5k_hw *ah, struct ieee80211_channel *chan, in ath5k_reset() argument
2905 struct ath_common *common = ath5k_hw_common(ah); in ath5k_reset()
2909 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "resetting\n"); in ath5k_reset()
2911 __set_bit(ATH_STAT_RESET, ah->status); in ath5k_reset()
2913 ath5k_hw_set_imr(ah, 0); in ath5k_reset()
2914 synchronize_irq(ah->irq); in ath5k_reset()
2915 ath5k_stop_tasklets(ah); in ath5k_reset()
2920 ani_mode = ah->ani_state.ani_mode; in ath5k_reset()
2921 ath5k_ani_init(ah, ATH5K_ANI_MODE_OFF); in ath5k_reset()
2926 ath5k_drain_tx_buffs(ah); in ath5k_reset()
2929 ath5k_hw_stop_rx_pcu(ah); in ath5k_reset()
2936 ret = ath5k_hw_dma_stop(ah); in ath5k_reset()
2942 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, in ath5k_reset()
2948 ah->curchan = chan; in ath5k_reset()
2950 ret = ath5k_hw_reset(ah, ah->opmode, ah->curchan, fast, skip_pcu); in ath5k_reset()
2952 ATH5K_ERR(ah, "can't reset hardware (%d)\n", ret); in ath5k_reset()
2956 ret = ath5k_rx_start(ah); in ath5k_reset()
2958 ATH5K_ERR(ah, "can't start recv logic\n"); in ath5k_reset()
2962 ath5k_ani_init(ah, ani_mode); in ath5k_reset()
2975 ah->ah_cal_next_full = jiffies + in ath5k_reset()
2977 ah->ah_cal_next_ani = jiffies + in ath5k_reset()
2979 ah->ah_cal_next_short = jiffies + in ath5k_reset()
2982 ewma_beacon_rssi_init(&ah->ah_beacon_rssi_avg); in ath5k_reset()
2985 memset(&ah->survey, 0, sizeof(ah->survey)); in ath5k_reset()
2986 spin_lock_bh(&common->cc_lock); in ath5k_reset()
2988 memset(&common->cc_survey, 0, sizeof(common->cc_survey)); in ath5k_reset()
2989 memset(&common->cc_ani, 0, sizeof(common->cc_ani)); in ath5k_reset()
2990 spin_unlock_bh(&common->cc_lock); in ath5k_reset()
3001 /* ath5k_chan_change(ah, c); */ in ath5k_reset()
3003 __clear_bit(ATH_STAT_RESET, ah->status); in ath5k_reset()
3005 ath5k_beacon_config(ah); in ath5k_reset()
3008 ieee80211_wake_queues(ah->hw); in ath5k_reset()
3017 struct ath5k_hw *ah = container_of(work, struct ath5k_hw, in ath5k_reset_work() local
3020 mutex_lock(&ah->lock); in ath5k_reset_work()
3021 ath5k_reset(ah, NULL, true); in ath5k_reset_work()
3022 mutex_unlock(&ah->lock); in ath5k_reset_work()
3029 struct ath5k_hw *ah = hw->priv; in ath5k_init() local
3030 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah); in ath5k_init()
3044 ATH5K_ERR(ah, "can't get channels\n"); in ath5k_init()
3051 ret = ath5k_desc_alloc(ah); in ath5k_init()
3053 ATH5K_ERR(ah, "can't allocate descriptors\n"); in ath5k_init()
3063 ret = ath5k_beaconq_setup(ah); in ath5k_init()
3065 ATH5K_ERR(ah, "can't setup a beacon xmit queue\n"); in ath5k_init()
3068 ah->bhalq = ret; in ath5k_init()
3069 ah->cabq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_CAB, 0); in ath5k_init()
3070 if (IS_ERR(ah->cabq)) { in ath5k_init()
3071 ATH5K_ERR(ah, "can't setup cab queue\n"); in ath5k_init()
3072 ret = PTR_ERR(ah->cabq); in ath5k_init()
3078 if (ah->ah_capabilities.cap_queues.q_tx_num >= 6) { in ath5k_init()
3081 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VO); in ath5k_init()
3083 ATH5K_ERR(ah, "can't setup xmit queue\n"); in ath5k_init()
3087 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VI); in ath5k_init()
3089 ATH5K_ERR(ah, "can't setup xmit queue\n"); in ath5k_init()
3093 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE); in ath5k_init()
3095 ATH5K_ERR(ah, "can't setup xmit queue\n"); in ath5k_init()
3099 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK); in ath5k_init()
3101 ATH5K_ERR(ah, "can't setup xmit queue\n"); in ath5k_init()
3105 hw->queues = 4; in ath5k_init()
3108 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE); in ath5k_init()
3110 ATH5K_ERR(ah, "can't setup xmit queue\n"); in ath5k_init()
3114 hw->queues = 1; in ath5k_init()
3117 tasklet_setup(&ah->rxtq, ath5k_tasklet_rx); in ath5k_init()
3118 tasklet_setup(&ah->txtq, ath5k_tasklet_tx); in ath5k_init()
3119 tasklet_setup(&ah->beacontq, ath5k_tasklet_beacon); in ath5k_init()
3120 tasklet_setup(&ah->ani_tasklet, ath5k_tasklet_ani); in ath5k_init()
3122 INIT_WORK(&ah->reset_work, ath5k_reset_work); in ath5k_init()
3123 INIT_WORK(&ah->calib_work, ath5k_calibrate_work); in ath5k_init()
3124 INIT_DELAYED_WORK(&ah->tx_complete_work, ath5k_tx_complete_poll_work); in ath5k_init()
3126 ret = ath5k_hw_common(ah)->bus_ops->eeprom_read_mac(ah, mac); in ath5k_init()
3128 ATH5K_ERR(ah, "unable to read address from EEPROM\n"); in ath5k_init()
3134 ath5k_update_bssid_mask_and_opmode(ah, NULL); in ath5k_init()
3136 regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain; in ath5k_init()
3137 ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier); in ath5k_init()
3139 ATH5K_ERR(ah, "can't initialize regulatory system\n"); in ath5k_init()
3145 ATH5K_ERR(ah, "can't register ieee80211 hw\n"); in ath5k_init()
3150 regulatory_hint(hw->wiphy, regulatory->alpha2); in ath5k_init()
3152 ath5k_init_leds(ah); in ath5k_init()
3154 ath5k_sysfs_register(ah); in ath5k_init()
3158 ath5k_txq_release(ah); in ath5k_init()
3160 ath5k_hw_release_tx_queue(ah, ah->bhalq); in ath5k_init()
3162 ath5k_desc_free(ah); in ath5k_init()
3168 ath5k_deinit_ah(struct ath5k_hw *ah) in ath5k_deinit_ah() argument
3170 struct ieee80211_hw *hw = ah->hw; in ath5k_deinit_ah()
3186 ath5k_desc_free(ah); in ath5k_deinit_ah()
3187 ath5k_txq_release(ah); in ath5k_deinit_ah()
3188 ath5k_hw_release_tx_queue(ah, ah->bhalq); in ath5k_deinit_ah()
3189 ath5k_unregister_leds(ah); in ath5k_deinit_ah()
3191 ath5k_sysfs_unregister(ah); in ath5k_deinit_ah()
3197 ath5k_hw_deinit(ah); in ath5k_deinit_ah()
3198 free_irq(ah->irq, ah); in ath5k_deinit_ah()
3202 ath5k_any_vif_assoc(struct ath5k_hw *ah) in ath5k_any_vif_assoc() argument
3211 ah->hw, IEEE80211_IFACE_ITER_RESUME_ALL, in ath5k_any_vif_assoc()
3219 struct ath5k_hw *ah = hw->priv; in ath5k_set_beacon_filter() local
3221 rfilt = ath5k_hw_get_rx_filter(ah); in ath5k_set_beacon_filter()
3226 ath5k_hw_set_rx_filter(ah, rfilt); in ath5k_set_beacon_filter()
3227 ah->filter_flags = rfilt; in ath5k_set_beacon_filter()
3230 void _ath5k_printk(const struct ath5k_hw *ah, const char *level, in _ath5k_printk() argument
3241 if (ah && ah->hw) in _ath5k_printk()
3243 level, wiphy_name(ah->hw->wiphy), &vaf); in _ath5k_printk()