Lines Matching +full:reg +full:- +full:5 +full:ah
2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
4 * Copyright (c) 2007-2008 Matthew W. S. Bell <mentor@madwifi.org>
5 * Copyright (c) 2007-2008 Luis Rodriguez <mcgrof@winlab.rutgers.edu>
6 * Copyright (c) 2007-2008 Pavel Roskin <proski@gnu.org>
7 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
30 #include "reg.h"
40 * - Buffering of RX and TX frames (after QCU/DCUs)
42 * - Encrypting and decrypting (using the built-in engine)
44 * - Generating ACKs, RTS/CTS frames
46 * - Maintaining TSF
48 * - FCS
50 * - Updating beacon data (with TSF etc)
52 * - Generating virtual CCA
54 * - RX/Multicast filtering
56 * - BSSID filtering
58 * - Various statistics
60 * -Different operating modes: AP, STA, IBSS
64 * registers on reg.h.
75 * rate -> duration table. This mapping is hw-based so
79 * ah->ah_ack_bitrate_high to true else base rate is
83 /* Tx -> ACK */
84 /* 1Mb -> 1Mb */ { 0,
85 /* 2MB -> 2Mb */ 1,
86 /* 5.5Mb -> 2Mb */ 1,
87 /* 11Mb -> 2Mb */ 1,
88 /* 6Mb -> 6Mb */ 4,
89 /* 9Mb -> 6Mb */ 4,
90 /* 12Mb -> 12Mb */ 6,
91 /* 18Mb -> 12Mb */ 6,
92 /* 24Mb -> 24Mb */ 8,
93 /* 36Mb -> 24Mb */ 8,
94 /* 48Mb -> 24Mb */ 8,
95 /* 54Mb -> 24Mb */ 8 };
102 * ath5k_hw_get_frame_duration() - Get tx time of a frame
103 * @ah: The &struct ath5k_hw
114 ath5k_hw_get_frame_duration(struct ath5k_hw *ah, enum nl80211_band band, in ath5k_hw_get_frame_duration() argument
122 if (!ah->ah_bwmode) { in ath5k_hw_get_frame_duration()
123 __le16 raw_dur = ieee80211_generic_frame_duration(ah->hw, in ath5k_hw_get_frame_duration()
129 dur -= 96; in ath5k_hw_get_frame_duration()
134 bitrate = rate->bitrate; in ath5k_hw_get_frame_duration()
139 switch (ah->ah_bwmode) { in ath5k_hw_get_frame_duration()
172 * ath5k_hw_get_default_slottime() - Get the default slot time for current mode
173 * @ah: The &struct ath5k_hw
176 ath5k_hw_get_default_slottime(struct ath5k_hw *ah) in ath5k_hw_get_default_slottime() argument
178 struct ieee80211_channel *channel = ah->ah_current_channel; in ath5k_hw_get_default_slottime()
181 switch (ah->ah_bwmode) { in ath5k_hw_get_default_slottime()
194 if ((channel->hw_value == AR5K_MODE_11B) && !ah->ah_short_slot) in ath5k_hw_get_default_slottime()
203 * ath5k_hw_get_default_sifs() - Get the default SIFS for current mode
204 * @ah: The &struct ath5k_hw
207 ath5k_hw_get_default_sifs(struct ath5k_hw *ah) in ath5k_hw_get_default_sifs() argument
209 struct ieee80211_channel *channel = ah->ah_current_channel; in ath5k_hw_get_default_sifs()
212 switch (ah->ah_bwmode) { in ath5k_hw_get_default_sifs()
225 if (channel->band == NL80211_BAND_5GHZ) in ath5k_hw_get_default_sifs()
234 * ath5k_hw_update_mib_counters() - Update MIB counters (mac layer statistics)
235 * @ah: The &struct ath5k_hw
244 ath5k_hw_update_mib_counters(struct ath5k_hw *ah) in ath5k_hw_update_mib_counters() argument
246 struct ath5k_statistics *stats = &ah->stats; in ath5k_hw_update_mib_counters()
248 /* Read-And-Clear */ in ath5k_hw_update_mib_counters()
249 stats->ack_fail += ath5k_hw_reg_read(ah, AR5K_ACK_FAIL); in ath5k_hw_update_mib_counters()
250 stats->rts_fail += ath5k_hw_reg_read(ah, AR5K_RTS_FAIL); in ath5k_hw_update_mib_counters()
251 stats->rts_ok += ath5k_hw_reg_read(ah, AR5K_RTS_OK); in ath5k_hw_update_mib_counters()
252 stats->fcs_error += ath5k_hw_reg_read(ah, AR5K_FCS_FAIL); in ath5k_hw_update_mib_counters()
253 stats->beacons += ath5k_hw_reg_read(ah, AR5K_BEACON_CNT); in ath5k_hw_update_mib_counters()
262 * ath5k_hw_write_rate_duration() - Fill rate code to duration table
263 * @ah: The &struct ath5k_hw
278 ath5k_hw_write_rate_duration(struct ath5k_hw *ah) in ath5k_hw_write_rate_duration() argument
286 for (i = 0; i < ah->sbands[band].n_bitrates; i++) { in ath5k_hw_write_rate_duration()
287 u32 reg; in ath5k_hw_write_rate_duration() local
290 if (ah->ah_ack_bitrate_high) in ath5k_hw_write_rate_duration()
291 rate = &ah->sbands[band].bitrates[ack_rates_high[i]]; in ath5k_hw_write_rate_duration()
292 /* CCK -> 1Mb */ in ath5k_hw_write_rate_duration()
294 rate = &ah->sbands[band].bitrates[0]; in ath5k_hw_write_rate_duration()
295 /* OFDM -> 6Mb */ in ath5k_hw_write_rate_duration()
297 rate = &ah->sbands[band].bitrates[4]; in ath5k_hw_write_rate_duration()
300 reg = AR5K_RATE_DUR(rate->hw_value); in ath5k_hw_write_rate_duration()
308 tx_time = ath5k_hw_get_frame_duration(ah, band, 10, in ath5k_hw_write_rate_duration()
311 ath5k_hw_reg_write(ah, tx_time, reg); in ath5k_hw_write_rate_duration()
313 if (!(rate->flags & IEEE80211_RATE_SHORT_PREAMBLE)) in ath5k_hw_write_rate_duration()
316 tx_time = ath5k_hw_get_frame_duration(ah, band, 10, rate, true); in ath5k_hw_write_rate_duration()
317 ath5k_hw_reg_write(ah, tx_time, in ath5k_hw_write_rate_duration()
318 reg + (AR5K_SET_SHORT_PREAMBLE << 2)); in ath5k_hw_write_rate_duration()
323 * ath5k_hw_set_ack_timeout() - Set ACK timeout on PCU
324 * @ah: The &struct ath5k_hw
328 ath5k_hw_set_ack_timeout(struct ath5k_hw *ah, unsigned int timeout) in ath5k_hw_set_ack_timeout() argument
330 if (ath5k_hw_clocktoh(ah, AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_ACK)) in ath5k_hw_set_ack_timeout()
332 return -EINVAL; in ath5k_hw_set_ack_timeout()
334 AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_ACK, in ath5k_hw_set_ack_timeout()
335 ath5k_hw_htoclock(ah, timeout)); in ath5k_hw_set_ack_timeout()
341 * ath5k_hw_set_cts_timeout() - Set CTS timeout on PCU
342 * @ah: The &struct ath5k_hw
346 ath5k_hw_set_cts_timeout(struct ath5k_hw *ah, unsigned int timeout) in ath5k_hw_set_cts_timeout() argument
348 if (ath5k_hw_clocktoh(ah, AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_CTS)) in ath5k_hw_set_cts_timeout()
350 return -EINVAL; in ath5k_hw_set_cts_timeout()
352 AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_CTS, in ath5k_hw_set_cts_timeout()
353 ath5k_hw_htoclock(ah, timeout)); in ath5k_hw_set_cts_timeout()
364 * ath5k_hw_set_lladdr() - Set station id
365 * @ah: The &struct ath5k_hw
371 ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac) in ath5k_hw_set_lladdr() argument
373 struct ath_common *common = ath5k_hw_common(ah); in ath5k_hw_set_lladdr()
378 memcpy(common->macaddr, mac, ETH_ALEN); in ath5k_hw_set_lladdr()
380 pcu_reg = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 0xffff0000; in ath5k_hw_set_lladdr()
385 ath5k_hw_reg_write(ah, low_id, AR5K_STA_ID0); in ath5k_hw_set_lladdr()
386 ath5k_hw_reg_write(ah, pcu_reg | high_id, AR5K_STA_ID1); in ath5k_hw_set_lladdr()
392 * ath5k_hw_set_bssid() - Set current BSSID on hw
393 * @ah: The &struct ath5k_hw
399 ath5k_hw_set_bssid(struct ath5k_hw *ah) in ath5k_hw_set_bssid() argument
401 struct ath_common *common = ath5k_hw_common(ah); in ath5k_hw_set_bssid()
407 if (ah->ah_version == AR5K_AR5212) in ath5k_hw_set_bssid()
413 ath5k_hw_reg_write(ah, in ath5k_hw_set_bssid()
414 get_unaligned_le32(common->curbssid), in ath5k_hw_set_bssid()
416 ath5k_hw_reg_write(ah, in ath5k_hw_set_bssid()
417 get_unaligned_le16(common->curbssid + 4) | in ath5k_hw_set_bssid()
418 ((common->curaid & 0x3fff) << AR5K_BSS_ID1_AID_S), in ath5k_hw_set_bssid()
421 if (common->curaid == 0) { in ath5k_hw_set_bssid()
422 ath5k_hw_disable_pspoll(ah); in ath5k_hw_set_bssid()
426 AR5K_REG_WRITE_BITS(ah, AR5K_BEACON, AR5K_BEACON_TIM, in ath5k_hw_set_bssid()
429 ath5k_hw_enable_pspoll(ah, NULL, 0); in ath5k_hw_set_bssid()
433 * ath5k_hw_set_bssid_mask() - Filter out bssids we listen
434 * @ah: The &struct ath5k_hw
448 ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask) in ath5k_hw_set_bssid_mask() argument
450 struct ath_common *common = ath5k_hw_common(ah); in ath5k_hw_set_bssid_mask()
454 memcpy(common->bssidmask, mask, ETH_ALEN); in ath5k_hw_set_bssid_mask()
455 if (ah->ah_version == AR5K_AR5212) in ath5k_hw_set_bssid_mask()
460 * ath5k_hw_set_mcast_filter() - Set multicast filter
461 * @ah: The &struct ath5k_hw
466 ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1) in ath5k_hw_set_mcast_filter() argument
468 ath5k_hw_reg_write(ah, filter0, AR5K_MCAST_FILTER0); in ath5k_hw_set_mcast_filter()
469 ath5k_hw_reg_write(ah, filter1, AR5K_MCAST_FILTER1); in ath5k_hw_set_mcast_filter()
473 * ath5k_hw_get_rx_filter() - Get current rx filter
474 * @ah: The &struct ath5k_hw
480 * check out reg.h.
483 ath5k_hw_get_rx_filter(struct ath5k_hw *ah) in ath5k_hw_get_rx_filter() argument
487 filter = ath5k_hw_reg_read(ah, AR5K_RX_FILTER); in ath5k_hw_get_rx_filter()
490 if (ah->ah_version == AR5K_AR5212) { in ath5k_hw_get_rx_filter()
491 data = ath5k_hw_reg_read(ah, AR5K_PHY_ERR_FIL); in ath5k_hw_get_rx_filter()
503 * ath5k_hw_set_rx_filter() - Set rx filter
504 * @ah: The &struct ath5k_hw
505 * @filter: RX filter mask (see reg.h)
512 ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter) in ath5k_hw_set_rx_filter() argument
517 if (ah->ah_version == AR5K_AR5212) { in ath5k_hw_set_rx_filter()
527 if (ah->ah_version == AR5K_AR5210 && in ath5k_hw_set_rx_filter()
535 AR5K_REG_ENABLE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA); in ath5k_hw_set_rx_filter()
537 AR5K_REG_DISABLE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA); in ath5k_hw_set_rx_filter()
540 ath5k_hw_reg_write(ah, filter & 0xff, AR5K_RX_FILTER); in ath5k_hw_set_rx_filter()
543 if (ah->ah_version == AR5K_AR5212) in ath5k_hw_set_rx_filter()
544 ath5k_hw_reg_write(ah, data, AR5K_PHY_ERR_FIL); in ath5k_hw_set_rx_filter()
556 * ath5k_hw_get_tsf64() - Get the full 64bit TSF
557 * @ah: The &struct ath5k_hw
562 ath5k_hw_get_tsf64(struct ath5k_hw *ah) in ath5k_hw_get_tsf64() argument
568 /* This code is time critical - we don't want to be interrupted here */ in ath5k_hw_get_tsf64()
583 tsf_upper1 = ath5k_hw_reg_read(ah, AR5K_TSF_U32); in ath5k_hw_get_tsf64()
585 tsf_lower = ath5k_hw_reg_read(ah, AR5K_TSF_L32); in ath5k_hw_get_tsf64()
586 tsf_upper2 = ath5k_hw_reg_read(ah, AR5K_TSF_U32); in ath5k_hw_get_tsf64()
602 * ath5k_hw_set_tsf64() - Set a new 64bit TSF
603 * @ah: The &struct ath5k_hw
609 ath5k_hw_set_tsf64(struct ath5k_hw *ah, u64 tsf64) in ath5k_hw_set_tsf64() argument
611 ath5k_hw_reg_write(ah, tsf64 & 0xffffffff, AR5K_TSF_L32); in ath5k_hw_set_tsf64()
612 ath5k_hw_reg_write(ah, (tsf64 >> 32) & 0xffffffff, AR5K_TSF_U32); in ath5k_hw_set_tsf64()
616 * ath5k_hw_reset_tsf() - Force a TSF reset
617 * @ah: The &struct ath5k_hw
622 ath5k_hw_reset_tsf(struct ath5k_hw *ah) in ath5k_hw_reset_tsf() argument
626 val = ath5k_hw_reg_read(ah, AR5K_BEACON) | AR5K_BEACON_RESET_TSF; in ath5k_hw_reset_tsf()
634 ath5k_hw_reg_write(ah, val, AR5K_BEACON); in ath5k_hw_reset_tsf()
635 ath5k_hw_reg_write(ah, val, AR5K_BEACON); in ath5k_hw_reset_tsf()
639 * ath5k_hw_init_beacon_timers() - Initialize beacon timers
640 * @ah: The &struct ath5k_hw
648 ath5k_hw_init_beacon_timers(struct ath5k_hw *ah, u32 next_beacon, u32 interval) in ath5k_hw_init_beacon_timers() argument
655 switch (ah->opmode) { in ath5k_hw_init_beacon_timers()
662 if (ah->ah_version == AR5K_AR5210) { in ath5k_hw_init_beacon_timers()
670 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_PCF); in ath5k_hw_init_beacon_timers()
673 AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG, AR5K_TXCFG_ADHOC_BCN_ATIM); in ath5k_hw_init_beacon_timers()
676 /* On non-STA modes timer1 is used as next DMA in ath5k_hw_init_beacon_timers()
679 timer1 = (next_beacon - AR5K_TUNE_DMA_BEACON_RESP) << 3; in ath5k_hw_init_beacon_timers()
680 timer2 = (next_beacon - AR5K_TUNE_SW_BEACON_RESP) << 3; in ath5k_hw_init_beacon_timers()
693 if (ah->opmode == NL80211_IFTYPE_AP || in ath5k_hw_init_beacon_timers()
694 ah->opmode == NL80211_IFTYPE_MESH_POINT) in ath5k_hw_init_beacon_timers()
695 ath5k_hw_reg_write(ah, 0, AR5K_TIMER0); in ath5k_hw_init_beacon_timers()
697 ath5k_hw_reg_write(ah, next_beacon, AR5K_TIMER0); in ath5k_hw_init_beacon_timers()
698 ath5k_hw_reg_write(ah, timer1, AR5K_TIMER1); in ath5k_hw_init_beacon_timers()
699 ath5k_hw_reg_write(ah, timer2, AR5K_TIMER2); in ath5k_hw_init_beacon_timers()
700 ath5k_hw_reg_write(ah, timer3, AR5K_TIMER3); in ath5k_hw_init_beacon_timers()
704 ath5k_hw_reset_tsf(ah); in ath5k_hw_init_beacon_timers()
706 ath5k_hw_reg_write(ah, interval & (AR5K_BEACON_PERIOD | in ath5k_hw_init_beacon_timers()
711 * performing a clear-on-write operation on PISR in ath5k_hw_init_beacon_timers()
715 if (ah->ah_version == AR5K_AR5210) in ath5k_hw_init_beacon_timers()
716 ath5k_hw_reg_write(ah, AR5K_ISR_BMISS, AR5K_ISR); in ath5k_hw_init_beacon_timers()
718 ath5k_hw_reg_write(ah, AR5K_ISR_BMISS, AR5K_PISR); in ath5k_hw_init_beacon_timers()
721 * based on vif->bss_conf params, until then in ath5k_hw_init_beacon_timers()
723 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_PWR_SV); in ath5k_hw_init_beacon_timers()
728 * ath5k_check_timer_win() - Check if timer B is timer A + window
749 if ((b - a == window) || /* 1.) */ in ath5k_check_timer_win()
750 (a - b == intval - window) || /* 2.) */ in ath5k_check_timer_win()
751 ((a | 0x10000) - b == intval - window) || /* 3.) */ in ath5k_check_timer_win()
752 ((b | 0x10000) - a == window)) /* 4.) */ in ath5k_check_timer_win()
758 * ath5k_hw_check_beacon_timers() - Check if the beacon timers are correct
759 * @ah: The &struct ath5k_hw
765 * HW timer registers (TIMER0 - TIMER3), which are closely related to the
772 * at any time - this is something we can't avoid. If the TSF jumps to a
783 * updated again. But - because the beacon interval is usually not an exact
797 ath5k_hw_check_beacon_timers(struct ath5k_hw *ah, int intval) in ath5k_hw_check_beacon_timers() argument
801 nbtt = ath5k_hw_reg_read(ah, AR5K_TIMER0); in ath5k_hw_check_beacon_timers()
802 atim = ath5k_hw_reg_read(ah, AR5K_TIMER3); in ath5k_hw_check_beacon_timers()
803 dma = ath5k_hw_reg_read(ah, AR5K_TIMER1) >> 3; in ath5k_hw_check_beacon_timers()
817 * ath5k_hw_set_coverage_class() - Set IEEE 802.11 coverage class
818 * @ah: The &struct ath5k_hw
824 ath5k_hw_set_coverage_class(struct ath5k_hw *ah, u8 coverage_class) in ath5k_hw_set_coverage_class() argument
826 /* As defined by IEEE 802.11-2007 17.3.8.6 */ in ath5k_hw_set_coverage_class()
827 int slot_time = ath5k_hw_get_default_slottime(ah) + 3 * coverage_class; in ath5k_hw_set_coverage_class()
828 int ack_timeout = ath5k_hw_get_default_sifs(ah) + slot_time; in ath5k_hw_set_coverage_class()
831 ath5k_hw_set_ifs_intervals(ah, slot_time); in ath5k_hw_set_coverage_class()
832 ath5k_hw_set_ack_timeout(ah, ack_timeout); in ath5k_hw_set_coverage_class()
833 ath5k_hw_set_cts_timeout(ah, cts_timeout); in ath5k_hw_set_coverage_class()
835 ah->ah_coverage_class = coverage_class; in ath5k_hw_set_coverage_class()
843 * ath5k_hw_start_rx_pcu() - Start RX engine
844 * @ah: The &struct ath5k_hw
852 ath5k_hw_start_rx_pcu(struct ath5k_hw *ah) in ath5k_hw_start_rx_pcu() argument
854 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX); in ath5k_hw_start_rx_pcu()
858 * ath5k_hw_stop_rx_pcu() - Stop RX engine
859 * @ah: The &struct ath5k_hw
864 ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah) in ath5k_hw_stop_rx_pcu() argument
866 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX); in ath5k_hw_stop_rx_pcu()
870 * ath5k_hw_set_opmode() - Set PCU operating mode
871 * @ah: The &struct ath5k_hw
877 ath5k_hw_set_opmode(struct ath5k_hw *ah, enum nl80211_iftype op_mode) in ath5k_hw_set_opmode() argument
879 struct ath_common *common = ath5k_hw_common(ah); in ath5k_hw_set_opmode()
882 ATH5K_DBG(ah, ATH5K_DEBUG_MODE, "mode %d\n", op_mode); in ath5k_hw_set_opmode()
885 pcu_reg = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 0xffff0000; in ath5k_hw_set_opmode()
888 | (ah->ah_version == AR5K_AR5210 ? in ath5k_hw_set_opmode()
897 if (ah->ah_version == AR5K_AR5210) in ath5k_hw_set_opmode()
900 AR5K_REG_ENABLE_BITS(ah, AR5K_CFG, AR5K_CFG_IBSS); in ath5k_hw_set_opmode()
907 if (ah->ah_version == AR5K_AR5210) in ath5k_hw_set_opmode()
910 AR5K_REG_DISABLE_BITS(ah, AR5K_CFG, AR5K_CFG_IBSS); in ath5k_hw_set_opmode()
915 | (ah->ah_version == AR5K_AR5210 ? in ath5k_hw_set_opmode()
920 | (ah->ah_version == AR5K_AR5210 ? in ath5k_hw_set_opmode()
925 return -EINVAL; in ath5k_hw_set_opmode()
931 low_id = get_unaligned_le32(common->macaddr); in ath5k_hw_set_opmode()
932 high_id = get_unaligned_le16(common->macaddr + 4); in ath5k_hw_set_opmode()
933 ath5k_hw_reg_write(ah, low_id, AR5K_STA_ID0); in ath5k_hw_set_opmode()
934 ath5k_hw_reg_write(ah, pcu_reg | high_id, AR5K_STA_ID1); in ath5k_hw_set_opmode()
939 if (ah->ah_version == AR5K_AR5210) in ath5k_hw_set_opmode()
940 ath5k_hw_reg_write(ah, beacon_reg, AR5K_BCR); in ath5k_hw_set_opmode()
946 * ath5k_hw_pcu_init() - Initialize PCU
947 * @ah: The &struct ath5k_hw
954 ath5k_hw_pcu_init(struct ath5k_hw *ah, enum nl80211_iftype op_mode) in ath5k_hw_pcu_init() argument
957 ath5k_hw_set_bssid(ah); in ath5k_hw_pcu_init()
960 ath5k_hw_set_opmode(ah, op_mode); in ath5k_hw_pcu_init()
966 if (ah->ah_version == AR5K_AR5212 && in ath5k_hw_pcu_init()
967 ah->nvifs) in ath5k_hw_pcu_init()
968 ath5k_hw_write_rate_duration(ah); in ath5k_hw_pcu_init()
978 ath5k_hw_reg_write(ah, (AR5K_TUNE_RSSI_THRES | in ath5k_hw_pcu_init()
984 if (ah->ah_mac_srev >= AR5K_SREV_AR2413) { in ath5k_hw_pcu_init()
985 ath5k_hw_reg_write(ah, 0x000100aa, AR5K_MIC_QOS_CTL); in ath5k_hw_pcu_init()
986 ath5k_hw_reg_write(ah, 0x00003210, AR5K_MIC_QOS_SEL); in ath5k_hw_pcu_init()
990 if (ah->ah_version == AR5K_AR5212) { in ath5k_hw_pcu_init()
991 ath5k_hw_reg_write(ah, in ath5k_hw_pcu_init()
993 AR5K_REG_SM(5, AR5K_QOS_NOACK_BIT_OFFSET) | in ath5k_hw_pcu_init()
999 if (ah->ah_coverage_class > 0) in ath5k_hw_pcu_init()
1000 ath5k_hw_set_coverage_class(ah, ah->ah_coverage_class); in ath5k_hw_pcu_init()
1003 if (ah->ah_version == AR5K_AR5212) { in ath5k_hw_pcu_init()
1005 if (ah->ah_ack_bitrate_high) in ath5k_hw_pcu_init()
1006 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, val); in ath5k_hw_pcu_init()
1008 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, val); in ath5k_hw_pcu_init()